diff options
| author | Mylène Josserand <mylene.josserand@free-electrons.com> | 2017-01-17 15:02:22 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-17 17:42:46 +0100 |
| commit | 603a0c8af9cb23f7cf94d57e76113fef51848200 (patch) | |
| tree | 0fb26415f874bacf728d62db4c55209ff6c3d254 /drivers/clk/sunxi-ng/ccu-sun8i-a33.c | |
| parent | 70421257c068b91476e70cade15fca68045d0693 (diff) | |
clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig
The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-a33.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 94f1c8beda8d..0d513d2674cb 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -440,7 +440,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", - 0x140, BIT(31), 0); + 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 0x140, BIT(30), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", |