diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2016-12-27 00:00:38 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-01-02 14:24:57 +0100 |
| commit | cb1d9f6ddaa436f2dce2710740b7a3546700949c (patch) | |
| tree | 6195814ec1a044894fbea51b0caf6a88b3b16cee /drivers/clk/rockchip/clk.c | |
| parent | 0c744ea4f77d72b3dcebb7a8f2684633ec79be88 (diff) | |
clk: rockchip: add a clock-type for muxes based in the grf
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the general register
files. Add a clock-type that can control these as well, so that we
don't need to work around them being absent.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index b886be30f34f..3abcbf441cc5 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -417,6 +417,13 @@ void __init rockchip_clk_register_branches( list->mux_shift, list->mux_width, list->mux_flags, &ctx->lock); break; + case branch_muxgrf: + clk = rockchip_clk_register_muxgrf(list->name, + list->parent_names, list->num_parents, + flags, ctx->grf, list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags); + break; case branch_divider: if (list->div_table) clk = clk_register_divider_table(NULL, |