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-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4.cpp30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 760bc1f7ac..cdbbb55796 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -158,4 +158,34 @@ vec4_visitor::dead_code_eliminate()
return progress;
}
+void
+vec4_visitor::split_uniform_registers()
+{
+ /* Prior to this, uniforms have been in an array sized according to
+ * the number of vector uniforms present, sparsely filled (so an
+ * aggregate results in reg indices being skipped over). Now we're
+ * going to cut those aggregates up so each .reg index is one
+ * vector. The goal is to make elimination of unused uniform
+ * components easier later.
+ */
+ foreach_list(node, &this->instructions) {
+ vec4_instruction *inst = (vec4_instruction *)node;
+
+ for (int i = 0 ; i < 3; i++) {
+ if (inst->src[i].file != UNIFORM)
+ continue;
+
+ assert(!inst->src[i].reladdr);
+
+ inst->src[i].reg += inst->src[i].reg_offset;
+ inst->src[i].reg_offset = 0;
+ }
+ }
+
+ /* Update that everything is now vector-sized. */
+ for (int i = 0; i < this->uniforms; i++) {
+ this->uniform_size[i] = 1;
+ }
+}
+
} /* namespace brw */