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authorChris Wilson <chris@chris-wilson.co.uk>2017-12-06 23:03:44 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2017-12-07 13:20:28 +0000
commit2fc64acf8a4465d5eab3d6cfec9b3c1b5df30d73 (patch)
tree2a428dfa412fb68ee36e63c36cbb4b17269f3645 /tests/pm_rc6_residency.c
parent261ab6bc964081ae62a6084c335033d8a48953fd (diff)
igt/perf_pmu: Tweak wait_for_rc6, yet again
Still CI remains obstinate that RC6 is not smoothly incrementing during the sample period. Tweak the wait_for_rc6() to first wait for the initial Evaluation Interval before polling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'tests/pm_rc6_residency.c')
-rw-r--r--tests/pm_rc6_residency.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/tests/pm_rc6_residency.c b/tests/pm_rc6_residency.c
index 16f4b142..01eeaa30 100644
--- a/tests/pm_rc6_residency.c
+++ b/tests/pm_rc6_residency.c
@@ -170,13 +170,20 @@ static bool wait_for_rc6(void)
struct timespec tv = {};
unsigned long start, now;
- start = read_rc6_residency("rc6");
+ /* First wait for roughly an RC6 Evaluation Interval */
+ usleep(160 * 1000);
+
+ /* Then poll for RC6 to start ticking */
+ now = read_rc6_residency("rc6");
do {
- usleep(50);
+ start = now;
+ usleep(5000);
now = read_rc6_residency("rc6");
- } while (now == start && !igt_seconds_elapsed(&tv));
+ if (now - start > 1)
+ return true;
+ } while (!igt_seconds_elapsed(&tv));
- return now != start;
+ return false;
}
igt_main