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AgeCommit message (Expand)AuthorFilesLines
2016-12-18radv: Implement indirect dispatch for the MEC.Bas Nieuwenhuizen1-9/+17
2016-12-18radv: update vkCmdUpdateBuffer for the MEC.Bas Nieuwenhuizen1-1/+3
2016-12-18radv: Implement cache flushing for the MEC.Bas Nieuwenhuizen1-7/+29
2016-12-18radv: add semaphore supportDave Airlie3-11/+72
2016-12-18radv: pass queue index into winsys submissionDave Airlie3-5/+13
2016-12-18radv: init compute queue and avoid initing transfer queuesDave Airlie3-15/+35
2016-12-18radv/winsys: Make WaitIdle queue aware.Bas Nieuwenhuizen5-21/+38
2016-12-18radv/meta: update header infoDave Airlie1-1/+2
2016-12-18radv: hook compute clears into clear image api.Dave Airlie1-8/+33
2016-12-18radv: clear image implementation for compute queueDave Airlie3-9/+272
2016-12-18radv/meta: split clear image out into a separate layer clear functionDave Airlie1-117/+128
2016-12-18radv: implement image->image copies using compute shaderDave Airlie4-6/+343
2016-12-18radv: add a compute shader implementation for buffer to imageDave Airlie3-6/+325
2016-12-18radv: Use correct pitch for views with different block size.Bas Nieuwenhuizen1-1/+4
2016-12-18radv: Store queue family in command buffers.Dave Airlie2-2/+35
2016-12-18radv: start fixing up queue allocate for multiple queuesDave Airlie2-15/+53
2016-12-18radv/winsys: start adding support for DMA/compute queueDave Airlie1-5/+20
2016-12-18radv/winsys: Expose number of compute/dma rings.Bas Nieuwenhuizen2-2/+15
2016-12-18freedreno/a5xx: border color supportRob Clark1-3/+160
2016-12-18freedreno/a5xx: use MRT0 to import linear zsRob Clark1-5/+20
2016-12-18freedreno: fdN_gmem_restore_format() is not gen specificRob Clark8-50/+25
2016-12-18freedreno/a5xx: cargo-cult end-batch sequence more faithfullyRob Clark4-4/+39
2016-12-18freedreno/a5xx: misc fixRob Clark1-1/+1
2016-12-18freedreno/a5xx: fix (at least some) vtx formatsRob Clark1-1/+1
2016-12-18freedreno/a5xx: more formatsRob Clark1-25/+25
2016-12-18freedreno/a5xx: fixup capsRob Clark2-6/+11
2016-12-18freedreno/a5xx: fix random faults on first sysmem drawRob Clark1-0/+3
2016-12-18freedreno: update generated headersRob Clark6-17/+80
2016-12-18freedreno/a5xx: fix stride/size for mem->gmem blitsRob Clark1-5/+7
2016-12-17radv/winsys: consolidate request->fence codeDave Airlie1-22/+19
2016-12-17radv: handle fence allocation failingDave Airlie1-1/+4
2016-12-17radv: Don't bail out on pipeline create failure.Bas Nieuwenhuizen1-21/+17
2016-12-16spirv/nir: add support for ImageGatherExtendedIlia Mirkin1-7/+69
2016-12-16anv: Fix uniform and storage buffer offset alignment limits.Francisco Jerez1-2/+2
2016-12-16nir: Remove nir_array from lower_locals_to_regsThomas Helland1-9/+0
2016-12-16swr: Implement fence attached work queues for deferred deletion.Bruce Cherniak9-54/+255
2016-12-16nir: Turn imov/fmov of undef into undefTimothy Arceri1-6/+6
2016-12-15egl/x11: cleanup init codeEric Engestrom1-14/+10
2016-12-15nir/lower_tex: fix number of components in replace_gradient_with_lod()Iago Toral Quiroga1-1/+2
2016-12-15Revert "nir: Turn imov/fmov of undef into undef."Timothy Arceri1-3/+1
2016-12-14i965/vec4: Fix TCS output reads with non-zero component qualifiers.Kenneth Graunke1-5/+5
2016-12-14i965/disasm: Decode dataport constant cache control fields.Francisco Jerez1-0/+1
2016-12-14i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.Francisco Jerez4-33/+0
2016-12-14i965/fs: Drop useless access mode override from pull constant generator code.Francisco Jerez1-2/+0
2016-12-14i965/fs: Fetch one cacheline of pull constants at a time.Francisco Jerez2-19/+18
2016-12-14i965/fs: Expose arbitrary pull constant load sizes to the IR.Francisco Jerez4-27/+26
2016-12-14i965: Factor out oword block read and write message control calculation.Francisco Jerez2-12/+8
2016-12-14i965/fs: Switch to the constant cache for uniform pull constants.Francisco Jerez4-91/+36
2016-12-14i965: Let the caller of brw_set_dp_write/read_message control the target cache.Francisco Jerez3-42/+43
2016-12-14i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().Francisco Jerez1-0/+1
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