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2017-10-03intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke6-6/+36
I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-27meson: Add build Intel "anv" vulkan driverDylan Baker1-0/+59
This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> (v4)
2017-09-26intel/genxml: Convert a not-present-or-"1" dict to a set.Eric Anholt1-2/+3
I was implementing the same enum support in broadcom's gen_pack_header.py, and did this same simplification there. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-02genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke3-3/+3
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-15intel/genxml: Fix gen10 BLEND_STATE variable length packingScott D Phillips1-2/+2
BLEND_STATE packing was modified to be variable-length in: 9670124e31 genxml: Make BLEND_STATE command support variable length array. The initial gen10.xml still had the old, fixed-length style definition for BLEND_STATE. So gen10_upload_blend_state would overwrite the packed BLEND_STATE_ENTRYs with its own fixed array of all-zero entries when packing BLEND_STATE. This caused BLEND_STATE upload to not work at all. Fixes: aa416f515a ("i965/genxml: Add gen10.xml") Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-07-02intel: genxml: make a couple of enums show up in aubinatorLionel Landwerlin6-45/+47
In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-06-28genxml: Silence about a billion unused parameter warningsIan Romanick1-2/+7
v2: Use textwrap.dedent to make the source line a lot shorter. Shortening (?) the line was requested by Jason. v3: Simplify the texwrap.dedent usage. Suggested by Dylan. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-06-22genxml: fix gen5 sampler border color state.Rafael Antognolli1-20/+20
Based on the current code, gen5 and gen6 have the same sampler border color state struct. So fix the gen5 one to match gen6. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-22intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat1-0/+18
Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat1-1/+1
This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat1-1/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat1-2/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Add INSTDONE registers in gen10Anuj Phogat1-0/+115
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat1-4/+65
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-21intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli1-2/+2
In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli3-3/+3
On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli3-3/+3
"Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2-4/+4
On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2-0/+5
Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli3-3/+3
This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2-0/+2
These fields are set by brw_clip_unit, so we need them when converting to genxml. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize GS_STATE.Rafael Antognolli1-1/+1
Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-16genxml: The viewport state offset is actually an address.Rafael Antognolli1-1/+1
This fixes code generation on gen45. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16genxml: Rename fields to match gen6+.Rafael Antognolli3-3/+3
"Anti-aliasing Enable" to "Anti-Aliasing Enable". Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli3-9/+9
Rename "Use Point Width State" to "Point Width Source". It accepts the same values and has the same meaning as gen6+, so lets keep them with the same name to simplify the code. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-14genxml: Fix Gen4-5 SF_STATE "Line Width" fixed point type.Kenneth Graunke3-3/+3
It's a U3.1. It became a U3.7 on Sandybridge. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-09intel/genxml: Update genx_bits for gen10+Anuj Phogat1-4/+2
This commit adds a gen10 case to the switch statement and drops some unneeded code for handling gen numbers which doesn't work on gen10 and above. V2: Drop "z = float(z)" and the "z *= 10" lines Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09i965/cnl: Include gen10_pack.hAnuj Phogat1-0/+2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09i965/cnl: Define genX(x) and GENX(x) for gen10Anuj Phogat1-0/+3
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09i965/genxml: Add gen10.xmlJason Ekstrand1-0/+3562
V2(Anuj): Add default value for length of 3DPRIMITIVE command Add values for 'Attribute Active Component Format' Rename few fields to match gen9.xml V3 (Ander Conselvan de Oliveira) Add gen10 alias for MOCS Make 3DSTATE_CONSTANT_BODY on Gen10 use arrays Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-06-01genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke4-32/+24
This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-01genxml: Fix parsing of address fields in groups.Kenneth Graunke1-2/+2
For example, <group count="4" start="64" size="64"> <field name="Pointer" start="5" end="63" type="address"/> </group> used to generate: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer, 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer, 0); ... but now generates code with proper subscripts: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer[0], 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer[1], 0); ... Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-30genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke1-0/+30
These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova <plamena.manolova@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-29genxml: Make a SCISSOR_RECT structure on Gen4-5.Kenneth Graunke3-12/+24
Gen6+ support multiple scissor rectangles, and define a SCISSOR_RECT structure containing their dimensions. On Gen4-5, those same fields exist in SF_VIEWPORT. This patch extracts the SF_VIEWPORT fields into a SCISSOR_RECT structure. Although not a named concept on Gen4-5, it works just as well, and gives us a consistent SCISSOR_RECT structure across all generations, making it easier to reuse code. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5Jason Ekstrand1-1/+1
All of the other gens use "PARAMETERS". Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Use the right subtype for VF_STATISTICS on gen4Jason Ekstrand1-1/+1
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Iron Lake doesn't support non-normalized sampler coordinatesJason Ekstrand1-1/+0
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Add SAMPLER_STATE to gen 4.5Jason Ekstrand1-0/+63
Somehow this got missed. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5Jason Ekstrand3-3/+3
It isn't a pointer to "color calc state", that's the packet it's in. It's a pointer to the CC viewport state. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Sampler state is a pointer on gen4-5Jason Ekstrand3-9/+9
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-26intel/genxml: Suffix KSP0 fields on Iron LakeJason Ekstrand1-5/+5
Iron Lake introduced the multiple KSP thing and so you have KSP0-3. However, the genxml didn't have an index on the first "Kernel Start Pointer" or "GRF Register Count". Add one to match gen6+. While we're here, we drop the brackets from the other "GRF Register Count" fields. Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-05-26intel/genxml: Make a bunch of things offsets on gen4-5Jason Ekstrand3-15/+15
Most things on gen4-5 are addresses because we don't have dynamic state base address and we don't have instruction state base on gen4. However, whoever converted things to addresses got a little over-excited and converted too much. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-05-15genxml: Remove brackets from kernel start pointer namesMatt Turner2-7/+7
Newer Gens' names don't have the brackets. Having common names will make some later patches simpler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-05-11genxml: Add alias for MOCS.Rafael Antognolli5-0/+5
Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set the same value as the defines. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-11i965: Port Gen4-5 VS_STATE to genxml.Kenneth Graunke3-3/+3
It's actually not that much code. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-05-11genxml: Fix KSPs on Ironlake to be offsets, not pointers.Kenneth Graunke1-8/+8
We use Instruction State Base Address on Ironlake, so we want KSP to be an offset not an actual pointer. Gen4/G45 use pointers. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-04i965: Fix line width on Cherryview.Kenneth Graunke1-0/+1
We just add another field to gen8.xml for the Cherryview line width, rather than trying to replicate the gymnastics done in the Vulkan driver to use gen9 SF pack functions. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-05-03genxml: Fix 3DSTATE_DEPTH_BUFFER length on gen5.Rafael Antognolli1-3/+3
The hardware docs are wrong, but the length used in the xml is also wrong. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-05-03genxml: Update 3DSTATE_LINE_STIPPLE xml on gen6.Rafael Antognolli1-1/+1
From the PRM, Line Stipple Inverse Repeat Count is on dw2, bits 31:16, format U1.13. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-05-03genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.Rafael Antognolli2-3/+3
- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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