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2016-09-22mapi: export all GLES 3.2 functions in libGLESv2.sowip/gles32-symbolsDylan Baker1-0/+12
See commit 5921f372c89a68fac6ddefc009442721d9df4db2 for the rational of this commit. Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-22mapi: sort static_data.py functionsDylan Baker1-2/+2
Sorted by vim's builtin "sort i" (keeping the sorting case insensitive) v2: - uses case insensitive sorting (Ken) Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-22mapi: retab static_data.py to be consistentDylan Baker1-1285/+1285
This file currently uses a mixture of 3 and 4 space indent. I have changed it all to 4 space indent, matching the settings in $ROOT/.editorconfig. This was generated with sed: sed -i -e 's@^ "@ "@g' Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-22spirv: fix AtomicLoad/Store on imagesLionel Landwerlin1-10/+3
OpAtomicLoad/Store should have pointer to images just like the rest of the atomic operators. These couple of lines were poorly copied from the ssbo/shared_vars cases (the only ones currently tests by the CTS). Fixes 2afb950161f8 ("spirv/nir: Add support for OpAtomicLoad/Store") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-22nir: Allow opt_peephole_sel to be more aggressive in flattening IFs.Eric Anholt4-31/+57
VC4 was running into a major performance regression from enabling control flow in the glmark2 conditionals test, because of short if statements containing an ffract. This pass seems like it was was trying to ensure that we only flattened IFs that should be entirely a win by guaranteeing that there would be fewer bcsels than there were MOVs otherwise. However, if the number of ALU ops is small, we can avoid the overhead of branching (which itself costs cycles) and still get a win, even if it means moving real instructions out of the THEN/ELSE blocks. For now, just turn on aggressive flattening on vc4. i965 will need some tuning to avoid regressions. It does looks like this may be useful to replace freedreno code. Improves glmark2 -b conditionals:fragment-steps=5:vertex-steps=0 from 47 fps to 95 fps on vc4. vc4 shader-db: total instructions in shared programs: 101282 -> 99543 (-1.72%) instructions in affected programs: 17365 -> 15626 (-10.01%) total uniforms in shared programs: 31295 -> 31172 (-0.39%) uniforms in affected programs: 3580 -> 3457 (-3.44%) total estimated cycles in shared programs: 225182 -> 223746 (-0.64%) estimated cycles in affected programs: 26085 -> 24649 (-5.51%) v2: Update shader-db output. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
2016-09-21docs: Mark ES 3.2 "all done" for i965/gen9+.Kenneth Graunke1-1/+1
2016-09-21docs: Add ES 3.2 to release notes.Kenneth Graunke1-0/+1
2016-09-21gallium/util: add comment on util_is_format_compatible()Brian Paul1-0/+24
From reading the code, it's not obvious what is src/dest compatible. The list of a->b copy-compatible formats comes from Jose's original check-in message, with some format name updates. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-09-21svga: minor simplification in svga_validate_surface_view()Brian Paul1-3/+2
Get rid of unneeded local var. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-09-21svga: remove disable_shader debug variableBrian Paul3-10/+0
Never used, AFAIK. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-09-21i965: Enable ES 3.2 on Skylake.Kenneth Graunke1-1/+2
It's already advertised because the version.c extension checks are fulfilled, but we didn't actually claim support, so trying to create a ES 3.2 context would fail. It's all done, and the CTS results look good, so let's turn it on. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-09-21nir/spirv/glsl450: Add support for the InterpolateAt opcodesJason Ekstrand1-1/+53
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-09-21nir/spirv: Claim support for SampleRateShadingJason Ekstrand1-1/+1
We already support all of the decorations that require this capability. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-09-21nir/spirv: Bring back the spirv2nir helper binaryJason Ekstrand2-0/+73
This was something that I wrote in the early days of the spirv_to_nir code but deleted once we had a real driver. However, in the absence of a shader_runner equivalent, it's extremely useful for debugging the spirv_to_nir code so let's bring it back. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-21i965: implement querying __DRI_IMAGE_ATTRIB_OFFSET.Chuanbo Weng1-2/+7
Implement querying this attribute in intelImageExtension and bump version of intelImageExtension. Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-21egl: return corresponding offset of EGLImage instead of 0.Chuanbo Weng1-2/+9
The offset should not always be 0. For example, if EGLImage is created from a 2D texture with EGL_GL_TEXTURE_LEVEL=1, then the offset should be the actual start of miplevel 1 in bo. v2: Add version check of __DRIimageExtension implementation (Suggested by Axel Davy). v3: Don't add version check of __DRIimageExtension implementation. Set the offset only when queryImage() succeeds. (Suggested by Emil Velikov) Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [Emil Velikov: coding style fixes] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-09-21dri: add offset attribute and bump version of EGLImage extensions.Chuanbo Weng1-1/+3
Offset is useful for buffer sharing with other components, so add it to queryImage attributes. Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-21i965/ir: Test thread dispatch packing assumptions.Francisco Jerez1-0/+30
Not [originally] intended for upstream. Should cause a GPU hang if some thread is executed with a non-contiguous dispatch mask breaking assumptions of brw_stage_has_packed_dispatch(). Doesn't cause any CTS, DEQP or Piglit regressions, while replacing brw_stage_has_packed_dispatch() with a dummy implementation that unconditionally returns true on top of this patch causes multiple GPU hangs. v2: Refactor into a separate function instead of emitting the test code directly from emit_nir_code(), drop VEC4 test and clean up slightly for upstream. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-21i965/ir: Pass identity mask to brw_find_live_channel() in the packed ↵Francisco Jerez2-3/+11
dispatch case. This avoids emitting a few extra instructions required to take the dispatch mask into account when it's known to be tightly packed. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-21i965/ir: Skip eliminate_find_live_channel() for stages with sparse thread ↵Francisco Jerez3-0/+65
dispatch. The eliminate_find_live_channel optimization eliminates FIND_LIVE_CHANNEL instructions in cases where control flow is known to be uniform, and replaces them with 'MOV 0', which in turn unblocks subsequent elimination of the BROADCAST instruction frequently used on the result of FIND_LIVE_CHANNEL. This is however not correct in per-sample fragment shader dispatch because the PSD can dispatch a fully unlit sample under certain conditions. Disable the optimization in that case. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> v2: Add devinfo argument to brw_stage_has_packed_dispatch() to implement hardware generation check.
2016-09-21i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNELJason Ekstrand5-13/+50
On at least Sky Lake, ce0 does not contain the full story as far as enabled channels goes. It is possible to have completely disabled channels where the corresponding bits in ce0 are 1. In order to get the correct execution mask, you have to mask off those channels which were disabled from the beginning by taking the AND of ce0 with either sr0.2 or sr0.3 depending on the shader stage. Failure to do so can result in FIND_LIVE_CHANNEL returning a completely dead channel. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: Francisco Jerez <currojerez@riseup.net> [ Francisco Jerez: Fix a couple of typos, add mask register type assertion, clarify reason why ce0 can have bits set for disabled channels, clarify that this may only be a problem when thread dispatch doesn't pack channels tightly in the SIMD thread. Apply same treatment to Align16 path. ] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-09-21i965/reg: Make brw_sr0_reg take a subnr and return a vec1 regJason Ekstrand2-13/+9
The state register sr0 is really a collection of dwords not a SIMD8 anything. It's much more convenient for brw_sr0_reg to return the particular dword you're looking for rather than a giant blob you have to massage into what you want. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> [ Francisco Jerez: Trivial simplification of brw_ud1_reg(). ] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-09-21anv: pipeline: use correct number of thread for computeLionel Landwerlin1-1/+4
Reproduces this commit : commit 0fb85ac08d61d365e67c8f79d6955e9f89543560 Author: Kenneth Graunke <kenneth@whitecape.org> Date: Mon Jun 6 21:37:34 2016 -0700 i965: Use the correct number of threads for compute shaders. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-21anv: allocator: correct scratch space for haswellLionel Landwerlin1-1/+21
This reproduces this commit : commit 2213ffdb4bb79856f0556bdf2bfd4bdf57720232 Author: Kenneth Graunke <kenneth@whitecape.org> Date: Mon Jun 6 21:37:34 2016 -0700 i965: Allocate scratch space for the maximum number of compute threads. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-21anv: device: calculate compute thread numbers using subslices numbersLionel Landwerlin6-18/+74
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-21gallivm: support negation on 64-bit integersNicolai Hähnle1-0/+4
This should be analogous to 32-bit integers. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-21radeonsi: prepare 64-bit integer support. (v2)Dave Airlie1-7/+62
v2: - no PIPE_CAP_INT64 yet - emit DIV/MOD without the divide-by-zero workaround Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-21gallivm/llvmpipe: prepare support for ARB_gpu_shader_int64.Dave Airlie5-5/+500
This enables 64-bit integer support in gallivm and llvmpipe. v2: add conversion opcodes. v3: - PIPE_CAP_INT64 is not there yet - restrict DIV/MOD defaults to the CPU, as for 32 bits - TGSI_OPCODE_I2U64 becomes TGSI_OPCODE_U2I64 Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-21tgsi/softpipe: prepare ARB_gpu_shader_int64 support. (v3)Dave Airlie1-132/+541
This adds all the opcodes to tgsi_exec for softpipe to use. v2: add conversion opcodes. v3: - no PIPE_CAP_INT64 yet - change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64 Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-21gallium/tgsi: add support for 64-bit integer immediates.Dave Airlie7-2/+117
This adds support to TGSI for 64-bit integer immediates. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-09-21gallium: add opcode and types for 64-bit integers. (v3)Dave Airlie4-20/+362
This just adds the basic support for 64-bit opcodes, and the new types. v2: add conversion opcodes. add documentation. v3: - make docs more consistent - change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2) Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-20i965: Rename intelScreen to screen.Kenneth Graunke28-170/+170
"intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-20i965: Rename __DRIScreen pointers to "dri_screen".Kenneth Graunke6-83/+85
I want to use "screen" as the variable name for a struct intel_screen pointer. This means that we can't use it for __DRIscreen pointers. Sometimes we called it "screen", sometimes "sPriv", sometimes "driScrnPriv", and sometimes "psp" (Pointer to Screen Private?). The last one is particularly confusing because we use "psp" to refer to the Gen4 PIPELINED_STATE_POINTERS packet as well. Let's be consistent. "dri_screen" is clear, and it's not used often enough that I'm worried about the verbosity. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-09-20mesa: Implement ARB_shader_viewport_layer_array for i965Dylan Baker8-3/+20
This extension is a combination of AMD_vertex_shader_viewport_index and AMD_vertex_shader_layer, making it rather trivial to implement. For gallium I *think* this needs a new cap because of the addition of support in tessellation evaluation shaders, and since I don't have any hardware to test it on, I've left that for someone else to wire up. Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-20radeon/vce: add firmware support for version 52.8.3Leo Liu1-0/+3
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-20st/omx/dec/h265: Correct the timestampingIndrajit Das1-1/+12
(derived from commit 3b6bda665a5a890f2c98e19d2939d7de92b8cb4c) v2: fix the tabs(Leo) Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nishanth Peethambaran <nishanth.peethambaran@amd.com> Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com>
2016-09-20aubinator: add a custom handler for immediate register loadLionel Landwerlin3-3/+47
Transforming this : 0x00c77084: 0x11000001: MI_LOAD_REGISTER_IMM 0x00c77088: 0x0000b020 : Dword 1 Register Offset: 0x0000b020 0x00c7708c: 0x00880038 : Dword 2 Data DWord: 8912952 Into this: 0x007880f0: 0x11000001: MI_LOAD_REGISTER_IMM 0x007880f4: 0x0000b020 : Dword 1 Register Offset: 0x0000b020 0x007880f8: 0x00080040 : Dword 2 Data DWord: 524352 register L3CNTLREG2 (0xb020) : 0x80040 SLM Enable: 0 URB Allocation: 32 URB Low Bandwidth: 0 RO Allocation: 32 RO Low Bandwidth: 0 DC Allocation: 0 DC Low Bandwidth: 0 v2: Drop unused arguments (Sirisha) Print out register name Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-09-20st/va: flush the context before calling flush_frontbuffer(v2)Nayan Deshmukh1-1/+5
so that the texture is rendered to back buffer before calling flush_frontbuffer and can be copied to a different buffer in the function v2: change comment style Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2016-09-20st/vdpau: flush the context before calling flush_frontbufferNayan Deshmukh1-2/+5
so that the texture is rendered to back buffer before calling flush_frontbuffer and can be copied to a different buffer in the function Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2016-09-20vl/dri3: handle the case of different GPU(v4.2)Nayan Deshmukh1-13/+53
In case of prime when rendering is done on GPU other then the server GPU, use a seprate linear buffer for each back buffer which will be displayed using present extension. v2: Use a seprate linear buffer for each back buffer (Michel) v3: Change variable names and fix coding style (Leo and Emil) v4: Use PIPE_BIND_SAMPLER_VIEW for back buffer in case when a seprate linear buffer is used (Michel) v4.1: remove empty line v4.2: destroy the context and handle the case when create_context fails (Emil) Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2016-09-20st/vdpau: fix argument type to vlVdpOutputSurfaceDMABufIlia Mirkin2-2/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-19swr: [rasterizer core] Better thread destructionTim Rowley8-69/+126
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-09-19swr: [rasterizer jitter] Fix missing end-of-file newlineTim Rowley1-1/+2
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-09-19swr: [rasterizer core] Add macros for mapping ArchRast to bucketsTim Rowley11-200/+249
Switch all RDTSC_START/STOP macros to use AR_BEGIN/END macros. Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-09-19glsl: Skip "unsized arrays aren't allowed" check for TCS/TES/GS vars.Kenneth Graunke1-1/+27
Fixes ESEXT-CTS.draw_elements_base_vertex_tests.AEP_shader_stages and ESEXT-CTS.texture_cube_map_array.texture_size_tesselation_con_sh. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-19nvc0: get rid of nvc0_stage_sampler_states_bind_range()Samuel Pitoiset1-74/+9
Same thing as nvc0_stage_set_sampler_views_range(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-19nvc0: get rid of nvc0_stage_set_sampler_views_range()Samuel Pitoiset1-89/+15
This function was quite similar to nvc0_stage_set_sampler_views() and I don't see any reasons to not remove it. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-18nv50/ir: optimize SUB(a, b) to MOV(a - b)Samuel Pitoiset1-0/+10
This helps shaders in UE4 demos, especially with Elemental (+1% perf). This optimization reduces spilling usage in one shader which explains the little gain. GF100/GK104: total instructions in shared programs :2838551 -> 2838045 (-0.02%) total gprs used in shared programs :396706 -> 396684 (-0.01%) total local used in shared programs :34432 -> 34416 (-0.05%) local gpr inst bytes helped 1 19 112 112 hurt 0 0 0 0 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-18gk110/ir: fix wrong emission of OP_NOTSamuel Pitoiset1-1/+1
This should emit src0 instead of src1. Found by inspection. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
2016-09-18r600g/sb: fix struct/class declaration conflictsMartina Kollarova1-5/+1
A couple of forward-declarations were causing warnings in clang: 'value' defined as a class here but previously declared as a struct [-Wmismatched-tags] Signed-off-by: Martina Kollarova <martina.kollarova@intel.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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