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2016-12-19isl/docs: Fix line wrapping of tablefor-jasonDylan Baker1-26/+23
Some literal blocks (blocks wrapped in ``) were cut across multiple lines, which was causing sphinx to emit warnings. This make the box slightly wider so the back ticks are not split and silences sphinx.
2016-12-19gallium/docs: Remove ref to non-existent EGL sectionDylan Baker1-2/+1
2016-12-19gallium/docs: Add newlines between levels of nested listsDylan Baker1-0/+2
rst is whitespace sensitive and not putting the spaces actually manes to make the following text a block quote rather than a sublist. Cleans up another sphinx warning.
2016-12-19gallium/docs: Fix title underlines to be correct lengthDylan Baker1-14/+14
Fixes some warnings from sphinx.
2016-12-19nir/docs: use syntax highlighted code blocksDylan Baker4-14/+14
2016-12-19isl/docs: Use the code-block instead of the code commandDylan Baker3-11/+11
This fixes syntax highlighting.
2016-12-19docs: Add nir documentationDylan Baker10-452/+5
2016-12-19nir: add initial documentationConnor Abbott8-0/+1441
2016-12-19Import Jason's isl-handbook into mesaDylan Baker10-0/+1521
This imports the isl-handbook, uses pandoc (with some hand touchups) to convert the markdown into rst files, and then adds them to the sphinx documentation.
2016-12-19Create a top level sphinx structure that includes gallium docsDylan Baker37-409/+240
This make a single toplevel sphinx directory that contains the make.bat and Makefile for generating the sphinx documentation. This will be used to handle nir and isl documentation in later commits.
2016-12-19Revert "cso: don't release sampler states that are bound"Michel Dänzer1-3/+1
This reverts commit 6dc96de303290e8d1fc294da478c4f370be98dea. No longer necessary with the previous change. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19cso: Make sanitize_hash safe for samplersMichel Dänzer1-1/+43
Remove currently bound sampler states from the hash table before pruning entries from the hash table, so they cannot accidentally be deleted by the pruning. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19cso: Store hash key in struct cso_samplerMichel Dänzer2-0/+2
Preparation for following changes, no functional change intended. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19cso: Optimize cso_save/restore_fragment_samplersMichel Dänzer1-4/+17
Only copy/memset the pointers that actually need to be. v2: * Cast info->nr_samplers to int for calculating delta (Nicolai) Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19cso: Store pointers to struct cso_sampler in struct sampler_infoMichel Dänzer1-15/+18
Preparation for following changes, no functional change intended. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19cso: Don't restore nr_samplers in cso_restore_fragment_samplersMichel Dänzer1-1/+0
If info->nr_samplers > ctx->nr_fragment_samplers_saved, the assignment would prevent cso_single_sampler_done from unbinding the no longer used samplers from the driver, which could result in use-after-free. This is probably unlikely to happen in practice though. Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-19EGL/android: Enhance pbuffer implementationLiu Zhiquan1-81/+96
Some dri drivers will pass multiple bits in buffer_mask parameter to droid_image_get_buffer(), more than the actual supported buffer type combination. For such case, will go through all the bits, and will not return error when unsupported buffer is requested, only return error when the allocation for supported buffer failed. v2: coding style and log changes v3: coding style changes and update patch format Signed-off-by: Liu Zhiquan <zhiquan.liu@intel.com> Signed-off-by: Long, Zhifang <zhifang.long@intel.com> Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2016-12-18radv: Use correct workgroup size limits.Bas Nieuwenhuizen1-4/+4
Not sure where the 16k comes from, but pretty sure 2k is the max. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: expose the compute queueDave Airlie1-11/+41
v2: Don't expose the SDMA queue and use the CIK check also in the second if. (Bas) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: Only emit PFP ME syncs for DMA on the GFX queue.Bas Nieuwenhuizen1-2/+2
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Create an empty CS per ring type.Bas Nieuwenhuizen2-7/+20
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Don't enable CMASK on compute queues.Bas Nieuwenhuizen4-8/+62
We can't fast clear on compute queues. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Use RELEASE_MEM packet for MEC timestamp query.Bas Nieuwenhuizen2-9/+21
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Implement indirect dispatch for the MEC.Bas Nieuwenhuizen1-9/+17
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: update vkCmdUpdateBuffer for the MEC.Bas Nieuwenhuizen1-1/+3
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Implement cache flushing for the MEC.Bas Nieuwenhuizen1-7/+29
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: add semaphore supportDave Airlie3-11/+72
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: pass queue index into winsys submissionDave Airlie3-5/+13
This is so we can submit on separate queues if needed Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: init compute queue and avoid initing transfer queuesDave Airlie3-15/+35
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv/winsys: Make WaitIdle queue aware.Bas Nieuwenhuizen5-21/+38
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv/meta: update header infoDave Airlie1-1/+2
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: hook compute clears into clear image api.Dave Airlie1-8/+33
These aren't used yet but we will want to use them when we implement a separate compute queue. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: clear image implementation for compute queueDave Airlie3-9/+272
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv/meta: split clear image out into a separate layer clear functionDave Airlie1-117/+128
This will make it easier to add support for clears on compute queues. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: implement image->image copies using compute shaderDave Airlie4-6/+343
This is required for having a separate compute queue, we probably can't use this on GFX queue due to DCC. v2: Set coord_components = 2 for itoi texture fetch. (Bas) Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: add a compute shader implementation for buffer to imageDave Airlie3-6/+325
This implements the reverse of the current buffer->image path and can be used when we need to do image transfer on compute queues This just adds the code turned off as we don't support separate computes queues yet, and we don't want to use this path on the GFX queues for DCC reasons. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: Use correct pitch for views with different block size.Bas Nieuwenhuizen1-1/+4
Needed when accessing a comrpessed texture as R32G32B32A32 from a shader. This was not encountered previously, as we used the CB for the reinterpretation, which does not use this pitch. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18radv: Store queue family in command buffers.Dave Airlie2-2/+35
v2: Added helper (Bas) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv: start fixing up queue allocate for multiple queuesDave Airlie2-15/+53
v2: Fix error handling and zero init the device (Bas) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv/winsys: start adding support for DMA/compute queueDave Airlie1-5/+20
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-18radv/winsys: Expose number of compute/dma rings.Bas Nieuwenhuizen2-2/+15
Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-12-18freedreno/a5xx: border color supportRob Clark1-3/+160
Not 100% sure it works if you have border color in VS.. but it might be right. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: use MRT0 to import linear zsRob Clark1-5/+20
A bit of a hack, but we need to do this until we can do tiled zs in sysmem (and associated tile/until blits for transfer_map). Fixes xonotic and glmark2 "refract", when reorder wasn't enabled. (reorder would paper over the issue by avoiding the extra round- trip to system memory and back to gmem. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno: fdN_gmem_restore_format() is not gen specificRob Clark8-50/+25
Refactor out into a common helper, since this is the same across generations when we need equiv z/s gmem restore format. Next patch needs this in a5xx, rather than creating yet another helper push this into core. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: cargo-cult end-batch sequence more faithfullyRob Clark4-4/+39
Fixes some issues at least with GMEM bypass mode, where we'd sometimes end up with some FS quads not hitting memory. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: misc fixRob Clark1-1/+1
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fix (at least some) vtx formatsRob Clark1-1/+1
Swap/component-order doesn't seem to be quite what that is. At least blob was always setting it to XYZW ('11') but we weren't. Causing problems w/ formats like sint16.. Hard-coding this instead at least seems to get glamor working. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: more formatsRob Clark1-25/+25
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fixup capsRob Clark2-6/+11
Might not be 100% accurate, mostly just copy from a4xx to get started. We are defn lying about occlusion query at this point (not implemented yet) but need it to expose anything higher than gl1.4 (glamor needs gl2.1) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fix random faults on first sysmem drawRob Clark1-0/+3
Not sure what this event is, but blob writes it.. and it seems to solve random write faults at mystery address that would sometimes happen on first BYPASS draw. Signed-off-by: Rob Clark <robdclark@gmail.com>
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