diff options
Diffstat (limited to 'src/intel/isl/docs/tiling.rst')
| -rw-r--r-- | src/intel/isl/docs/tiling.rst | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/intel/isl/docs/tiling.rst b/src/intel/isl/docs/tiling.rst index bc55df96fd..e534418258 100644 --- a/src/intel/isl/docs/tiling.rst +++ b/src/intel/isl/docs/tiling.rst @@ -72,7 +72,7 @@ ISL Representation The structure of any given tiling format is represented by ISL using the ``isl_tiling`` enum and the ``isl_tile_info`` structure: -.. code:: c +.. code-block:: c enum isl_tiling { ISL_TILING_LINEAR = 0, @@ -94,10 +94,10 @@ The structure of any given tiling format is represented by ISL using the }; bool - isl_tiling_get_info(const struct isl_device \*dev, + isl_tiling_get_info(const struct isl_device *dev, enum isl_tiling tiling, uint32_t format_bpb, - struct isl_tile_info \*info); + struct isl_tile_info *info); Instead of using separate "Tile Mode" and "Tiled Resource Mode" fields like are used by the Sky Lake ``RENDER_SURFACE_STATE`` packet, ISL has a @@ -110,7 +110,7 @@ underlying format has to be passed into ``isl_tiling_get_info``. The proper way to compute the size of an image in bytes given a width and height in elements is as follows: -.. code:: c +.. code-block:: c uint32_t width_tl = DIV_ROUND_UP(width_el, tile_info.logical_extent_el.w); uint32_t height_tl = DIV_ROUND_UP(height_el, tile_info.logical_extent_el.h); @@ -193,7 +193,7 @@ Bit-6 Swizzling When bit-6 swizzling is enabled, bits 9 and 10 are XOR'd in with bit 6 of the tiled address: -.. code:: c +.. code-block:: c addr[6] ^= addr[9] ^ addr[10]; @@ -246,7 +246,7 @@ Bit-6 Swizzling When bit-6 swizzling is enabled, bit 9 is XOR'd in with bit 6 of the tiled address: -.. code:: c +.. code-block:: c addr[6] ^= addr[9]; |