diff options
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_buffer.c | 6 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 |
4 files changed, 7 insertions, 4 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 2f55653ada..2bf502012c 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -342,6 +342,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, /* TODO: Enable this once the kernel handles it efficiently. */ info->has_local_buffers = info->drm_minor >= 20 && !info->has_dedicated_vram; + info->kernel_flushes_hdp_before_ib = true; + info->num_render_backends = amdinfo->rb_pipes; info->clock_crystal_freq = amdinfo->gpu_counter_freq; if (!info->clock_crystal_freq) { @@ -484,6 +486,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle); printf(" has_ctx_priority = %u\n", info->has_ctx_priority); printf(" has_local_buffers = %u\n", info->has_local_buffers); + printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 75cb98020d..9857cd0c7a 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -96,6 +96,7 @@ struct radeon_info { bool has_fence_to_handle; bool has_ctx_priority; bool has_local_buffers; + bool kernel_flushes_hdp_before_ib; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index d17b2c6a83..beb0557e43 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -124,8 +124,7 @@ void si_init_resource_fields(struct si_screen *sscreen, /* Older kernels didn't always flush the HDP cache before * CS execution */ - if (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor < 40) { + if (!sscreen->info.kernel_flushes_hdp_before_ib) { res->domains = RADEON_DOMAIN_GTT; res->flags |= RADEON_FLAG_GTT_WC; break; @@ -152,8 +151,7 @@ void si_init_resource_fields(struct si_screen *sscreen, * ensures all CPU writes finish before the GPU * executes a command stream. */ - if (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor < 40) + if (!sscreen->info.kernel_flushes_hdp_before_ib) res->domains = RADEON_DOMAIN_GTT; } diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 253dd4e2eb..6e3162d1cf 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -528,6 +528,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->accel_working2 < 3); ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.ib_start_alignment = 4096; + ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |