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authorChad Versace <chadversary@chromium.org>2016-12-09 16:22:52 -0800
committerChad Versace <chadversary@chromium.org>2016-12-10 08:05:11 -0800
commit42011be1e27f59d750b781c10766e19ec0ee6ff5 (patch)
tree414501ee4a78845dca14f9847bd22cf84630fbcf /src
parent1c8be049bea786c2c054a770025976beba5b8636 (diff)
i965/mt: Disable HiZ when sharing depth buffer externally (v2)
intel_miptree_make_shareable() discarded and disabled CCS. Fix it so that it discards and disables HiZ too. Fixes dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer on Skylake. v2: Actually do what the commit message says. Discard the HiZ buffer. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98329 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Nanley Chery <nanley.g.chery@intel.com Cc: Haixia Shi <hshi@chromium.org> Cc: mesa-stable@lists.freedesktop.org
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c29
1 files changed, 22 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 15404dae32..c4afab94ca 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -945,6 +945,19 @@ intel_miptree_reference(struct intel_mipmap_tree **dst,
*dst = src;
}
+static void
+intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer *hiz_buf)
+{
+ if (hiz_buf == NULL)
+ return;
+
+ if (hiz_buf->mt)
+ intel_miptree_release(&hiz_buf->mt);
+ else
+ drm_intel_bo_unreference(hiz_buf->aux_base.bo);
+
+ free(hiz_buf);
+}
void
intel_miptree_release(struct intel_mipmap_tree **mt)
@@ -961,13 +974,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
drm_intel_bo_unreference((*mt)->bo);
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->r8stencil_mt);
- if ((*mt)->hiz_buf) {
- if ((*mt)->hiz_buf->mt)
- intel_miptree_release(&(*mt)->hiz_buf->mt);
- else
- drm_intel_bo_unreference((*mt)->hiz_buf->aux_base.bo);
- free((*mt)->hiz_buf);
- }
+ intel_miptree_hiz_buffer_free((*mt)->hiz_buf);
if ((*mt)->mcs_buf) {
drm_intel_bo_unreference((*mt)->mcs_buf->bo);
free((*mt)->mcs_buf);
@@ -2311,6 +2318,8 @@ intel_miptree_all_slices_resolve_color(struct brw_context *brw,
* Fast color clears are unsafe with shared buffers, so we need to resolve and
* then discard the MCS buffer, if present. We also set the no_ccs flag to
* ensure that no MCS buffer gets allocated in the future.
+ *
+ * HiZ is similarly unsafe with shared buffers.
*/
void
intel_miptree_make_shareable(struct brw_context *brw,
@@ -2331,6 +2340,12 @@ intel_miptree_make_shareable(struct brw_context *brw,
mt->mcs_buf = NULL;
}
+ if (mt->hiz_buf) {
+ intel_miptree_all_slices_resolve_depth(brw, mt);
+ intel_miptree_hiz_buffer_free(mt->hiz_buf);
+ mt->hiz_buf = NULL;
+ }
+
mt->disable_aux_buffers = true;
}