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authorIan Romanick <ian.d.romanick@intel.com>2015-05-08 12:55:00 -0700
committerIan Romanick <ian.d.romanick@intel.com>2017-10-30 09:27:09 -0700
commit6403efbe7458d05cf117adb41c8a152ed6e28bdd (patch)
tree74c392361a08b0f04895ca667d828ac7083ad304 /src/intel
parent34f7e761bc61d3086c1e4e42285c31678b256107 (diff)
glsl: Remove ir_binop_greater and ir_binop_lequal expressions
NIR does not have these instructions. TGSI and Mesa IR both implement them using < and >=, repsectively. Removing them deletes a bunch of code and means I don't have to add code to the SPIR-V generator for them. v2: Rebase on 2+ years of change... and fix a major bug added in the rebase. text data bss dec hex filename 8255291 268856 294072 8818219 868e2b 32-bit i965_dri.so before 8254235 268856 294072 8817163 868a0b 32-bit i965_dri.so after 7815339 345592 420592 8581523 82f193 64-bit i965_dri.so before 7813995 345560 420592 8580147 82ec33 64-bit i965_dri.so after Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_shader.cpp4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 7d62479fc6..ddb941c1cb 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -76,10 +76,6 @@ brw_conditional_for_comparison(unsigned int op)
switch (op) {
case ir_binop_less:
return BRW_CONDITIONAL_L;
- case ir_binop_greater:
- return BRW_CONDITIONAL_G;
- case ir_binop_lequal:
- return BRW_CONDITIONAL_LE;
case ir_binop_gequal:
return BRW_CONDITIONAL_GE;
case ir_binop_equal: