diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2016-05-26 20:39:51 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-05-31 16:41:22 +0200 |
| commit | fc4896e686f79893d6496c7a792a6c72cb3759c1 (patch) | |
| tree | 8519acf62c9cbb293b0e62a8411d0facf1363c17 | |
| parent | 877c00c653ac782f8867a3fee24f16707b1d568c (diff) | |
radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0
It's not needed since it was fixed in the kernel.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index dcf206df21..6221f1cb83 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -116,8 +116,9 @@ void si_context_gfx_flush(void *context, unsigned flags, ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH; - /* The kernel doesn't flush TC for VI correctly (need TC_WB_ACTION_ENA). */ - if (ctx->b.chip_class == VI) + + /* DRM 3.1.0 doesn't flush TC for VI correctly. */ + if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 | SI_CONTEXT_INV_VMEM_L1; |