diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2018-04-16 16:32:41 -0700 |
|---|---|---|
| committer | Dylan Baker <dylan@pnwbakers.com> | 2018-04-26 10:49:38 -0700 |
| commit | 646a26b35c23fb7659b453fb0038e49af04b603e (patch) | |
| tree | 86cb700ab0ff49d0ae14c7d605c39ac8a979aae8 | |
| parent | 66277b0b24680e66d0076bd8a0d8eca738304439 (diff) | |
intel/compiler: Add scheduler deps for instructions that implicitly read g0jenkins_gl
Otherwise the scheduler can move the writes after the reads.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Cc: Clayton A Craft <clayton.a.craft@intel.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 0d5ce25c1ca23abc6d91538f4374a18509091060)
| -rw-r--r-- | src/intel/compiler/brw_ir_vec4.h | 25 | ||||
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 3 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_ir_vec4.h b/src/intel/compiler/brw_ir_vec4.h index 95c5119c6c..e401d8b4d1 100644 --- a/src/intel/compiler/brw_ir_vec4.h +++ b/src/intel/compiler/brw_ir_vec4.h @@ -334,6 +334,31 @@ public: opcode != BRW_OPCODE_IF && opcode != BRW_OPCODE_WHILE)); } + + bool reads_g0_implicitly() const + { + switch (opcode) { + case SHADER_OPCODE_TEX: + case SHADER_OPCODE_TXL: + case SHADER_OPCODE_TXD: + case SHADER_OPCODE_TXF: + case SHADER_OPCODE_TXF_CMS_W: + case SHADER_OPCODE_TXF_CMS: + case SHADER_OPCODE_TXF_MCS: + case SHADER_OPCODE_TXS: + case SHADER_OPCODE_TG4: + case SHADER_OPCODE_TG4_OFFSET: + case SHADER_OPCODE_SAMPLEINFO: + case VS_OPCODE_PULL_CONSTANT_LOAD: + case GS_OPCODE_SET_PRIMITIVE_ID: + case GS_OPCODE_GET_INSTANCE_ID: + case SHADER_OPCODE_GEN4_SCRATCH_READ: + case SHADER_OPCODE_GEN4_SCRATCH_WRITE: + return true; + default: + return false; + } + } }; /** diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 0e793de4dd..f9dd864e11 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -1267,6 +1267,9 @@ vec4_instruction_scheduler::calculate_deps() } } + if (inst->reads_g0_implicitly()) + add_dep(last_fixed_grf_write, n); + if (!inst->is_send_from_grf()) { for (int i = 0; i < inst->mlen; i++) { /* It looks like the MRF regs are released in the send |