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| author | Francisco Jerez <currojerez@riseup.net> | 2016-12-08 18:00:17 -0800 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-12-14 16:50:26 -0800 |
| commit | 591e14ec08b13e8d50636feb1afa578257175b9d (patch) | |
| tree | 7dbb3684b533745867a9a613d868538cdc3c4baf | |
| parent | e0c1ec3b0965d573408536e6e17d41cd39f26616 (diff) | |
i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index dd426bf215..b8f740640f 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -351,6 +351,7 @@ brw_emit_mi_flush(struct brw_context *brw) int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | + PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |