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2013-07-08gr/nvc0: fix gpc firmware regressionMaarten Lankhorst2-20/+23
"drm/nve0-/gr: some new gpc registers can have multiple copies" 5ee86c4190f9e caused a regression for nvc0, because the bit indicating last transfer has occured was no longer set, resulting in random system lockups. Reported-by: Ronald Uitermark <ronald645@gmail.com> Tested-by: Ronald Uitermark <ronald645@gmail.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-08drm: fix minor thinko causing bo moves to not be async on keplerBen Skeggs2-1/+3
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05disp/nva3: Fix HDMI audio regressionIlia Mirkin1-0/+4
This is the nva3 counterpart to commit beba44b17 (drm/nv84/disp: Fix HDMI audio regression). The regression happened as a result of refactoring in commit 8e9e3d2de (drm/nv84/disp: move hdmi control into core). Reported-and-tested-by: Max Baldwin <archerseven@gmail.com> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05nv50-/disp: Use output specific mask in interruptEmil Velikov1-1/+5
The commit commit 476e84e126171d809f9c0b5d97137f5055f95ca8 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon Feb 11 09:24:23 2013 +1000 drm/nv50-/disp: initial supervisor support for off-chip encoders changed the write mask in one of the interrupt functions for on-chip encoders, causing a regression in certain VGA dual-head setups. This commit reintroduces the mask thus resolving the regression Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129 Reported-and-Tested-by: Yves-Alexis <corsac@debian.org> Cc: stable@vger.kernel.org [3.9+] CC: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvc0-: remove some more of the hardcoded register writesBen Skeggs3-28/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvc0-: factor out yet more unknown magic into versioned functionsBen Skeggs9-14/+42
NVC1/NVD9 are the only chipsets that should have anything different happen on them after this. We previously weren't doing these register modifications, and NVIDIA do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05devinit/nvd7: use fermi class, not teslaBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvf0-: ctxsw scratch reg count got bumped to 16Ben Skeggs12-3034/+3303
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvc0-: remove hardcoding of UNK count/mask in GPCCS ucodeBen Skeggs4-95/+129
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvf0: build cs ucode for GK110Ben Skeggs11-1/+1438
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvc0-: extend one of the magic calculations for >4 GPCsBen Skeggs1-6/+11
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvf0: fix ddx shaders locking up on meBen Skeggs3-3/+54
This can be generalised and used on GK104 (probably even GF117), but lets just make it work for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05devinit/nvc0: minor typoBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05nvf0/gr: enable support, if external cs ucode is availableBen Skeggs2-1/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvf0: magic sequence that makes PGRAPH come out of hidingBen Skeggs2-4/+48
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05ce/nvf0: enable supportBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05fifo/nvf0: enable supportBen Skeggs2-2/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05gr/nvd7: initial supportMaarten Lankhorst29-20/+1940
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-04gr/nvc0-: generate cs register lists from grctx dataBen Skeggs11-2073/+1152
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-04gr/nvc0-: tpc regs a subset of gpc, add separate list for gpc/unk regsBen Skeggs8-34/+52
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-04gr/nve0-: some new gpc registers can have multiple copiesBen Skeggs4-180/+227
GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-04gr/nvc0-: pull out a group of separately context-switched gpc regsBen Skeggs6-96/+68
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-04gr/nvc0-: make register lists from initvals functionsBen Skeggs36-8427/+6148
Generated context verified to be the same for all supported chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01disp/nvd0-: handle case where display engine is missing/disabledMaarten Lankhorst6-7/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs18-2609/+1273
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-27bsp/nv84: initial vp2 engine implementationIlia Mirkin3-14/+16
2013-06-27vp/nv84: initial vp2 engine implementationIlia Mirkin4-14/+17
2013-06-27core: xtensa engine base class implementationIlia Mirkin6-1/+214
2013-06-27vdec: fork vp3 implementations from vp2Ilia Mirkin11-14/+209
2013-06-27core: move falcon class to engine/Ben Skeggs17-28/+26
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-25kms: don't fail if there's no dcb table entriesBen Skeggs2-7/+9
Fixes module not loading on Tesla K20. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-18drm: remove limit on gartMaarten Lankhorst1-5/+0
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-18vm: perform a bar flush when flushing vmMaarten Lankhorst2-0/+8
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc0: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs6-600/+344
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc8: update initial register/context valuesBen Skeggs6-10/+74
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc4: update initial register/context valuesBen Skeggs6-9/+62
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc1: update initial register/context valuesBen Skeggs6-35/+80
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc3: update initial register/context valuesBen Skeggs6-12/+112
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc0: update initial register/context valuesBen Skeggs6-544/+1042
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvd9: update initial register/context valuesBen Skeggs6-74/+482
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nve4: update initial register/context valuesBen Skeggs4-157/+31
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvc0-: bump maximum gpc/tpc limitsBen Skeggs1-2/+4
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nvf0: initial register/context setupBen Skeggs6-482/+1057
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nve7: update initial register/context valuesBen Skeggs4-3/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13gr/nve6: update initial register/context valuesBen Skeggs4-113/+383
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13drm: delay busy bo vma removal until fence signalsBen Skeggs4-15/+108
As opposed to an explicit wait. Allows userspace to not stall waiting on buffer deletion. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13vm: make each vma take a reference on its parent vmBen Skeggs1-1/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13core: remove nouveau_mm.mutex, no more usersBen Skeggs3-5/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13vm: take subdev mutex, not the mm, protects against race with vm/nvc0Ben Skeggs1-16/+17
nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-06-13vm/nvc0: handle bar tlb flushes internallyBen Skeggs3-34/+28
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 02:41:11 +0000