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2014-09-30i965: Use BDW_MOCS_PTE for renderbuffers.for-valtteriKenneth Graunke1-1/+1
Write-back caching cannot be used for buffers being scanned out by the display engine; surfaces used for scan-out must be write-through or uncached. I originally chose WT for render targets because it works in all cases. However, we really want to use write-back caching where possible, as it is more efficient. Most renderbuffers are not used for scanout - off-screen FBOs certainly are fine, and non-pageflipped backbuffers should be fine as well. So in most cases WB will work. However, we don't know what will be used for scan-out, so we instead simply use the PTE value specified by the kernel, as it knows these things. This matches our MOCS choice on Haswell. Fixes performance regressions since commit ee4484be3dc827cf15bcf109f5 in a microbenchmark (spotted by Eero Tamminen). Improves performance in GLBenchmark 2.7/EgyptHD by 7.44362% +/- 0.496939% (n=55) on a Broadwell GT2. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reported-by: Eero Tamminen <eero.t.tamminen@intel.com> Cc: mesa-stable@lists.freedesktop.org
2014-09-30i965: Add a BRW_MOCS_PTE #define.Kenneth Graunke1-3/+7
Like BDW_MOCS_WB and BDW_MOCS_WT, this specifies that we want to use all three caches (L3, LLC, and eLLC where available), but leaves the LLC caching mode up to the kernel's page table entry. This allows the kernel to pick WB/WT/UC based on whether it's using a buffer for scanout. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org
2014-09-30radeonsi: Pass the slice size to si_dma_copy_bufferMichel Dänzer1-4/+4
Otherwise some parts of tiled slices can be missed. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-30radeonsi: Catch more cases that can't be handled by si_dma_copy_buffer/tileMichel Dänzer1-3/+11
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-30radeonsi: Fix si_dma_copy(_tile) for compressed formatsMichel Dänzer1-2/+2
Fixes GPUVM faults when running the piglit test "getteximage-formats init-by-rendering" with R600_DEBUG=forcedma on SI. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-30radeonsi: Fix tiling mode index for stencil resourcesMichel Dänzer1-2/+3
We are currently only dealing with depth-only or stencil-only resources here, not with resources having both depth and stencil[0]. In both cases, the tiling mode index is in the tile_mode field, not in the stencil_tile_mode field. [0] Add an assertion for that. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-30ilo: fix format of edge flag pointerChia-I Wu1-3/+5
The VE format of edge flag pointers was changed in 780ce576bb1781f027797039693b98253ee4813e. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-30ilo: add a pass to finalize ilo_ve_stateChia-I Wu8-158/+190
Add finalize_vertex_elements() to finalize ilo_ve_state. This fixes a potential issue with URB entry allocation for VS and move the complexity of gen6_3DSTATE_VERTEX_ELEMENTS() to the new function. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-30ilo: precalculate aligned depth buffer sizeChia-I Wu7-48/+43
To replace the hacky zs_align_surface(). Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-30ilo: use dynamic bo for rectlist verticesChia-I Wu10-73/+92
The size is always 24 bytes. We can upload them to the dynamic buffer. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-30st/xa: Fix regression in xa_yuv_planar_blit()Thomas Hellstrom2-0/+12
Commit "st/xa: scissor to help tilers" broke xa_yuv_planar_blit() and vmwgfx textured video. Fix this by implementing scissors also in the yuv draw path. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Cc: Rob Clark <robclark@freedesktop.org> Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
2014-09-29i965: Delete intel_chipset.h.Kenneth Graunke5-251/+0
Unused; it was replaced by include/pci_ids/i965_pci_ids.h long ago. Acked-by: Matt Turner <mattst88@gmail.com>
2014-09-29driconf: Correct and update Catalan translationAlex Henrie1-8/+8
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-09-29driconf: Update Spanish translationAlex Henrie1-5/+5
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-09-29driconf: Synchronize po filesAlex Henrie6-319/+390
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-09-29vc4: Don't try to do stores to buffers that aren't bound.Eric Anholt1-5/+8
The code was kind of mixed up what buffers were getting stored in the case that a resolve bit was unset (which are set based on the GL state at draw time) and the buffer wasn't actually bound. In particular, depth-only rendering would store the color buffer contents, which happen to be pointing at the depth buffer. Thanks to clearing out the resolve bits for things we really can't resolve, now I can drop the safety checks for buffer presence around the actual stores. Fixes 42 piglit tests.
2014-09-29vc4: Shove some depth comparison bits down to where they're used.Eric Anholt1-5/+5
2014-09-29i965: Use BRW_MATH_DATA_SCALAR when source regioning is scalar.Matt Turner6-11/+9
Notice the mistaken (but harmless) argument swapping in brw_math_invert(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-29i965/compaction: Move variable declarations to their uses.Matt Turner1-5/+4
Tested-by: Mark Janes <mark.a.janes@intel.com>
2014-09-29i965/compaction: Simplify jump target code.Matt Turner1-26/+18
My attempts to clarify the code with _compacted/_uncompacted prefixed variables apparently failed. Hopefully this is clearer. In any case, the previous code wasn't clear enough to gcc to let it optimize division by a power of two into a shift. No problems now. Also, the previous code (in the ADD case) didn't work on 32-bit x86, due to complicated set of interactions best summed up as unsigned division and compiler optimizations. Tested-by: Mark Janes <mark.a.janes@intel.com>
2014-09-29freedreno/a3xx: re-emit shaders on variant changeRob Clark2-1/+50
We need to keep track if a state change other than frag/vert shader state will trigger us to need a different shader variant, and if necessary mark the appropriate shader state as dirty. Otherwise we will forget to re-emit the shader state. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno/ir3: add some cmdline argsRob Clark1-8/+87
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno/a3xx: add support to emulate GL_CLAMPRob Clark8-16/+129
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno: add texcoord clamp support to loweringRob Clark2-5/+173
This is for hw that needs to emulate some texture wrap modes (like CLAMP) with some help from the shader. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno: move bind_sampler_states to per-generationRob Clark4-23/+48
Keep the existing function as a common helper. But this lets us move an a2xx specific hack out of common code. And the PIPE_TEX_WRAP_CLAMP emulation will require an a3xx specific hack. So rather than piling on hacks, split this out. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno/a3xx: fix border color orderRob Clark1-5/+4
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29freedreno/a3xx: add 32bit integer vtx formatsRob Clark2-17/+37
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-29vc4: Add support for GL 1.1's stupid CLAMP mode.Eric Anholt1-4/+19
We just clamp the incoming texture coordinates. This breaks the lambda calculation, but it gets the piglit tests to pass. This is the same behavior as in i965.
2014-09-29vc4: Add support for texture border color.Eric Anholt2-1/+84
One spot in the docs says that it's stored at a miplevel just beyond the last miplevel, which was scary. But really, you just load it as the R coordinate (which conflicts with cubemaps, but you don't do border clamping on cubes).
2014-09-29vc4: Add the necessary stubs for occlusion queries.Eric Anholt4-1/+87
We have to expose them for GL 2.0, but we just always return a value of 0. We should be advertising 0 query bits instead of 64, but gallium doesn't have plumbing for that yet. At least this stops the segfaults.
2014-09-29vc4: Optimize out silly SUBs of 0.Eric Anholt1-0/+11
Drops instructions on vs-temp-array-mat4-index-col-row-wr.shader_test, which I was looking at because it's failing to register allocate.
2014-09-29vc4: Dump constant uniform values in VC4_DEBUG=qir.Eric Anholt6-24/+32
Definitely helps when trying to understand and optimize a program.
2014-09-29vc4: Turn a SEL_X_Y(x, 0) into SEL_X_0(x).Eric Anholt1-14/+61
This may reduce register pressure and uniform counts. Drops a bunch of 0 uniform loads on vs-temp-array-mat4-index-col-row-wr.shader_test, which is failing to register allocate.
2014-09-29vc4: Add support for texture cube maps.Eric Anholt5-22/+84
It's not passing some of the piglit tests, because it looks like at small miplevels some contents from surrounding faces are getting filtered in at the corners. It does get 7 new tests passing.
2014-09-29vc4: Rename the slice's size0.Eric Anholt2-5/+5
In the other related fields, "0" refers to the size of the first miplevel, while this is a field in a slice. The other implicit slices we have (cubemap layers) don't vary in size compared to the first one.
2014-09-29vc4: Stop trying to reuse temporaries that store uniform values.Eric Anholt2-12/+0
Almost always, the MOV will get copy propagated out. Even if it doesn't, it's probably better to just reload the uniform at next use (to reduce register pressure) rather than try to save instruction count. I was looking at this because in the presence of texturing (which calls add_uniform() directly to get the uniform load forced into the instruction) the c->uniform_contents indices don't match 1:1 with the temporary qregs.
2014-09-29egl: setup screen iterator before using itTapani Pälli1-1/+1
commit 4ed23fd broke creation of pbuffer surfaces, patch fixes the failure, noticed when running chrome with '--use-gl=egl'. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-09-29ilo: fix a missing 'else'Chia-I Wu1-1/+1
An 'else' is missing in the disassembler. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-29glsl: Allow texture2DProjLod and textureCubeLod in GL ESKalyan Kondapally1-3/+3
According to GLES (i.e. 1.0 and above) spec textureCubeLod and texture2DProjLod are built in functions. We seem to disable support for these functions with GLES. This patch enables the support. Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84355
2014-09-28configure.ac: bump libdrm_freedreno requirementRob Clark1-1/+1
We need 2.4.57 for fd_bo_dmabuf() / fd_bo_from_dmabuf(). Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27glsl: Recognize open-coded pow(x, y).Matt Turner1-0/+14
pow(x, y) is equivalent to exp(log(x) * y). instructions in affected programs: 578 -> 458 (-20.76%) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-27i965/fs: Don't invalidate live intervals in saturate propagation.Matt Turner1-2/+1
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-27i965/fs: Ignore mov.sat instructions in interference check in sat prop.Matt Turner1-1/+2
When an instruction's result was consumed by multiple mov.sat instructions, we would decide that we couldn't move the saturate modifier because something else was using the result, even though it was just another mov.sat! total instructions in shared programs: 4275598 -> 4274842 (-0.02%) instructions in affected programs: 75634 -> 74878 (-1.00%) Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-27i965/fs: Walk instructions in reverse in saturate propagation.Matt Turner1-3/+3
When we find a mov.sat, we search backwards. We might as well search everything else backwards as well and potentially look at fewer instructions. This change enables the next patch. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-09-27freedreno/a3xx: add flat interpolation modeRob Clark7-19/+60
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27freedreno/a3xx: add LOD_BIASRob Clark1-0/+1
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27freedreno: turn missing caps into compile warningsRob Clark1-10/+10
Get rid of the 'default' case (as suggestied by imirkin) so compiler warns us about missing caps. Also add some caps that were missing until now. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27freedreno: we have more than 0 viewports!Rob Clark1-0/+3
4155d1c7 'st/mesa: drop dependence on API profile in st_init_extensions' broke freedreno because somehow 'PIPE_CAP_MAX_VIEWPORTS' fell through the cracks. Resulting that we reported zero viewports. So the state tracker never bothered to give us any valid viewport! Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27freedreno: update generated headersRob Clark4-17/+133
Among other things, fixes a bug for fixed point registers/bitfields. Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-27freedreno: don't advertise mirror-clamp supportRob Clark1-1/+1
At least on a3xx, we cannot do it without some emulation in shader. Signed-off-by: Rob Clark <robclark@freedesktop.org>
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