i965/miptree: CPU map the aux buffer for initcpu_map_mcs

This patch uses the fast cpu mapping to initialize the MCS buffer on platforms
with LLC.

The MCS buffer needs to be initialized to 0xff in order to indicate that the
data within is invalid. Later, hardware will end up correctly filling out the
MCS buffer. The current code is naively calling the raw miptree map function,
which ends up doing a GTT mapping. This all makes sense because the buffer is
tiled, and so we want the proper tiling to occur. Additionally, on platforms
without LLC, we'd need to make sure that the writes made it out to memory, and
gtt writes is the mechanism employed today in i965.

I realized that for this initialization case, we'd write the whole buffer with
all 1s. As a result of this, it should be safe to not bother tiling the data.
Coherency is handled for us on LLC platforms. As a result, we may as well not
bother with a GTT mapping at all and get the cheaper cached writes.

Tiling is tricky. If you CPU map, you must make sure you align the height in
order to capture the full width of the buffer. It's weird and I need to explain
that better.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>

0 files changed, 0 insertions, 0 deletions