diff options
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_mocs.c | 30 |
2 files changed, 29 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8c4f4d0c5df0..352e7698f457 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4084,7 +4084,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, if (ret) goto err_unpin_display; - i915_gem_object_flush_cpu_write_domain(obj); + if (!HAS_COHERENT_DISPLAY(obj->base.dev)) + i915_gem_object_flush_cpu_write_domain(obj); old_write_domain = obj->base.write_domain; old_read_domains = obj->base.read_domains; diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 46ac00e10a01..b114c407225e 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -96,6 +96,7 @@ struct drm_i915_mocs_table { * end. */ static const struct drm_i915_mocs_entry skylake_mocs_table[] = { + /* MOCS table version #1 */ /* { 0x00000009, 0x0010 } */ [0] = { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), @@ -107,9 +108,32 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = { LE_SCF(0)), (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, /* { 0x0000003b, 0x0030 } */ - [2] = { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) - | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } + [2] = { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | + LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), + (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, + + /* MOCS table version #2 */ + /* 3: ellC only (via PTEs) + WB L3 */ + [3] = { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(TC_PTE) | LE_LRUM(3) | + LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), + (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, + + /* 4: Older buffers (VBOs) */ + [4] = { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(1) | + LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), + (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }, + + /* MOCS table version #3 */ + + /* 60-62 RSVD for Software. 63 reserved */ + [60] = { 0x38, 0x30 }, + [61] = { 0x38, 0x30 }, + + /* 62: LLC only + WB L3 TEST */ + [62] = { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(TC_LLC_ELLC) | LE_LRUM(3) | + LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)), + (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) } + }; /* NOTE: the LE_TGT_CACHE is not used on Broxton */ |