diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-09-09 15:40:22 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-09-10 17:52:59 -0700 |
| commit | 169f9c030c16d1247a3a762972d8687d89a16750 (patch) | |
| tree | de8f71d4571ccefa5b2a18a372c74f83b8b7d1c1 | |
| parent | 4e5eb8ba25054ede4798fa424e6f32b23aba0f98 (diff) | |
i965: Add an assertion that writemask != NULL for non-ARFs.
We've observed GPU hangs on Ivybridge from the following instruction:
mov(8) g115<1>.F 0D { align16 WE_normal NoDDChk 1Q };
There should be no reason to ever set the writemask on a destination
register to zero, except for perhaps the ARF NULL register.
This patch adds an assertion to enforce this for non-ARF registers.
Excluding ARFs is conservative yet should still catch the majority
of mistakes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f26c913565..36c494ee2b 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -126,6 +126,8 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, else { insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask; + assert(dest.dw1.bits.writemask != 0 || + dest.file == BRW_ARCHITECTURE_REGISTER_FILE); /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1: * Although Dst.HorzStride is a don't care for Align16, HW needs * this to be programmed as "01". |