pci id generator

9 files changed, 310 insertions, 205 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index db6466ff1a..fd4a3d0c5b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -179,7 +179,7 @@ GLboolean brwCreateContext( int api,
 
    /* WM maximum threads is number of EUs times number of threads per EU. */
    if (intel->gen >= 6) {
-      if (IS_GT2(intel->intelScreen->deviceID)) {
+      if (IS_GT2(intel->intelScreen)) {
 	 /* This could possibly be 80, but is supposed to require
 	  * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
 	  * GPU reset to change.
diff --git a/src/mesa/drivers/dri/intel/extract.sh b/src/mesa/drivers/dri/intel/extract.sh
new file mode 100755
index 0000000000..7938108d6f
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/extract.sh
@@ -0,0 +1,25 @@
+function print_chipset_map() {
+	echo "static const struct chipset_map chipset_map[] = {"
+
+	while read name id driver info; do
+		case $name in
+		PCI_VENDOR) vendor=$id ;;
+		PCI_*)
+			echo "   { $vendor, $id, &$info }," ;;
+	      esac
+	done
+
+	echo "};"
+}
+
+function print_defines() {
+	while read name id driver info; do
+		case $name in
+		PCI_VENDOR) vendor=$id ;;
+		PCI_*)
+			echo "#define $name $id" ;;
+	      esac
+	done
+}
+
+print_chipset_map
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 377989bcc1..02a621f078 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -109,7 +109,7 @@ do_flush_locked(struct intel_context *intel)
    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
       intel_decode(batch->map, batch->used,
 		   batch->bo->offset,
-		   intel->intelScreen->deviceID, GL_TRUE);
+		   intel->intelScreen->chipset.gen, GL_TRUE);
 
       if (intel->vtbl.debug_batch != NULL)
 	 intel->vtbl.debug_batch(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index a3f40effc3..5bff4d3d11 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -1,146 +1,53 @@
- /*
- * Copyright © 2007 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-#define PCI_CHIP_I810			0x7121
-#define PCI_CHIP_I810_DC100		0x7123
-#define PCI_CHIP_I810_E			0x7125
-#define PCI_CHIP_I815			0x1132
-
-#define PCI_CHIP_I830_M			0x3577
-#define PCI_CHIP_845_G			0x2562
-#define PCI_CHIP_I855_GM		0x3582
-#define PCI_CHIP_I865_G			0x2572
-
-#define PCI_CHIP_I915_G			0x2582
-#define PCI_CHIP_E7221_G		0x258A
-#define PCI_CHIP_I915_GM		0x2592
-#define PCI_CHIP_I945_G			0x2772
-#define PCI_CHIP_I945_GM		0x27A2
-#define PCI_CHIP_I945_GME		0x27AE
-
-#define PCI_CHIP_Q35_G			0x29B2
-#define PCI_CHIP_G33_G			0x29C2
-#define PCI_CHIP_Q33_G			0x29D2
-
-#define PCI_CHIP_IGD_GM			0xA011
-#define PCI_CHIP_IGD_G			0xA001
-
-#define IS_IGDGM(devid)	(devid == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid)	(devid == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
-#define PCI_CHIP_I965_G			0x29A2
-#define PCI_CHIP_I965_Q			0x2992
-#define PCI_CHIP_I965_G_1		0x2982
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I965_GM                0x2A02
-#define PCI_CHIP_I965_GME               0x2A12
-
-#define PCI_CHIP_GM45_GM                0x2A42
-
-#define PCI_CHIP_IGD_E_G                0x2E02
-#define PCI_CHIP_Q45_G                  0x2E12
-#define PCI_CHIP_G45_G                  0x2E22
-#define PCI_CHIP_G41_G                  0x2E32
-#define PCI_CHIP_B43_G                  0x2E42
-#define PCI_CHIP_B43_G1                 0x2E92
-
-#define PCI_CHIP_ILD_G                  0x0042
-#define PCI_CHIP_ILM_G                  0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102	/* Desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106	/* Mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
-#define PCI_CHIP_SANDYBRIDGE_S		0x010A	/* Server */
-
-#define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
-				 devid == PCI_CHIP_I915_GM || \
-				 devid == PCI_CHIP_I945_GM || \
-				 devid == PCI_CHIP_I945_GME || \
-				 devid == PCI_CHIP_I965_GM || \
-				 devid == PCI_CHIP_I965_GME || \
-				 devid == PCI_CHIP_GM45_GM || \
-				 IS_IGD(devid) || \
-				 devid == PCI_CHIP_ILM_G)
-
-#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
-                                 devid == PCI_CHIP_Q45_G || \
-                                 devid == PCI_CHIP_G45_G || \
-                                 devid == PCI_CHIP_G41_G || \
-                                 devid == PCI_CHIP_B43_G || \
-                                 devid == PCI_CHIP_B43_G1)
-#define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
-
-#define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
-#define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
-#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_915(devid)		(devid == PCI_CHIP_I915_G || \
-				 devid == PCI_CHIP_E7221_G || \
-				 devid == PCI_CHIP_I915_GM)
-
-#define IS_945(devid)		(devid == PCI_CHIP_I945_G || \
-				 devid == PCI_CHIP_I945_GM || \
-				 devid == PCI_CHIP_I945_GME || \
-				 devid == PCI_CHIP_G33_G || \
-				 devid == PCI_CHIP_Q33_G || \
-				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
-				 devid == PCI_CHIP_I965_Q || \
-				 devid == PCI_CHIP_I965_G_1 || \
-				 devid == PCI_CHIP_I965_GM || \
-				 devid == PCI_CHIP_I965_GME || \
-				 devid == PCI_CHIP_I946_GZ || \
-				 IS_G4X(devid))
-
-/* Compat macro for intel_decode.c */
-#define IS_IRONLAKE(devid)	IS_GEN5(devid)
-
-#define IS_GT1(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GT2(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS	|| \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
-
-#define IS_GEN6(devid)		(IS_GT1(devid) || IS_GT2(devid))
-
-#define IS_965(devid)		(IS_GEN4(devid) || \
-				 IS_G4X(devid) || \
-				 IS_GEN5(devid) || \
-				 IS_GEN6(devid))
-
-#define IS_9XX(devid)		(IS_915(devid) || \
-				 IS_945(devid) || \
-				 IS_965(devid))
+#define PCI_CHIP_I810 0x7121
+#define PCI_CHIP_I810_DC100 0x7123
+#define PCI_CHIP_I810_E 0x7125
+#define PCI_CHIP_I815 0x1132
+#define PCI_CHIP_I830_M 0x3577
+#define PCI_CHIP_845_G 0x2562
+#define PCI_CHIP_I855_GM 0x3582
+#define PCI_CHIP_I865_G 0x2572
+#define PCI_CHIP_I915_G 0x2582
+#define PCI_CHIP_E7221_G 0x258A
+#define PCI_CHIP_I915_GM 0x2592
+#define PCI_CHIP_I945_G 0x2772
+#define PCI_CHIP_I945_GM 0x27A2
+#define PCI_CHIP_I945_GME 0x27AE
+#define PCI_CHIP_Q35_G 0x29B2
+#define PCI_CHIP_G33_G 0x29C2
+#define PCI_CHIP_Q33_G 0x29D2
+#define PCI_CHIP_IGD_GM 0xA011
+#define PCI_CHIP_IGD_G 0xA001
+#define PCI_CHIP_I965_G 0x29A2
+#define PCI_CHIP_I965_Q 0x2992
+#define PCI_CHIP_I965_G_1 0x2982
+#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_I965_GME 0x2A12
+#define PCI_CHIP_GM45_GM 0x2A42
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G41_G 0x2E32
+#define PCI_CHIP_B43_G 0x2E42
+#define PCI_CHIP_B43_G1 0x2E92
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
+#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102
+#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
+#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106
+#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
+#define PCI_CHIP_SANDYBRIDGE_S 0x010A
+
+
+#define IS_9XX(s) ((s)->chipset.is_i9xx)
+#define IS_965(s) ((s)->chipset.is_i965)
+
+#define IS_GEN4(s) ((s)->gen == 4)
+#define IS_GEN5(s) ((s)->gen == 5)
+#define IS_GEN6(s) ((s)->gen == 6)
+
+#define IS_IRONLAKE(s) ((s)->gen == 5)
+
+#define IS_GT2(s)		((s)->chipset.is_gt2)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index acdf35fc71..29a1c6c02f 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -652,27 +652,14 @@ intelInitContext(struct intel_context *intel,
    intel->driFd = sPriv->fd;
 
    intel->has_xrgb_textures = GL_TRUE;
-   intel->gen = intelScreen->gen;
-   if (IS_GEN6(intel->intelScreen->deviceID)) {
-      intel->needs_ff_sync = GL_TRUE;
-      intel->has_luminance_srgb = GL_TRUE;
-   } else if (IS_GEN5(intel->intelScreen->deviceID)) {
-      intel->needs_ff_sync = GL_TRUE;
-      intel->has_luminance_srgb = GL_TRUE;
-   } else if (IS_965(intel->intelScreen->deviceID)) {
-      if (IS_G4X(intel->intelScreen->deviceID)) {
-	  intel->has_luminance_srgb = GL_TRUE;
-	  intel->is_g4x = GL_TRUE;
-      }
-   } else if (IS_9XX(intel->intelScreen->deviceID)) {
-      if (IS_945(intel->intelScreen->deviceID)) {
-	 intel->is_945 = GL_TRUE;
-      }
-   } else {
-      if (intel->intelScreen->deviceID == PCI_CHIP_I830_M ||
-	  intel->intelScreen->deviceID == PCI_CHIP_845_G) {
-	 intel->has_xrgb_textures = GL_FALSE;
-      }
+   intel->gen = intelScreen->chipset.gen;
+   intel->needs_ff_sync = intelScreen->chipset.needs_ff_sync;
+   intel->has_luminance_srgb = intelScreen->chipset.has_luminance_srgb;
+   intel->is_945 = intelScreen->chipset.is_i945;
+
+   if (intel->intelScreen->deviceID == PCI_CHIP_I830_M ||
+       intel->intelScreen->deviceID == PCI_CHIP_845_G) {
+      intel->has_xrgb_textures = GL_FALSE;
    }
 
    memset(&ctx->TextureFormatSupported, 0,
diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c
index 688b8fee64..9a2505b33a 100644
--- a/src/mesa/drivers/dri/intel/intel_decode.c
+++ b/src/mesa/drivers/dri/intel/intel_decode.c
@@ -1,3 +1,4 @@
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdarg.h>
@@ -789,7 +790,7 @@ i915_decode_instruction(uint32_t *data, uint32_t hw_offset,
 static int
 decode_3d_1d(uint32_t *data, int count,
 	     uint32_t hw_offset,
-	     uint32_t devid,
+	     uint32_t gen,
 	     int *failures)
 {
     unsigned int len, i, c, idx, word, map, sampler, instr;
@@ -889,7 +890,7 @@ decode_3d_1d(uint32_t *data, int count,
 		    BUFFER_FAIL(count, len, "3DSTATE_LOAD_STATE_IMMEDIATE_1");
 
 		/* save vertex state for decode */
-		if (IS_9XX(devid)) {
+		if (gen >= 3) {
 		    if (word == 2) {
 			saved_s2_set = 1;
 			saved_s2 = data[i];
@@ -1021,7 +1022,7 @@ decode_3d_1d(uint32_t *data, int count,
 	}
 	return len;
     case 0x01:
-	if (!IS_9XX(devid))
+	if (gen < 3)
 		break;
 	instr_out(data, hw_offset, 0, "3DSTATE_SAMPLER_STATE\n");
 	instr_out(data, hw_offset, 1, "mask\n");
@@ -1107,7 +1108,7 @@ decode_3d_1d(uint32_t *data, int count,
     for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++)
     {
 	opcode_3d_1d = &opcodes_3d_1d[idx];
-	if (opcode_3d_1d->i830_only && IS_9XX(devid))
+	if (opcode_3d_1d->i830_only && gen >= 3)
 	    continue;
 
 	if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
@@ -1340,7 +1341,7 @@ out:
 }
 
 static int
-decode_3d(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
+decode_3d(uint32_t *data, int count, uint32_t hw_offset, uint32_t gen, int *failures)
 {
     uint32_t opcode;
     unsigned int idx;
@@ -1368,7 +1369,7 @@ decode_3d(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *fa
     case 0x1f:
 	return decode_3d_primitive(data, count, hw_offset, failures);
     case 0x1d:
-	return decode_3d_1d(data, count, hw_offset, devid, failures);
+	return decode_3d_1d(data, count, hw_offset, gen, failures);
     case 0x1c:
 	return decode_3d_1c(data, count, hw_offset, failures);
     }
@@ -1563,7 +1564,7 @@ state_max_out(uint32_t *data, uint32_t hw_offset, unsigned int index,
 }
 
 static int
-decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
+decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t gen, int *failures)
 {
     uint32_t opcode;
     unsigned int idx, len;
@@ -1641,9 +1642,9 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
 			data[1] & ~0x3f, ((data[1] & 0x3f) + 1) * 64);
 	return len;
     case 0x6101:
-	if (IS_GEN6(devid))
+	if (gen == 3)
 	    sba_len = 10;
-	else if (IS_IRONLAKE(devid))
+	else if (gen == 5)
 	    sba_len = 8;
 	else
 	    sba_len = 6;
@@ -1659,17 +1660,17 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
 
 	state_base_out(data, hw_offset, i++, "general");
 	state_base_out(data, hw_offset, i++, "surface");
-	if (IS_GEN6(devid))
+	if (gen == 6)
 	    state_base_out(data, hw_offset, i++, "dynamic");
 	state_base_out(data, hw_offset, i++, "indirect");
-	if (IS_IRONLAKE(devid) || IS_GEN6(devid))
+	if (gen == 5 || gen == 6)
 	    state_base_out(data, hw_offset, i++, "instruction");
 
 	state_max_out(data, hw_offset, i++, "general");
-	if (IS_GEN6(devid))
+	if (gen == 6)
 	    state_max_out(data, hw_offset, i++, "dynamic");
 	state_max_out(data, hw_offset, i++, "indirect");
-	if (IS_IRONLAKE(devid) || IS_GEN6(devid))
+	if (gen = 5 || gen == 6)
 	    state_max_out(data, hw_offset, i++, "instruction");
 
 	return len;
@@ -1909,7 +1910,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
 }
 
 static int
-decode_3d_i830(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int *failures)
+decode_3d_i830(uint32_t *data, int count, uint32_t hw_offset, uint32_t gen, int *failures)
 {
     unsigned int idx;
     uint32_t opcode;
@@ -1944,7 +1945,7 @@ decode_3d_i830(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, in
     case 0x1f:
 	return decode_3d_primitive(data, count, hw_offset, failures);
     case 0x1d:
-	return decode_3d_1d(data, count, hw_offset, devid, failures);
+	return decode_3d_1d(data, count, hw_offset, gen, failures);
     case 0x1c:
 	return decode_3d_1c(data, count, hw_offset, failures);
     }
@@ -1988,7 +1989,7 @@ decode_3d_i830(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, in
 int
 intel_decode(uint32_t *data, int count,
 	     uint32_t hw_offset,
-	     uint32_t devid,
+	     uint32_t gen,
 	     uint32_t ignore_end_of_batchbuffer)
 {
     int ret;
@@ -2023,18 +2024,18 @@ intel_decode(uint32_t *data, int count,
 			       hw_offset + index * 4, &failures);
 	    break;
 	case 0x3:
-	    if (IS_965(devid)) {
+	    if (gen >= 4) {
 		index += decode_3d_965(data + index, count - index,
 				       hw_offset + index * 4,
-				       devid, &failures);
-	    } else if (IS_9XX(devid)) {
+				       gen, &failures);
+	    } else if (gen >= 3) {
 		index += decode_3d(data + index, count - index,
 				   hw_offset + index * 4,
-				   devid, &failures);
+				   gen, &failures);
 	    } else {
 		index += decode_3d_i830(data + index, count - index,
 					hw_offset + index * 4,
-					devid, &failures);
+					gen, &failures);
 	    }
 	    break;
 	default:
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 188daa1904..9d8fc93ea9 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -96,6 +96,49 @@ const GLuint __driNConfigOptions = 11;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE */
 
+static const struct intel_chipset intel_chipset_i8xx = {
+   .gen = 2
+};
+
+static const struct intel_chipset intel_chipset_i915 = {
+   .is_i9xx = 1, .gen = 3, .is_i915 = 1
+};
+
+static const struct intel_chipset intel_chipset_i945 = {
+   .is_i9xx = 1, .gen = 3, .is_i945 = 1
+};
+
+static const struct intel_chipset intel_chipset_i965 = {
+   .is_i9xx = 1, .gen = 4, .is_i965 = 1,
+};
+
+static const struct intel_chipset intel_chipset_g4x = {
+   .is_i9xx = 1, .gen = 4, .is_i965 = 1, .is_g4x = 1,
+   .needs_ff_sync = 1, .has_luminance_srgb = 1
+};
+
+static const struct intel_chipset intel_chipset_ilk = {
+   .is_i9xx = 1, .gen = 5, .is_i965 = 1,
+   .needs_ff_sync = 1, .has_luminance_srgb = 1
+};
+
+static const struct intel_chipset intel_chipset_snb_gt1 = {
+   .is_i9xx = 1, .gen = 6, .is_i965 = 1, .is_gt1 = 1,
+   .needs_ff_sync = 1, .has_luminance_srgb = 1
+};
+
+static const struct intel_chipset intel_chipset_snb_gt2 = {
+   .is_i9xx = 1, .gen = 6, .is_i965 = 1, .is_gt2 = 1,
+   .needs_ff_sync = 1, .has_luminance_srgb = 1
+};
+
+struct chipset_map {
+   int vendor, id;
+   const struct intel_chipset *chipset;
+};
+
+#include "intel_chipset.c"
+
 static const __DRItexBufferExtension intelTexBufferExtension = {
     { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
    intelSetTexBuffer,
@@ -480,7 +523,7 @@ intelCreateContext(gl_api api,
    struct intel_screen *intelScreen = sPriv->private;
 
 #ifdef I915
-   if (IS_9XX(intelScreen->deviceID)) {
+   if (IS_9XX(intelScreen)) {
       if (!IS_965(intelScreen->deviceID)) {
 	 return i915CreateContext(api, mesaVis, driContextPriv,
 				  sharedContextPrivate);
@@ -490,7 +533,7 @@ intelCreateContext(gl_api api,
       return i830CreateContext(mesaVis, driContextPriv, sharedContextPrivate);
    }
 #else
-   if (IS_965(intelScreen->deviceID))
+   if (IS_965(intelScreen))
       return brwCreateContext(api, mesaVis,
 			      driContextPriv, sharedContextPrivate);
 #endif
@@ -545,6 +588,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
    GLenum fb_type[3];
    unsigned int api_mask;
    char *devid_override;
+   int i;
 
    static const GLenum back_buffer_modes[] = {
        GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
@@ -581,18 +625,19 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
       intelScreen->deviceID = strtod(devid_override, NULL);
    }
 
-   if (IS_GEN6(intelScreen->deviceID)) {
-      intelScreen->gen = 6;
-   } else if (IS_GEN5(intelScreen->deviceID)) {
-      intelScreen->gen = 5;
-   } else if (IS_965(intelScreen->deviceID)) {
-      intelScreen->gen = 4;
-   } else if (IS_9XX(intelScreen->deviceID)) {
-      intelScreen->gen = 3;
-   } else {
-      intelScreen->gen = 2;
+   for (i = 0; i < Elements(chipset_map); i++) {
+      if (chipset_map[i].id == intelScreen->deviceID)
+	 break;
+   }
+
+   if (i == Elements(chipset_map)) {
+      fprintf(stderr,
+	      "\nERROR!  Unknown chipset (%04x)\n", intelScreen->deviceID);
+      return GL_FALSE;
    }
 
+   intelScreen->chipset = *chipset_map[i].chipset;
+
    api_mask = (1 << __DRI_API_OPENGL);
 #if FEATURE_ES1
    api_mask |= (1 << __DRI_API_GLES);
@@ -601,7 +646,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
    api_mask |= (1 << __DRI_API_GLES2);
 #endif
 
-   if (IS_9XX(intelScreen->deviceID) || IS_965(intelScreen->deviceID))
+   if (IS_9XX(intelScreen) || IS_965(intelScreen))
       psp->api_mask = api_mask;
 
    if (!intel_init_bufmgr(intelScreen))
@@ -714,7 +759,7 @@ intelAllocateBuffer(__DRIscreen *screen,
    if ((attachment == __DRI_BUFFER_DEPTH ||
 	attachment == __DRI_BUFFER_STENCIL ||
 	attachment == __DRI_BUFFER_DEPTH_STENCIL) &&
-       intelScreen->gen >= 4)
+       intelScreen->chipset.gen >= 4)
       tiling = I915_TILING_Y;
    else
       tiling = I915_TILING_X;
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 4613c9858c..1a32641d20 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -34,10 +34,24 @@
 #include "i915_drm.h"
 #include "xmlconfig.h"
 
+struct intel_chipset {
+   int gen;
+   unsigned int is_i9xx : 1;
+   unsigned int is_i915 : 1;
+   unsigned int is_i945 : 1;
+   unsigned int is_i965 : 1;
+   unsigned int is_g4x : 1;
+   unsigned int is_gt1 : 1;
+   unsigned int is_gt2 : 1;
+
+   unsigned int needs_ff_sync : 1;
+   unsigned int has_luminance_srgb : 1;
+};
+
 struct intel_screen
 {
    int deviceID;
-   int gen;
+   struct intel_chipset chipset;
 
    int logTextureGranularity;
 
@@ -56,6 +70,89 @@ struct intel_screen
    driOptionCache optionCache;
 };
 
+#define IS_9XX(s) ((s)->chipset.is_i9xx)
+#define IS_965(s) ((s)->chipset.is_i965)
+
+#define IS_GEN4(s) ((s)->gen == 4)
+#define IS_GEN5(s) ((s)->gen == 5)
+#define IS_GEN6(s) ((s)->gen == 6)
+
+#define IS_IRONLAKE(s) ((s)->gen == 5)
+
+#define IS_GT2(s)		((s)->chipset.is_gt2)
+
+#if 0
+#define IS_IGDGM(devid)	(devid == PCI_CHIP_IGD_GM)
+#define IS_IGDG(devid)	(devid == PCI_CHIP_IGD_G)
+#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
+
+#define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
+				 devid == PCI_CHIP_I915_GM || \
+				 devid == PCI_CHIP_I945_GM || \
+				 devid == PCI_CHIP_I945_GME || \
+				 devid == PCI_CHIP_I965_GM || \
+				 devid == PCI_CHIP_I965_GME || \
+				 devid == PCI_CHIP_GM45_GM || \
+				 IS_IGD(devid) || \
+				 devid == PCI_CHIP_ILM_G)
+
+#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
+                                 devid == PCI_CHIP_Q45_G || \
+                                 devid == PCI_CHIP_G45_G || \
+                                 devid == PCI_CHIP_G41_G || \
+                                 devid == PCI_CHIP_B43_G || \
+                                 devid == PCI_CHIP_B43_G1)
+#define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
+#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
+
+#define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
+#define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
+#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
+
+#define IS_915(devid)		(devid == PCI_CHIP_I915_G || \
+				 devid == PCI_CHIP_E7221_G || \
+				 devid == PCI_CHIP_I915_GM)
+
+#define IS_945(devid)		(devid == PCI_CHIP_I945_G || \
+				 devid == PCI_CHIP_I945_GM || \
+				 devid == PCI_CHIP_I945_GME || \
+				 devid == PCI_CHIP_G33_G || \
+				 devid == PCI_CHIP_Q33_G || \
+				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
+
+#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
+				 devid == PCI_CHIP_I965_Q || \
+				 devid == PCI_CHIP_I965_G_1 || \
+				 devid == PCI_CHIP_I965_GM || \
+				 devid == PCI_CHIP_I965_GME || \
+				 devid == PCI_CHIP_I946_GZ || \
+				 IS_G4X(devid))
+
+/* Compat macro for intel_decode.c */
+#define IS_IRONLAKE(devid)	IS_GEN5(devid)
+
+#define IS_GT1(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_S)
+
+#define IS_GT2(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS	|| \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
+
+#define IS_GEN6(devid)		(IS_GT1(devid) || IS_GT2(devid))
+
+#define IS_965(devid)		(IS_GEN4(devid) || \
+				 IS_G4X(devid) || \
+				 IS_GEN5(devid) || \
+				 IS_GEN6(devid))
+
+#define IS_9XX(devid)		(IS_915(devid) || \
+				 IS_945(devid) || \
+				 IS_965(devid))
+#endif
+
+
 extern GLboolean intelMapScreenRegions(__DRIscreen * sPriv);
 
 extern void intelDestroyContext(__DRIcontext * driContextPriv);
diff --git a/src/mesa/drivers/dri/intel/pci_ids.txt b/src/mesa/drivers/dri/intel/pci_ids.txt
new file mode 100644
index 0000000000..1e1327a6de
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/pci_ids.txt
@@ -0,0 +1,43 @@
+PCI_VENDOR			0x8086
+
+PCI_CHIP_I810			0x7121	i915	intel_chipset_i8xx
+PCI_CHIP_I810_DC100		0x7123	i915	intel_chipset_i8xx
+PCI_CHIP_I810_E			0x7125	i915	intel_chipset_i8xx
+PCI_CHIP_I815			0x1132	i915	intel_chipset_i8xx
+PCI_CHIP_I830_M			0x3577	i915	intel_chipset_i8xx
+PCI_CHIP_845_G			0x2562	i915	intel_chipset_i8xx
+PCI_CHIP_I855_GM		0x3582	i915	intel_chipset_i8xx
+PCI_CHIP_I865_G			0x2572	i915	intel_chipset_i8xx
+PCI_CHIP_I915_G			0x2582	i915	intel_chipset_i915
+PCI_CHIP_E7221_G		0x258A	i915	intel_chipset_i915
+PCI_CHIP_I915_GM		0x2592	i915	intel_chipset_i915
+PCI_CHIP_I945_G			0x2772	i915	intel_chipset_i945
+PCI_CHIP_I945_GM		0x27A2	i915	intel_chipset_i945
+PCI_CHIP_I945_GME		0x27AE	i915	intel_chipset_i945
+PCI_CHIP_Q35_G			0x29B2	i915	intel_chipset_i945
+PCI_CHIP_G33_G			0x29C2	i915	intel_chipset_i945
+PCI_CHIP_Q33_G			0x29D2	i915	intel_chipset_i945
+PCI_CHIP_IGD_GM			0xA011	i915	intel_chipset_i945
+PCI_CHIP_IGD_G			0xA001	i915	intel_chipset_i945
+PCI_CHIP_I965_G			0x29A2	i965	intel_chipset_i965
+PCI_CHIP_I965_Q			0x2992	i965	intel_chipset_i965
+PCI_CHIP_I965_G_1		0x2982	i965	intel_chipset_i965
+PCI_CHIP_I946_GZ		0x2972	i965	intel_chipset_i965
+PCI_CHIP_I965_GM		0x2A02	i965	intel_chipset_i965
+PCI_CHIP_I965_GME		0x2A12	i965	intel_chipset_i965
+PCI_CHIP_GM45_GM		0x2A42	i965	intel_chipset_g4x
+PCI_CHIP_IGD_E_G		0x2E02	i965	intel_chipset_g4x
+PCI_CHIP_Q45_G			0x2E12	i965	intel_chipset_g4x
+PCI_CHIP_G45_G			0x2E22	i965	intel_chipset_g4x
+PCI_CHIP_G41_G			0x2E32	i965	intel_chipset_g4x
+PCI_CHIP_B43_G			0x2E42	i965	intel_chipset_g4x
+PCI_CHIP_B43_G1			0x2E92	i965	intel_chipset_g4x
+PCI_CHIP_ILD_G			0x0042	i965	intel_chipset_ilk
+PCI_CHIP_ILM_G			0x0046	i965	intel_chipset_ilk
+PCI_CHIP_SANDYBRIDGE_GT1	0x0102	i965	intel_chipset_snb_gt1
+PCI_CHIP_SANDYBRIDGE_GT2	0x0112	i965	intel_chipset_snb_gt2
+PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122	i965	intel_chipset_snb_gt2
+PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106	i965	intel_chipset_snb_gt1
+PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116	i965	intel_chipset_snb_gt2
+PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126	i965	intel_chipset_snb_gt2
+PCI_CHIP_SANDYBRIDGE_S		0x010A	i965	intel_chipset_snb_gt1