Importing vendor version xf86-012804-2330 on Thu Jan 29 00:06:33 PST 2004

1 files changed, 74 insertions, 25 deletions

diff --git a/hw/xfree86/os-support/bus/zx1PCI.c b/hw/xfree86/os-support/bus/zx1PCI.c
index ee92263fa..5d4d6a991 100644
--- a/hw/xfree86/os-support/bus/zx1PCI.c
+++ b/hw/xfree86/os-support/bus/zx1PCI.c
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.6 2003/12/11 17:11:39 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/zx1PCI.c,v 1.8 2004/01/16 15:39:38 tsi Exp $ */
 /*
  * Copyright (C) 2002-2003 The XFree86 Project, Inc.  All Rights Reserved.
  *
@@ -97,9 +97,10 @@
 #define LBA_PORT5_CNTRL		0x1228U
 #define LBA_PORT6_CNTRL		0x1230U
 #define LBA_PORT7_CNTRL		0x1238U
-#define LBA_ROPE_RESET		  0x01UL
-#define LBA_CLEAR_ERROR		  0x10UL
-#define LBA_HARD_FAIL		  0x40UL
+#define LBA_RESET_FUNCTION	  0x0000000001UL
+#define LBA_CLEAR_ERROR		  0x0000000010UL
+#define LBA_HARD_FAIL		  0x0000000040UL
+#define LBA_RESET_COMPLETE	  0x0100000000UL
 
 #define ROPE_PAGE_CONTROL	0x1418U
 
@@ -117,8 +118,11 @@
 #define IOA_SUBORDINATE_BUS	0x0059U
 
 #define IOA_CONTROL		0x0108U
-#define IOA_FORWARD_VGA		  0x08UL
-#define IOA_HARD_FAIL		  0x40UL
+#define IOA_RESET_FUNCTION	  0x0000000001UL
+#define IOA_FORWARD_VGA		  0x0000000008UL
+#define IOA_CLEAR_ERROR		  0x0000000010UL
+#define IOA_HARD_FAIL		  0x0000000040UL
+#define IOA_RESET_COMPLETE	  0x0100000000UL
 
 #define IOA_LMMIO_BASE		0x0200U
 #define IOA_LMMIO_MASK		0x0208U
@@ -134,12 +138,33 @@
 #define IOA_ELMMIO_MASK		0x0258U
 #define IOA_EIOS_BASE		0x0260U
 #define IOA_EIOS_MASK		0x0268U
-
+#define IOA_GLOBAL_MASK		0x0270U
 #define IOA_SLAVE_CONTROL	0x0278U
 #define IOA_VGA_PEER_ENABLE	  0x2000UL
 #define IOA_MSI_BASE		0x0280U
 #define IOA_MSI_MASK		0x0288U
 
+#define IOA_DMA_BASE		0x02B0U
+#define IOA_DMA_MASK		0x02B8U
+
+#define IOA_ERROR_CONFIG	0x0680U
+#define IOA_ERROR_PIOWRITE	  0x0001UL
+#define IOA_ERROR_PIOREAD	  0x0002UL
+#define IOA_ERROR_DMAWRITE	  0x0004UL
+#define IOA_ERROR_DMAREAD	  0x0008UL
+#define IOA_ERROR_CONFIG_MASTER	  0x0010UL
+#define IOA_ERROR_SMART		  0x0020UL
+#define IOA_ERROR_FATAL_SERR	  0x0040UL
+#define IOA_ERROR_ASSERT_SERR	  0x0080UL
+/*	?			  0x0100UL */
+#define IOA_ERROR_LOOPBACK	  0x0200UL
+#define IOA_ERROR_CONFIG_TARGET	  0x0400UL
+#define IOA_ERROR_IO_MASTER	  0x0800UL
+#define IOA_ERROR_IO_TARGET	  0x1000UL
+#define IOA_ERROR_MEM_MASTER	  0x2000UL
+#define IOA_ERROR_MEM_TARGET	  0x4000UL
+#define IOA_ERROR_HF_IO_FATAL	  0x8000UL
+
 #define RANGE_ENABLE		0x01UL		/* In various base registers */
 
 #define IO_MASK			((1UL << 16) - 1UL)
@@ -156,10 +181,15 @@
 static CARD8 *pZX1mio = NULL,
 	     *pZX1ioa = NULL;
 
-static INT8   zx1_ropemap[8];		/* One for each (potential) rope */
-static CARD64 zx1_lbacntl[8];		/*  "   "   "        "       "   */
+/* Per-rope data */
+static INT8   zx1_ropemap[8];
+static CARD32 zx1_pciids[8];
+static CARD64 zx1_lbacntl[8];
 static int    zx1_busno[8], zx1_subno[8];
 
+/* Array of Booleans for non-empty buses */
+static INT8   zx1_busnmpt[MAX_PCI_BUSES];
+
 static pciBusFuncs_t zx1BusFuncs;
 static int           zx1_fakebus = -1;
 static Bool          zx1_hasvga = FALSE;
@@ -292,7 +322,8 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 	 * SLAVE_CONTROL register.
 	 */
 	tmp1 = MIO_QUAD(VGA_ROUTE);
-	tmp2 = IOA_QUAD(ropenum, IOA_CONTROL);
+	tmp2 = IOA_QUAD(ropenum, IOA_CONTROL) &
+	    ~(IOA_RESET_FUNCTION | IOA_CLEAR_ERROR);
 	if ((tmp1 & VGA_ENABLE) && ((tmp1 & 0x07UL) == ropenum)) {
 	    current |= PCI_PCI_BRIDGE_VGA_EN;
 	    if ((mask & PCI_PCI_BRIDGE_VGA_EN) &&
@@ -315,8 +346,9 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 		    MIO_QUAD(VGA_ROUTE) = 0UL;
 		    tmp3 = IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL);
 		    if (tmp3 & IOA_FORWARD_VGA)
-			IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) =
-			    tmp3 & ~IOA_FORWARD_VGA;
+			IOA_QUAD(tmp1 & 0x07UL, IOA_CONTROL) = tmp3 &
+			    ~(IOA_RESET_FUNCTION | IOA_FORWARD_VGA |
+			      IOA_CLEAR_ERROR);
 		}
 		if (!(tmp2 & IOA_FORWARD_VGA)) {
 		    tmp2 |= IOA_FORWARD_VGA;
@@ -329,7 +361,7 @@ ControlZX1Bridge(int bus, CARD16 mask, CARD16 value)
 
 	/* Move on to master abort failure enablement */
 	tmp1 = MIO_QUAD((ropenum << 3) + LBA_PORT0_CNTRL) &
-	       ~(LBA_ROPE_RESET | LBA_CLEAR_ERROR);
+	       ~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR);
 	if ((tmp1 & LBA_HARD_FAIL) || (tmp2 & IOA_HARD_FAIL)) {
 	    current |= PCI_PCI_BRIDGE_MASTER_ABORT_EN;
 	    if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) &&
@@ -520,14 +552,14 @@ xf86PreScanZX1(void)
 
 	    /* Prevent hard-fails */
 	    zx1_lbacntl[i] = MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) &
-		~(LBA_ROPE_RESET | LBA_CLEAR_ERROR);
+		~(LBA_RESET_FUNCTION | LBA_CLEAR_ERROR);
 	    if (zx1_lbacntl[i] & LBA_HARD_FAIL)
 		MIO_QUAD((i << 3) + LBA_PORT0_CNTRL) =
 		    zx1_lbacntl[i] & ~LBA_HARD_FAIL;
 
 	    /* Poke for an ioa */
-	    tmp = IOA_LONG(i, PCI_ID_REG);
-	    switch ((CARD32)tmp) {
+	    zx1_pciids[i] = IOA_LONG(i, PCI_ID_REG);
+	    switch (zx1_pciids[i]) {
 	    case DEVID(VENDOR_HP, CHIP_ELROY):
 	    case DEVID(VENDOR_HP, CHIP_ZX1_LBA):	/* Mercury */
 	    case DEVID(VENDOR_HP, CHIP_ZX1_AGP8):	/* QuickSilver */
@@ -539,10 +571,10 @@ xf86PreScanZX1(void)
 		break;
 
 	    default:
-		if ((CARD16)(tmp + 1U) > (CARD16)1U)
+		if ((CARD16)(zx1_pciids[i] + 1U) > (CARD16)1U)
 		    xf86MsgVerb(X_NOTICE, 0,
 			"HP ZX1:  Unexpected vendor/device id 0x%08X"
-			" on rope %d\n", (CARD32)tmp, i);
+			" on rope %d\n", zx1_pciids[i], i);
 		/* Nobody home, or not the "right" kind of rope guest */
 
 		/*
@@ -906,6 +938,9 @@ xf86PostScanZX1(void)
     if (!pZX1mio)
 	return;
 
+    (void)memset(zx1_busnmpt, FALSE, sizeof(zx1_busnmpt));
+    pBusInfo = pciBusInfo[0];
+
     /*
      * Certain 2.4 & 2.5 Linux kernels add fake PCI devices.  Remove them to
      * prevent any possible interference with our PCI validation.
@@ -929,6 +964,8 @@ xf86PostScanZX1(void)
 	    *ppPCI++ = pPCI;
 	    idx++;
 
+	    zx1_busnmpt[pPCI->busnum] = TRUE;
+
 	    if (zx1_hasvga)
 		continue;
 
@@ -953,8 +990,8 @@ xf86PostScanZX1(void)
     }
 
     /*
-     * Restore hard-fail settings and figure out the actual subordinate bus
-     * numbers.
+     * Restore hard-fail settings and figure out the actual secondary and
+     * subordinate bus numbers.
      */
     for (i = 0;  i < 8;  i++) {
 	if (zx1_ropemap[i] != i)
@@ -968,6 +1005,14 @@ xf86PostScanZX1(void)
 
 	if (zx1_fakebus <= zx1_subno[i])
 	    zx1_fakebus = zx1_subno[i] + 1;
+
+	while (!zx1_busnmpt[zx1_busno[i]]) {
+	    if (zx1_busno[i])	/* Info for bus zero is in static storage */
+		xfree(pciBusInfo[zx1_busno[i]]);
+	    pciBusInfo[zx1_busno[i]++] = NULL;
+	    if (zx1_busno[i] > zx1_subno[i])
+		break;
+	}
     }
 
     if (zx1_fakebus >= pciNumBuses) {
@@ -977,13 +1022,13 @@ xf86PostScanZX1(void)
     }
 
     /* Set up our extra bus functions */
-    zx1BusFuncs = *(pciBusInfo[0]->funcs);
+    zx1BusFuncs = *(pBusInfo->funcs);
     zx1BusFuncs.pciControlBridge = ControlZX1Bridge;
     zx1BusFuncs.pciGetBridgeResources = GetZX1BridgeResources;
 
     /* Set up our own fake bus to act as the root segment */
-    zx1FakeBus.configMech = pciBusInfo[0]->configMech;
-    zx1FakeBus.numDevices = pciBusInfo[0]->numDevices;
+    zx1FakeBus.configMech = pBusInfo->configMech;
+    zx1FakeBus.numDevices = pBusInfo->numDevices;
     zx1FakeBus.primary_bus = zx1_fakebus;
     pciBusInfo[zx1_fakebus] = &zx1FakeBus;
 
@@ -1018,7 +1063,8 @@ xf86PostScanZX1(void)
 
     /* Add a fake PCI-to-PCI bridge to represent each active rope */
     for (i = 0;  i < 8;  i++) {
-	if ((zx1_ropemap[i] != i) || !(pBusInfo = pciBusInfo[zx1_busno[i]]))
+	if ((zx1_ropemap[i] != i) || (zx1_busno[i] > zx1_subno[i]) ||
+	    !(pBusInfo = pciBusInfo[zx1_busno[i]]))
 	    continue;
 
 	if (++idx >= MAX_PCI_DEVICES)
@@ -1028,7 +1074,7 @@ xf86PostScanZX1(void)
 	pPCI->devnum = i | 0x10;
      /* pPCI->funcnum = 0; */
 	pPCI->tag = PCI_MAKE_TAG(zx1_fakebus, pPCI->devnum, 0);
-	pPCI->pci_device_vendor = DEVID(VENDOR_HP, CHIP_ZX1_LBA);
+	pPCI->pci_device_vendor = zx1_pciids[i];
 	pPCI->pci_base_class = PCI_CLASS_BRIDGE;
 	pPCI->pci_sub_class = PCI_SUBCLASS_BRIDGE_PCI;
 	pPCI->pci_header_type = 1;
@@ -1044,6 +1090,9 @@ xf86PostScanZX1(void)
 	/* Plug in chipset routines */
 	pBusInfo->funcs = &zx1BusFuncs;
 
+	/* Set bridge control register for scanpci utility */
+	pPCI->pci_bridge_control = ControlZX1Bridge(zx1_busno[i], 0, 0);
+
 #ifdef OLD_FORMAT
 	xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x "
 		    "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n",