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-rw-r--r--DRIVER_VERSION2
-rw-r--r--Makefile4
-rw-r--r--backup.c37
-rw-r--r--command-list.c7
-rw-r--r--files.c33
-rw-r--r--gen-manpage-opts.c59
-rw-r--r--install-from-cwd.c204
-rw-r--r--kernel.c120
-rw-r--r--kernel.h1
-rwxr-xr-xlibpci.abin0 -> 28108 bytes
-rw-r--r--misc.c133
-rw-r--r--misc.h16
-rw-r--r--ncurses-ui.c5
-rw-r--r--nvidia-installer.c70
-rw-r--r--nvidia-installer.h6
-rw-r--r--option_table.h100
-rwxr-xr-xpci/config.h11
-rwxr-xr-xpci/header.h935
-rw-r--r--pci/pci.h170
-rwxr-xr-xpci/types.h53
-rw-r--r--snarf-ftp.c2
-rw-r--r--snarf-http.c48
-rw-r--r--snarf.c2
-rw-r--r--update.c14
24 files changed, 1718 insertions, 314 deletions
diff --git a/DRIVER_VERSION b/DRIVER_VERSION
index 795d573..bd74b5c 100644
--- a/DRIVER_VERSION
+++ b/DRIVER_VERSION
@@ -1 +1 @@
-1.0-8178
+1.0-8756
diff --git a/Makefile b/Makefile
index 8182d8b..10eff53 100644
--- a/Makefile
+++ b/Makefile
@@ -161,7 +161,7 @@ ALL_SRC = $(SRC) $(NCURSES_UI_C) $(TLS_TEST_C) $(TLS_TEST_DSO_C) \
OBJS = $(ALL_SRC:.c=.o)
ALL_CFLAGS = -I. $(CFLAGS) -imacros $(CONFIG_H)
-ALL_LDFLAGS = -ldl $(LDFLAGS)
+ALL_LDFLAGS = -L. -ldl $(LDFLAGS)
MKPRECOMPILED_SRC = crc.c mkprecompiled.c
MKPRECOMPILED_OBJS = $(MKPRECOMPILED_SRC:.c=.o)
@@ -190,7 +190,7 @@ $(MKPRECOMPILED): $(CONFIG_H) $(MKPRECOMPILED_OBJS)
$(CC) $(ALL_CFLAGS) $(ALL_LDFLAGS) $(MKPRECOMPILED_OBJS) -o $@
$(NVIDIA_INSTALLER): $(CONFIG_H) $(OBJS)
- $(CC) $(ALL_CFLAGS) $(ALL_LDFLAGS) $(OBJS) -o $@
+ $(CC) $(ALL_CFLAGS) $(ALL_LDFLAGS) $(OBJS) -Wl,-Bstatic -lpci -Wl,-Bdynamic -o $@
$(NCURSES_UI_C): $(GEN_UI_ARRAY) $(NCURSES_UI)
$(GEN_UI_ARRAY) $(NCURSES_UI) ncurses_ui_array > $@
diff --git a/backup.c b/backup.c
index 6f0f2d8..b061852 100644
--- a/backup.c
+++ b/backup.c
@@ -659,7 +659,7 @@ static BackupInfo *read_backup_log_file(Options *op)
{
struct stat stat_buf;
char *buf, *c, *line, *filename;
- int fd, num, line_num = 0;
+ int fd, num, length, line_num = 0;
float percent;
BackupLogEntry *e;
@@ -698,7 +698,9 @@ static BackupInfo *read_backup_log_file(Options *op)
/* map the file */
- buf = mmap(0, stat_buf.st_size, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
+ length = stat_buf.st_size;
+
+ buf = mmap(0, length, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
if (!buf) {
ui_error(op, "Unable to mmap file '%s' (%s).", strerror(errno));
return NULL;
@@ -708,13 +710,13 @@ static BackupInfo *read_backup_log_file(Options *op)
b = nvalloc(sizeof(BackupInfo));
- b->version = get_next_line(buf, &c);
+ b->version = get_next_line(buf, &c, buf, length);
if (!b->version || !c) goto parse_error;
percent = (float) (c - buf) / (float) stat_buf.st_size;
ui_status_update(op, percent, NULL);
- b->description = get_next_line(c, &c);
+ b->description = get_next_line(c, &c, buf, length);
if (!b->description || !c) goto parse_error;
b->n = 0;
@@ -728,7 +730,7 @@ static BackupInfo *read_backup_log_file(Options *op)
/* read and parse the next line */
- line = get_next_line(c, &c);
+ line = get_next_line(c, &c, buf, length);
if (!line) break;
if (!parse_first_line(line, &num, &filename)) goto parse_error;
@@ -749,7 +751,8 @@ static BackupInfo *read_backup_log_file(Options *op)
switch(e->num) {
case INSTALLED_FILE:
- if ((line = get_next_line(c, &c)) == NULL) goto parse_error;
+ line = get_next_line(c, &c, buf, length);
+ if (line == NULL) goto parse_error;
line_num++;
if (!parse_crc(line, &e->crc)) goto parse_error;
@@ -758,7 +761,8 @@ static BackupInfo *read_backup_log_file(Options *op)
break;
case INSTALLED_SYMLINK:
- if ((line = get_next_line(c, &c)) == NULL) goto parse_error;
+ line = get_next_line(c, &c, buf, length);
+ if (line == NULL) goto parse_error;
line_num++;
e->target = line;
@@ -766,12 +770,14 @@ static BackupInfo *read_backup_log_file(Options *op)
break;
case BACKED_UP_SYMLINK:
- if ((line = get_next_line(c, &c)) == NULL) goto parse_error;
+ line = get_next_line(c, &c, buf, length);
+ if (line == NULL) goto parse_error;
line_num++;
e->target = line;
- if ((line = get_next_line(c, &c)) == NULL) goto parse_error;
+ line = get_next_line(c, &c, buf, length);
+ if (line == NULL) goto parse_error;
line_num++;
if (!parse_mode_uid_gid(line, &e->mode, &e->uid, &e->gid))
@@ -783,7 +789,8 @@ static BackupInfo *read_backup_log_file(Options *op)
default:
if (num < BACKED_UP_FILE_NUM) goto parse_error;
- if ((line = get_next_line(c, &c)) == NULL) goto parse_error;
+ line = get_next_line(c, &c, buf, length);
+ if (line == NULL) goto parse_error;
line_num++;
if (!parse_crc_mode_uid_gid(line, &e->crc, &e->mode,
@@ -980,23 +987,25 @@ char *get_installed_driver_version_and_descr(Options *op, int *major,
{
struct stat stat_buf;
char *c, *version = NULL, *descr = NULL, *buf = NULL;
- int fd = -1;
+ int length, fd = -1;
if ((fd = open(BACKUP_LOG, O_RDONLY)) == -1) goto done;
if (fstat(fd, &stat_buf) == -1) goto done;
/* map the file */
+
+ length = stat_buf.st_size;
- buf = mmap(0, stat_buf.st_size, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
+ buf = mmap(0, length, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
if (!buf) goto done;
- version = get_next_line(buf, &c);
+ version = get_next_line(buf, &c, buf, length);
if (!version) goto done;
if (!nvid_version(version, major, minor, patch)) goto done;
- descr = get_next_line(c, NULL);
+ descr = get_next_line(c, NULL, buf, length);
done:
if (version) free(version);
diff --git a/command-list.c b/command-list.c
index 6135446..aef045e 100644
--- a/command-list.c
+++ b/command-list.c
@@ -162,7 +162,8 @@ CommandList *build_command_list(Options *op, Package *p)
#endif /* NV_X86_64 */
}
- find_conflicting_kernel_modules(op, p, l);
+ if (!op->no_kernel_module)
+ find_conflicting_kernel_modules(op, p, l);
/*
* find any existing files that clash with what we're going to
@@ -506,6 +507,7 @@ static ConflictingFileInfo __opengl_libs[] = {
{ "libGL.", 6 /* strlen("libGL.") */ },
{ "libnvidia-tls.", 14 /* strlen("libnvidia-tls.") */ },
{ "libGLwrapper.", 13 /* strlen("libGLwrapper.") */ },
+ { "libnvidia-cfg.", 14 /* strlen("libnvidia-cfg.") */ },
{ NULL, 0 }
};
@@ -733,7 +735,8 @@ void condense_file_list(FileList *l)
for (i = 0; i < l->num; i++) {
match = FALSE;
- lstat(l->filename[i], &stat_buf);
+ if (lstat(l->filename[i], &stat_buf) == -1)
+ continue;
for (j = 0; j < n; j++) {
diff --git a/files.c b/files.c
index 35e7fab..7bae8d5 100644
--- a/files.c
+++ b/files.c
@@ -691,7 +691,7 @@ int set_destinations(Options *op, Package *p)
int get_license_acceptance(Options *op)
{
struct stat buf;
- char *text;
+ char *text, *tmp;
int fd;
/* trivial accept if the user accepted on the command line */
@@ -709,8 +709,18 @@ int get_license_acceptance(Options *op)
MAP_FILE|MAP_SHARED,
fd, 0x0)) == (char *) -1) goto failed;
- if (!ui_display_license(op, text)) {
+ /*
+ * the mmap'ed license file may not be NULL terminated, so copy it
+ * into a temporary buffer and explicity NULL terminate the string
+ */
+
+ tmp = nvalloc(buf.st_size + 1);
+ memcpy(tmp, text, buf.st_size);
+ tmp[buf.st_size] = '\0';
+
+ if (!ui_display_license(op, tmp)) {
ui_message(op, "License not accepted. Aborting installation.");
+ nvfree(tmp);
munmap(text, buf.st_size);
close(fd);
return FALSE;
@@ -718,6 +728,7 @@ int get_license_acceptance(Options *op)
ui_log(op, "License accepted.");
+ nvfree(tmp);
munmap(text, buf.st_size);
close(fd);
@@ -1573,19 +1584,27 @@ char *process_template_file(Options *op, PackageEntry *pe,
failed = TRUE; goto done;
}
+ /*
+ * allocate a string to hold the contents of the mmap'ed file,
+ * plus explicit NULL termination
+ */
+
+ tmp = nvalloc(stat_buf.st_size + 1);
+ memcpy(tmp, src, stat_buf.st_size);
+ tmp[stat_buf.st_size] = '\0';
+
+ /* setup to walk the tokens and replacements arrays */
+
token = *tokens;
replacement = *replacements;
- tmp = src;
while (token != NULL && replacement != NULL) {
/*
* Replace any occurances of 'token' with 'replacement' in
- * the source string and free the source unless it points
- * to the source file mapping, in which case the unmap has
- * to be deferred.
+ * the source string and free the source
*/
tmp0 = nv_strreplace(tmp, token, replacement);
- if (tmp != src) nvfree(tmp);
+ nvfree(tmp);
tmp = tmp0;
token = *(++tokens);
replacement = *(++replacements);
diff --git a/gen-manpage-opts.c b/gen-manpage-opts.c
index d49576a..440502e 100644
--- a/gen-manpage-opts.c
+++ b/gen-manpage-opts.c
@@ -3,12 +3,18 @@
*/
#include <stdio.h>
#include <ctype.h>
+#include <string.h>
#include "nvidia-installer.h"
#include "option_table.h"
static void print_option(const NVOption *o)
{
+ char scratch[64], *s;
+ int j, len;
+
+ int omitWhiteSpace;
+
printf(".TP\n.BI ");
/* Print the name of the option */
/* XXX We should backslashify the '-' characters in o->name. */
@@ -24,15 +30,58 @@ static void print_option(const NVOption *o)
}
if (o->flags & NVOPT_HAS_ARGUMENT) {
- printf("=\" \"%s", o->name);
+ len = strlen(o->name);
+ for (j = 0; j < len; j++) scratch[j] = toupper(o->name[j]);
+ scratch[len] = '\0';
+ printf("=\" \"%s", scratch);
}
printf("\"\n");
- /* Print the option description */
- /* XXX Each sentence should be on its own line! */
- /* XXX We need to backslashify the '-' characters here. */
- printf("%s\n", o->description);
+ /*
+ * Print the option description: write each character one at a
+ * time (ugh) so that we can special-case a few characters:
+ *
+ * "[" --> "\n.I "
+ * "]" --> "\n"
+ * "-" --> "\-"
+ *
+ * Brackets are used to mark the text inbetween as italics.
+ * '-' is special cased so that we can backslashify it.
+ *
+ * XXX Each sentence should be on its own line!
+ */
+
+ omitWhiteSpace = 0;
+
+ for (s = o->description; s && *s; s++) {
+
+ switch (*s) {
+ case '[':
+ printf("\n.I ");
+ omitWhiteSpace = 0;
+ break;
+ case ']':
+ printf("\n");
+ omitWhiteSpace = 1;
+ break;
+ case '-':
+ printf("\\-");
+ omitWhiteSpace = 0;
+ break;
+ case ' ':
+ if (!omitWhiteSpace) {
+ printf("%c", *s);
+ }
+ break;
+ default:
+ printf("%c", *s);
+ omitWhiteSpace = 0;
+ break;
+ }
+ }
+
+ printf("\n");
}
int main(int argc, char* argv[])
diff --git a/install-from-cwd.c b/install-from-cwd.c
index 32828b8..995637d 100644
--- a/install-from-cwd.c
+++ b/install-from-cwd.c
@@ -54,8 +54,7 @@
static Package *parse_manifest(Options *op);
-
-
+static int install_kernel_module(Options *op, Package *p);
/*
@@ -100,6 +99,13 @@ int install_from_cwd(Options *op)
ui_set_title(op, "%s (%d.%d-%d)", p->description,
p->major, p->minor, p->patch);
+ /*
+ * warn the user if "legacy" GPUs are installed in this system
+ * and if no supported GPU is found, at all.
+ */
+
+ check_for_nvidia_graphics_devices(op, p);
+
/* make sure the kernel module is unloaded */
if (!check_for_unloaded_kernel_module(op, p)) goto failed;
@@ -117,85 +123,21 @@ int install_from_cwd(Options *op)
* they really want to overwrite the existing installation
*/
- /* print warning message if a legacy gpu is detected in the system */
-
- check_for_legacy_gpu(op, p);
-
if (!check_for_existing_driver(op, p)) return FALSE;
-
- /* determine where to install the kernel module */
-
- if (!determine_kernel_module_installation_path(op)) goto failed;
-
- /* check '/proc/sys/kernel/modprobe' */
-
- if (!check_proc_modprobe_path(op)) return FALSE;
-
- /*
- * do nvchooser-style logic to decide if we have a prebuilt kernel
- * module for their kernel
- *
- * XXX One could make the argument that we should not actually do
- * the building/linking now, but just add this to the list of
- * operations and do it when we execute the operation list. I
- * think it's better to make sure we have a kernel module early on
- * -- a common problem for users will be not having a prebuilt
- * kernel interface for their kernel, and not having the kernel
- * headers installed, so it's better to catch that earlier on.
- */
-
- if (find_precompiled_kernel_interface(op, p)) {
- /*
- * we have a prebuild kernel interface, so now link the kernel
- * interface with the binary portion of the kernel module.
- *
- * XXX if linking fails, maybe we should fall through and
- * attempt to build the kernel module? No, if linking fails,
- * then there is something pretty seriously wrong... better to
- * abort.
- */
-
- if (!link_kernel_module(op, p)) goto failed;
+ /* attempt to build a kernel module for the target kernel */
+ if (!op->no_kernel_module) {
+ if (!install_kernel_module(op, p)) goto failed;
} else {
- /*
- * make sure that the selected or default system compiler
- * is compatible with the target kernel; the user may choose
- * to override the check.
- */
- if (!check_cc_version(op, p)) goto failed;
-
- /*
- * make sure the required development tools are present on
- * this system before attempting to verify the compiler and
- * trying to build a custom kernel interface.
- */
- if (!check_development_tools(op)) goto failed;
-
- /*
- * we do not have a prebuilt kernel interface; thus we'll need
- * to compile the kernel interface, so determine where the
- * kernel source files are.
- */
-
- if (!determine_kernel_source_path(op, p)) goto failed;
-
- /* and now, build the kernel interface */
-
- if (!build_kernel_module(op, p)) goto failed;
+ ui_warn(op, "You specified the '--no-kernel-module' command line "
+ "option, nvidia-installer will not install a kernel "
+ "module as part of this driver installation, and it will "
+ "not remove existing NVIDIA kernel modules not part of "
+ "an earlier NVIDIA driver installation. Please ensure "
+ "that an NVIDIA kernel module matching this driver version "
+ "is installed seperately.");
}
-
- /*
- * if we got this far, we have a complete kernel module; test it
- * to be sure it's OK
- */
-
- if (!test_kernel_module(op, p)) goto failed;
-
- /* add the kernel module to the list of things to install */
-
- if (!add_kernel_module_to_package(op, p)) goto failed;
/*
* if we are only installing the kernel module, then remove
@@ -353,6 +295,97 @@ int install_from_cwd(Options *op)
/*
+ * install_kernel_module() - attempt to build and install a kernel
+ * module for the running kernel; we first check if a prebuilt kernel
+ * interface file exists. If yes, we try to link it into the final
+ * kernel module, else we try to build one from source.
+ *
+ * If we succeed in building a kernel module, we attempt to load it
+ * into the host kernel and add it to the list of files to install if
+ * the load attempt succeeds.
+ */
+
+static int install_kernel_module(Options *op, Package *p)
+{
+ /* determine where to install the kernel module */
+
+ if (!determine_kernel_module_installation_path(op)) return FALSE;
+
+ /* check '/proc/sys/kernel/modprobe' */
+
+ if (!check_proc_modprobe_path(op)) return FALSE;
+
+ /*
+ * do nvchooser-style logic to decide if we have a prebuilt kernel
+ * module for their kernel
+ *
+ * XXX One could make the argument that we should not actually do
+ * the building/linking now, but just add this to the list of
+ * operations and do it when we execute the operation list. I
+ * think it's better to make sure we have a kernel module early on
+ * -- a common problem for users will be not having a prebuilt
+ * kernel interface for their kernel, and not having the kernel
+ * headers installed, so it's better to catch that earlier on.
+ */
+
+ if (find_precompiled_kernel_interface(op, p)) {
+
+ /*
+ * we have a prebuild kernel interface, so now link the kernel
+ * interface with the binary portion of the kernel module.
+ *
+ * XXX if linking fails, maybe we should fall through and
+ * attempt to build the kernel module? No, if linking fails,
+ * then there is something pretty seriously wrong... better to
+ * abort.
+ */
+
+ if (!link_kernel_module(op, p)) return FALSE;
+
+ } else {
+ /*
+ * make sure that the selected or default system compiler
+ * is compatible with the target kernel; the user may choose
+ * to override the check.
+ */
+ if (!check_cc_version(op, p)) return FALSE;
+
+ /*
+ * make sure the required development tools are present on
+ * this system before attempting to verify the compiler and
+ * trying to build a custom kernel interface.
+ */
+ if (!check_development_tools(op)) return FALSE;
+
+ /*
+ * we do not have a prebuilt kernel interface; thus we'll need
+ * to compile the kernel interface, so determine where the
+ * kernel source files are.
+ */
+
+ if (!determine_kernel_source_path(op, p)) return FALSE;
+
+ /* and now, build the kernel interface */
+
+ if (!build_kernel_module(op, p)) return FALSE;
+ }
+
+ /*
+ * if we got this far, we have a complete kernel module; test it
+ * to be sure it's OK
+ */
+
+ if (!test_kernel_module(op, p)) return FALSE;
+
+ /* add the kernel module to the list of things to install */
+
+ if (!add_kernel_module_to_package(op, p)) return FALSE;
+
+ return TRUE;
+}
+
+
+/*
* add_this_kernel() - build a precompiled kernel interface for the
* running kernel, and repackage the .run file to include the new
* precompiled kernel interface.
@@ -451,13 +484,13 @@ static Package *parse_manifest (Options *op)
/* the first line is the description */
line = 1;
- p->description = get_next_line(manifest, &ptr);
+ p->description = get_next_line(manifest, &ptr, manifest, len);
if (!p->description) goto invalid_manifest_file;
/* the second line is the version */
line++;
- p->version_string = get_next_line(ptr, &ptr);
+ p->version_string = get_next_line(ptr, &ptr, manifest, len);
if (!p->version_string) goto invalid_manifest_file;
if (!nvid_version(p->version_string, &p->major, &p->minor, &p->patch))
goto invalid_manifest_file;
@@ -465,13 +498,13 @@ static Package *parse_manifest (Options *op)
/* new third line is the kernel interface filename */
line++;
- p->kernel_interface_filename = get_next_line(ptr, &ptr);
+ p->kernel_interface_filename = get_next_line(ptr, &ptr, manifest, len);
if (!p->kernel_interface_filename) goto invalid_manifest_file;
/* the fourth line is the kernel module name */
line++;
- p->kernel_module_name = get_next_line(ptr, &ptr);
+ p->kernel_module_name = get_next_line(ptr, &ptr, manifest, len);
if (!p->kernel_module_name) goto invalid_manifest_file;
/*
@@ -480,7 +513,7 @@ static Package *parse_manifest (Options *op)
*/
line++;
- tmpstr = get_next_line(ptr, &ptr);
+ tmpstr = get_next_line(ptr, &ptr, manifest, len);
if (!tmpstr) goto invalid_manifest_file;
p->bad_modules = NULL;
@@ -501,7 +534,7 @@ static Package *parse_manifest (Options *op)
*/
line++;
- tmpstr = get_next_line(ptr, &ptr);
+ tmpstr = get_next_line(ptr, &ptr, manifest, len);
if (!tmpstr) goto invalid_manifest_file;
p->bad_module_filenames = NULL;
@@ -518,7 +551,7 @@ static Package *parse_manifest (Options *op)
/* the seventh line is the kernel module build directory */
line++;
- p->kernel_module_build_directory = get_next_line(ptr, &ptr);
+ p->kernel_module_build_directory = get_next_line(ptr, &ptr, manifest, len);
if (!p->kernel_module_build_directory) goto invalid_manifest_file;
remove_trailing_slashes(p->kernel_module_build_directory);
@@ -528,7 +561,8 @@ static Package *parse_manifest (Options *op)
*/
line++;
- p->precompiled_kernel_interface_directory = get_next_line(ptr, &ptr);
+ p->precompiled_kernel_interface_directory =
+ get_next_line(ptr, &ptr, manifest, len);
if (!p->precompiled_kernel_interface_directory)
goto invalid_manifest_file;
remove_trailing_slashes(p->precompiled_kernel_interface_directory);
@@ -539,7 +573,7 @@ static Package *parse_manifest (Options *op)
line++;
do {
- buf = get_next_line(ptr, &ptr);
+ buf = get_next_line(ptr, &ptr, manifest, len);
if ((!buf) || (buf[0] == '\0')) {
done = TRUE;
} else {
diff --git a/kernel.c b/kernel.c
index 453db96..77f7bf1 100644
--- a/kernel.c
+++ b/kernel.c
@@ -46,7 +46,6 @@
#include "precompiled.h"
#include "snarf.h"
#include "crc.h"
-#include "nvLegacy.h"
/* local prototypes */
@@ -703,6 +702,16 @@ int test_kernel_module(Options *op, Package *p)
nvfree(cmd);
}
+ /*
+ * Likewise, we need to preload the i2c-core.ko kernel module to
+ * satisfy another dependency not resolved by `insmod`.
+ */
+ if (strncmp(get_kernel_name(op), "2.4", 3) != 0) {
+ cmd = nvstrcat(op->utils[MODPROBE], " -q i2c-core", NULL);
+ run_command(op, cmd, NULL, FALSE, 0, TRUE);
+ nvfree(cmd);
+ }
+
cmd = nvstrcat(op->utils[INSMOD], " ",
p->kernel_module_build_directory, "/",
p->kernel_module_filename, NULL);
@@ -712,10 +721,18 @@ int test_kernel_module(Options *op, Package *p)
ret = run_command(op, cmd, &data, op->expert, 0, TRUE);
if (ret != 0) {
- ui_error(op, "Unable to load the kernel module '%s'. This is "
- "most likely because the kernel module was built using "
- "the wrong kernel source files. %s",
- p->kernel_module_filename, install_your_kernel_source);
+ ui_error(op, "Unable to load the kernel module '%s'. This "
+ "happens most frequently when this kernel module was "
+ "built against the wrong or improperly configured "
+ "kernel sources, with a version of gcc that differs "
+ "from the one used to build the target kernel, or "
+ "if a driver such as rivafb/nvidiafb is present and "
+ "prevents the NVIDIA kernel module from obtaining "
+ "ownership of the NVIDIA graphics device(s).\n\n"
+ "Please see the log entries 'Kernel module load "
+ "error' and 'Kernel messages' at the end of the file "
+ "'%s' for more information.",
+ p->kernel_module_filename, op->log_file_name);
/*
* if in expert mode, run_command() would have caused this to
@@ -800,8 +817,8 @@ int load_kernel_module(Options *op, Package *p)
ret = TRUE;
}
- if (cmd) free(cmd);
- if (data) free(data);
+ nvfree(cmd);
+ nvfree(data);
return ret;
@@ -1308,6 +1325,7 @@ download_updated_kernel_interface(Options *op, Package *p,
{
int fd = -1;
int dst_fd = -1;
+ int length;
char *url = NULL;
char *tmpfile = NULL;
char *dstfile = NULL;
@@ -1343,10 +1361,12 @@ download_updated_kernel_interface(Options *op, Package *p,
/* get the length of the file */
if (fstat(fd, &stat_buf) == -1) goto done;
+
+ length = stat_buf.st_size;
/* map the file into memory for easier reading */
- str = mmap(0, stat_buf.st_size, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
+ str = mmap(0, length, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
if (str == (void *) -1) goto done;
/*
@@ -1357,7 +1377,7 @@ download_updated_kernel_interface(Options *op, Package *p,
ptr = str;
while (TRUE) {
- buf = get_next_line(ptr, &ptr);
+ buf = get_next_line(ptr, &ptr, str, length);
if ((!buf) || (buf[0] == '\0')) goto done;
s = strstr(buf, ":::");
@@ -1513,88 +1533,6 @@ int check_cc_version(Options *op, Package *p)
} /* check_cc_version() */
-
-/*
- * check_for_legacy_gpu() - run 'lspci -n' and check if any of the returned pci_id
- * corresponds to a legacy gpu. If so, print a warning message for each of them,
- * and returns TRUE.
- * Does not print any warning message and returns FALSE if no legacy GPU has been
- * detected.
- */
-
-int check_for_legacy_gpu(Options *op, Package *p)
-{
- char *cmd = NULL, *data, *tok, *file;
- int ret;
- unsigned int pci_id;
- char hexdigits[] = "0123456789abcdef";
- int hex[UCHAR_MAX];
- int i;
- int found=FALSE;
-
- // lspci not being in the path should not prevent the installation
- file=find_system_util("lspci");
- if (file==NULL)
- return FALSE;
-
- cmd = nvstrcat(file, " -n | ",
- op->utils[CUT], " -d' ' -f4", NULL);
- ret = run_command(op, cmd, &data, FALSE, 0, TRUE);
- free(cmd);
- free(file);
-
- if (ret != 0)
- return FALSE;
-
- /* Convert to lower case then we can do insensitive string comparison */
- nvstrtolower(data);
-
- /* Initialize tables for string->hex conversion */
- for (i = 0; i < UCHAR_MAX; i++)
- hex[i] = 0;
- for (i = 0; hexdigits[i] != '\0'; i++)
- hex[(int)hexdigits[i]] = i;
-
- tok = strtok(data, "\n");
- while(tok) {
- if(strlen(tok)<9)
- break;
-
- /* Check vendor id */
- if(strncmp(tok, "10de", 4)) {
- tok = strtok(NULL, "\n");
- continue;
- }
-
- /* Construct pci_id */
- pci_id = (hex[(int)tok[5]] << 12) +
- (hex[(int)tok[6]] << 8 ) +
- (hex[(int)tok[7]] << 4 ) +
- (hex[(int)tok[8]]);
-
- for(i=0;i< sizeof(LegacyList) / sizeof(LEGACY_INFO); i++)
- {
- if(pci_id==LegacyList[i].uiDevId)
- {
- ui_warn(op, "The NVIDIA %s GPU installed in this system is "
- "supported through the NVIDIA Legacy drivers. Please "
- "visit http://www.nvidia.com/object/unix.html for more "
- "information. The %s NVIDIA driver will ignore "
- "this GPU. ",
- LegacyList[i].AdapterString, p->version_string);
- found = TRUE;
- }
- }
-
- tok = strtok(NULL, "\n");
- }
-
- free(data);
- return found;
-
-} /* check_for_legacy_gpu() */
-
-
/*
* fbdev_check() - run the rivafb_sanity_check and the nvidiafb_sanity_check
* conftests; if either test fails, print the error message from the test
diff --git a/kernel.h b/kernel.h
index 736e3bf..3e9bb27 100644
--- a/kernel.h
+++ b/kernel.h
@@ -40,6 +40,5 @@ int check_kernel_module_version (Options*, Package*);
int check_for_unloaded_kernel_module (Options*, Package*);
int find_precompiled_kernel_interface (Options*, Package*);
char *get_kernel_name (Options*);
-int check_for_legacy_gpu (Options*, Package*);
#endif /* __NVIDIA_INSTALLER_KERNEL_H__ */
diff --git a/libpci.a b/libpci.a
new file mode 100755
index 0000000..0082fd1
--- /dev/null
+++ b/libpci.a
Binary files differ
diff --git a/misc.c b/misc.c
index 1a3658d..ab6061f 100644
--- a/misc.c
+++ b/misc.c
@@ -40,6 +40,7 @@
#include <sys/mman.h>
#include <dirent.h>
#include <libgen.h>
+#include <pci/pci.h>
#include "nvidia-installer.h"
#include "user-interface.h"
@@ -47,6 +48,7 @@
#include "files.h"
#include "misc.h"
#include "crc.h"
+#include "nvLegacy.h"
static int check_symlink(Options*, const char*, const char*, const char*);
static int check_file(Options*, const char*, const mode_t, const uint32);
@@ -415,11 +417,15 @@ char *fget_next_line(FILE *fp, int *eof)
/*
- * get_next_line() - this function scans for the next newline or
- * carriage return in buf. If non-NULL, the passed-by-reference
- * parameter e is set to point to the next printable character in the
- * buffer, or NULL if EOF is encountered.
+ * get_next_line() - this function scans for the next newline,
+ * carriage return, NUL terminator, or EOF in buf. If non-NULL, the
+ * passed-by-reference parameter 'end' is set to point to the next
+ * printable character in the buffer, or NULL if EOF is encountered.
*
+ * If the parameter 'start' is non-NULL, then that is interpretted as
+ * the start of the buffer string, and we check that we never walk
+ * 'length' bytes past 'start'.
+ *
* On success, a newly allocated buffer is allocated containing the
* next line of text (with a NULL terminator in place of the
* newline/carriage return).
@@ -427,27 +433,46 @@ char *fget_next_line(FILE *fp, int *eof)
* On error, NULL is returned.
*/
-char *get_next_line(char *buf, char **e)
+char *get_next_line(char *buf, char **end, char *start, int length)
{
char *c, *retbuf;
int len;
- if (e) *e = NULL;
-
- if ((!buf) || (*buf == '\0') || (*buf == EOF)) return NULL;
+ if (start && (length < 1)) return NULL;
+#define __AT_END(_start, _current, _length) \
+ ((_start) && (((_current) - (_start)) >= (_length)))
+
+ if (end) *end = NULL;
+
+ if ((!buf) ||
+ __AT_END(start, buf, length) ||
+ (*buf == '\0') ||
+ (*buf == EOF)) return NULL;
+
c = buf;
- while ((*c != '\0') && (*c != EOF) && (*c != '\n') && (*c != '\r')) c++;
+
+ while ((!__AT_END(start, c, length)) &&
+ (*c != '\0') &&
+ (*c != EOF) &&
+ (*c != '\n') &&
+ (*c != '\r')) c++;
len = c - buf;
retbuf = nvalloc(len + 1);
strncpy(retbuf, buf, len);
retbuf[len] = '\0';
- if (e) {
- while ((*c != '\0') && (*c != EOF) && (!isprint(*c))) c++;
- if ((*c == '\0') || (*c == EOF)) *e = NULL;
- else *e = c;
+ if (end) {
+ while ((!__AT_END(start, c, length)) &&
+ (*c != '\0') &&
+ (*c != EOF) &&
+ (!isprint(*c))) c++;
+
+ if (__AT_END(start, c, length) ||
+ (*c == '\0') ||
+ (*c == EOF)) *end = NULL;
+ else *end = c;
}
return retbuf;
@@ -703,12 +728,12 @@ int find_system_utils(Options *op)
needed_utils[i].util, op->utils[i]);
}
- for (j=0, i = MAX_SYSTEM_UTILS; i < MAX_SYSTEM_OPTIONAL_UTILS; i++, j++) {
+ for (j = 0, i = MAX_SYSTEM_UTILS; i < MAX_SYSTEM_OPTIONAL_UTILS; i++, j++) {
op->utils[i] = find_system_util(optional_utils[j].util);
if (op->utils[i]) {
ui_expert(op, "found `%s` : `%s`",
- optional_utils[i].util, op->utils[i]);
+ optional_utils[j].util, op->utils[i]);
} else {
op->utils[i] = NULL;
}
@@ -1013,6 +1038,8 @@ int continue_after_error(Options *op, const char *fmt, ...)
"error during installation: '%s'. Continue anyway? "
"(\"no\" will abort)?", msg);
+ nvfree(msg);
+
return ret;
} /* continue_after_error() */
@@ -1884,8 +1911,8 @@ int check_for_running_x(Options *op)
"running", path);
ui_error(op, "You appear to be running an X server; please exit "
"X before installing. For further details, please see "
- "the chapter \"Installing the NVIDIA Driver\" in the "
- "README available on the Linux driver download page at "
+ "the section INSTALLING THE NVIDIA DRIVER in the README "
+ "available on the Linux driver download page at "
"www.nvidia.com.");
return FALSE;
}
@@ -1895,6 +1922,78 @@ int check_for_running_x(Options *op)
} /* check_for_running_x() */
+
+/*
+ * check_for_nvidia_graphics_devices() - check if there are supported
+ * NVIDIA graphics devices installed in this system. If one or more
+ * supported devices are found, the function returns TRUE, else it prints
+ * a warning message and returns FALSE. If legacy devices are detected
+ * in the system, a warning message is printed for each one.
+ */
+
+static void ignore_libpci_output(char *fmt, ...)
+{
+}
+
+int check_for_nvidia_graphics_devices(Options *op, Package *p)
+{
+ struct pci_access *pacc;
+ struct pci_dev *dev;
+ int i, found_supported_device = FALSE;
+ uint16 class;
+
+ pacc = pci_alloc();
+ if (!pacc) return TRUE;
+
+ pacc->error = ignore_libpci_output;
+ pacc->warning = ignore_libpci_output;
+ pci_init(pacc);
+ if (!pacc->methods) return TRUE;
+
+ pci_scan_bus(pacc);
+
+ for (dev = pacc->devices; dev != NULL; dev = dev->next) {
+ if ((pci_fill_info(dev, PCI_FILL_IDENT) & PCI_FILL_IDENT) &&
+ ((class = pci_read_word(dev, PCI_CLASS_DEVICE)) == PCI_CLASS_DISPLAY_VGA) &&
+ (dev->vendor_id == 0x10de) /* NVIDIA */ &&
+ (dev->device_id >= 0x0020) /* TNT or later */) {
+ /*
+ * First check if this GPU is a "legacy" GPU; if it is, print a
+ * warning message and point the user to the NVIDIA Linux
+ * driver download page for.
+ */
+ int found_legacy_device = FALSE;
+ for (i = 0; i < sizeof(LegacyList) / sizeof(LEGACY_INFO); i++) {
+ if (dev->device_id == LegacyList[i].uiDevId) {
+ ui_warn(op, "The NVIDIA %s GPU installed in this system is supported "
+ "through the NVIDIA legacy Linux graphics drivers. Please "
+ "visit http://www.nvidia.com/object/unix.html for more "
+ "information. The %s NVIDIA Linux graphics driver will "
+ "ignore this GPU.", LegacyList[i].AdapterString, p->version_string);
+ found_legacy_device = TRUE;
+ }
+ }
+ if (!found_legacy_device) found_supported_device = TRUE;
+ }
+ }
+
+ pci_cleanup(pacc);
+ if (!pacc->devices) return TRUE;
+
+ if (!found_supported_device) {
+ ui_warn(op, "You do not appear to have an NVIDIA GPU supported by the "
+ "%s NVIDIA Linux graphics driver installed in this system. "
+ "For further details, please see the appendix SUPPORTED "
+ "NVIDIA GRAPHICS CHIPS in the README available on the Linux "
+ "driver download page at www.nvidia.com.", p->version_string);
+ return FALSE;
+ }
+
+ return TRUE;
+
+} /* check_for_nvidia_graphics_devices() */
+
+
/*
* check_selinux() - check if selinux is available.
* Sets the variable op->selinux_enabled.
diff --git a/misc.h b/misc.h
index 596d30b..9dbcea2 100644
--- a/misc.h
+++ b/misc.h
@@ -68,6 +68,18 @@ do { \
} \
} while (0)
+/*
+ * NV_STRCAT() - takes a dynamically allocated string followed by a
+ * NULL-terminated list of arbitrary strings and concatenates the
+ * strings with nvstrcat(); the newly allocated string replaces the
+ * original one, which is freed.
+ */
+#define NV_STRCAT(str, args...) \
+do { \
+ char *__tmp_str = (str); \
+ (str) = nvstrcat(__tmp_str, ##args); \
+ nvfree(__tmp_str); \
+} while (0)
void *nvalloc(size_t size);
void *nvrealloc(void *ptr, size_t size);
@@ -76,13 +88,12 @@ void nvfree(char *s);
char *nvstrtolower(char *s);
char *nvstrcat(const char *str, ...);
char *read_next_word (char *buf, char **e);
-char *assemble_string(const char *fmt, va_list ap);
int check_euid(Options *op);
int check_runlevel(Options *op);
int adjust_cwd(Options *op, const char *program_name);
char *fget_next_line(FILE *fp, int *eof);
-char *get_next_line(char *buf, char **e);
+char *get_next_line(char *buf, char **e, char *start, int length);
int run_command(Options *op, const char *cmd, char **data,
int output, int status, int redirect);
int read_text_file(const char *filename, char **buf);
@@ -105,6 +116,7 @@ void collapse_multiple_slashes(char *s);
int is_symbolic_link_to(const char *path, const char *dest);
Distribution get_distribution(Options *op);
int check_for_running_x(Options *op);
+int check_for_nvidia_graphics_devices(Options *op, Package *p);
int run_nvidia_xconfig(Options *op);
TextRows *nv_format_text_rows(const char *prefix, const char *buf,
diff --git a/ncurses-ui.c b/ncurses-ui.c
index f2cd4a1..847ad8f 100644
--- a/ncurses-ui.c
+++ b/ncurses-ui.c
@@ -1869,9 +1869,10 @@ static void nv_ncurses_pager_update(DataStruct *d, PagerStruct *p)
static void nv_ncurses_pager_handle_events(DataStruct *d,
PagerStruct *p, int ch)
{
- int n = p->t->n - (p->region->h - 1);
-
+ int n;
+
if (!p) return;
+ n = p->t->n - (p->region->h - 1);
switch (ch) {
case KEY_UP:
diff --git a/nvidia-installer.c b/nvidia-installer.c
index 86f322b..236d40c 100644
--- a/nvidia-installer.c
+++ b/nvidia-installer.c
@@ -82,6 +82,34 @@ static void print_version(void)
}
+/*
+ * cook_description() - the description string may contain text within
+ * brackets, which is used by the manpage generator to denote text to
+ * be italicized. We want to omit the bracket characters here.
+ */
+
+static char *cook_description(const char *description)
+{
+ int len;
+ char *s, *dst;
+ const char *src;
+
+ len = strlen(description);
+ s = nvalloc(len + 1);
+
+ for (src = description, dst = s; *src; src++) {
+ if (*src != '[' && (*src != ']')) {
+ *dst = *src;
+ dst++;
+ }
+ }
+
+ *dst = '\0';
+
+ return s;
+
+} /* cook_description() */
+
/*
* print_help() - print usage information
@@ -139,12 +167,16 @@ static void print_help_args_only(int args_only, int advanced)
len = strlen(o->name);
for (j = 0; j < len; j++) scratch[j] = toupper(o->name[j]);
scratch[len] = '\0';
- tmp = nvstrcat(msg, "=[", scratch, "]", NULL);
+ tmp = nvstrcat(msg, "=", scratch, NULL);
nvfree(msg);
msg = tmp;
}
fmtoutp(TAB, msg);
- if (o->description) fmtoutp(BIGTAB, o->description);
+ if (o->description) {
+ tmp = cook_description(o->description);
+ fmtoutp(BIGTAB, tmp);
+ free(tmp);
+ }
fmtout("");
nvfree(msg);
}
@@ -253,7 +285,10 @@ Options *parse_commandline(int argc, char *argv[])
case 'A': print_help(TRUE); exit(0); break;
case 'q': op->no_questions = TRUE; break;
case 'b': op->no_backup = TRUE; break;
- case 'K': op->kernel_module_only = TRUE; break;
+ case 'K':
+ op->kernel_module_only = TRUE;
+ op->no_kernel_module = FALSE; /* conflicts */
+ break;
case 'X': op->run_nvidia_xconfig = TRUE; break;
case 's':
op->silent = op->no_questions = op->accept_license = TRUE;
@@ -345,7 +380,7 @@ Options *parse_commandline(int argc, char *argv[])
case 'N':
op->no_network = TRUE;
break;
- case PRECOMPILED_KERNEL_INTERFACES_PATH:
+ case PRECOMPILED_KERNEL_INTERFACES_PATH_OPTION:
op->precompiled_kernel_interfaces_path = optarg;
break;
case NO_ABI_NOTE_OPTION:
@@ -357,7 +392,7 @@ Options *parse_commandline(int argc, char *argv[])
case NO_RECURSION_OPTION:
op->no_recursion = TRUE;
break;
- case FORCE_SELINUX:
+ case FORCE_SELINUX_OPTION:
if (strcasecmp(optarg, "yes") == 0)
op->selinux_option = SELINUX_FORCE_YES;
else if (strcasecmp(optarg, "no") == 0)
@@ -371,9 +406,14 @@ Options *parse_commandline(int argc, char *argv[])
exit(1);
}
break;
- case NO_SIGWINCH_WORKAROUND:
+ case NO_SIGWINCH_WORKAROUND_OPTION:
op->sigwinch_workaround = FALSE;
break;
+ case NO_KERNEL_MODULE_OPTION:
+ op->no_kernel_module = TRUE;
+ op->kernel_module_only = FALSE; /* conflicts */
+ break;
+
default:
fmterr("");
fmterr("Invalid commandline, please run `%s --help` "
@@ -382,9 +422,21 @@ Options *parse_commandline(int argc, char *argv[])
exit(1);
}
- op->update_arguments = append_update_arguments(op->update_arguments,
- c, optarg,
- long_options);
+ /*
+ * as we go, build a list of options that we would pass on to
+ * a new invocation of the installer if we were to download a
+ * new driver and run its installer (update mode). Be sure
+ * not to place "--update" or "--force-update" in the update
+ * argument list (avoid infinite loop)
+ */
+
+ if ((c != UPDATE_OPTION) && (c != 'f')) {
+
+ op->update_arguments =
+ append_update_arguments(op->update_arguments,
+ c, optarg,
+ long_options);
+ }
}
nvfree((void*)long_options);
diff --git a/nvidia-installer.h b/nvidia-installer.h
index 45d0276..dfa4e91 100644
--- a/nvidia-installer.h
+++ b/nvidia-installer.h
@@ -87,8 +87,9 @@ typedef enum {
} Distribution;
-typedef unsigned int uint32;
-typedef unsigned char uint8;
+typedef unsigned int uint32;
+typedef unsigned short uint16;
+typedef unsigned char uint8;
@@ -123,6 +124,7 @@ typedef struct __options {
int no_backup;
int no_network;
int kernel_module_only;
+ int no_kernel_module;
int no_abi_note;
int no_rpms;
int no_recursion;
diff --git a/option_table.h b/option_table.h
index 97aa83a..d0eec91 100644
--- a/option_table.h
+++ b/option_table.h
@@ -10,38 +10,41 @@ typedef struct {
char *description; /* not used by nvgetopt() */
} NVOption;
-#define XFREE86_PREFIX_OPTION 1
-#define OPENGL_PREFIX_OPTION 2
-#define KERNEL_INCLUDE_PATH_OPTION 3
-#define KERNEL_INSTALL_PATH_OPTION 4
-#define UNINSTALL_OPTION 5
-#define PROC_MOUNT_POINT_OPTION 6
-#define USER_INTERFACE_OPTION 7
-#define LOG_FILE_NAME_OPTION 8
-#define HELP_ARGS_ONLY_OPTION 9
-#define TMPDIR_OPTION 10
-#define NO_OPENGL_HEADERS_OPTION 11
-#define INSTALLER_PREFIX_OPTION 12
-#define FORCE_TLS_OPTION 13
-#define SANITY_OPTION 14
-#define ADVANCED_OPTIONS_ARGS_ONLY_OPTION 15
-#define UTILITY_PREFIX_OPTION 16
-#define ADD_THIS_KERNEL_OPTION 17
-#define RPM_FILE_LIST_OPTION 18
-#define NO_RUNLEVEL_CHECK_OPTION 19
-#define PRECOMPILED_KERNEL_INTERFACES_PATH 20
-#define NO_ABI_NOTE_OPTION 21
-#define KERNEL_SOURCE_PATH_OPTION 22
-#define NO_RPMS_OPTION 23
-#define X_PREFIX_OPTION 24
-#define KERNEL_OUTPUT_PATH_OPTION 25
-#define NO_RECURSION_OPTION 26
-#define FORCE_TLS_COMPAT32_OPTION 27
-#define COMPAT32_PREFIX_OPTION 28
-#define UPDATE_OPTION 29
-#define FORCE_SELINUX 30
-#define NO_SIGWINCH_WORKAROUND 31
-#define X_MODULE_PATH_OPTION 32
+enum {
+ XFREE86_PREFIX_OPTION = 1,
+ OPENGL_PREFIX_OPTION,
+ KERNEL_INCLUDE_PATH_OPTION,
+ KERNEL_INSTALL_PATH_OPTION,
+ UNINSTALL_OPTION,
+ PROC_MOUNT_POINT_OPTION,
+ USER_INTERFACE_OPTION,
+ LOG_FILE_NAME_OPTION,
+ HELP_ARGS_ONLY_OPTION,
+ TMPDIR_OPTION,
+ NO_OPENGL_HEADERS_OPTION,
+ INSTALLER_PREFIX_OPTION,
+ FORCE_TLS_OPTION,
+ SANITY_OPTION,
+ ADVANCED_OPTIONS_ARGS_ONLY_OPTION,
+ UTILITY_PREFIX_OPTION,
+ ADD_THIS_KERNEL_OPTION,
+ RPM_FILE_LIST_OPTION,
+ NO_RUNLEVEL_CHECK_OPTION,
+ PRECOMPILED_KERNEL_INTERFACES_PATH_OPTION,
+ NO_ABI_NOTE_OPTION,
+ KERNEL_SOURCE_PATH_OPTION,
+ NO_RPMS_OPTION,
+ X_PREFIX_OPTION,
+ KERNEL_OUTPUT_PATH_OPTION,
+ NO_RECURSION_OPTION,
+ FORCE_TLS_COMPAT32_OPTION,
+ COMPAT32_PREFIX_OPTION,
+ UPDATE_OPTION,
+ FORCE_SELINUX_OPTION,
+ NO_SIGWINCH_WORKAROUND_OPTION,
+ X_MODULE_PATH_OPTION,
+ NO_KERNEL_MODULE_OPTION
+};
static const NVOption __options[] = {
/* These options are printed by "nvidia-installer --help" */
@@ -215,7 +218,7 @@ static const NVOption __options[] = {
{ "ui", USER_INTERFACE_OPTION, NVOPT_HAS_ARGUMENT,
"Specify what user interface to use, if available. "
- "Valid values are 'ncurses' (the default) or 'none'. "
+ "Valid values for [UI] are 'ncurses' (the default) or 'none'. "
"If the ncurses interface fails to initialize, or 'none' "
"is specified, then a simple printf/scanf interface will "
"be used." },
@@ -236,7 +239,7 @@ static const NVOption __options[] = {
"The nvidia-installer will select the OpenGL "
"libraries appropriate for your system; however, you may use "
"this option to force the installer to install one library "
- "type or another. Valid values for [TLS TYPE] are 'new' and "
+ "type or another. Valid values for [FORCE-TLS] are 'new' and "
"'classic'." },
#if defined(NV_X86_64)
@@ -248,14 +251,14 @@ static const NVOption __options[] = {
{ "kernel-name", 'k', NVOPT_HAS_ARGUMENT,
"Build and install the NVIDIA kernel module for the "
- "non-running kernel specified by [KERNELNAME] ([KERNELNAME] "
+ "non-running kernel specified by [KERNEL-NAME] ([KERNEL-NAME] "
"should be the output of `uname -r` when the target kernel is "
"actually running). This option implies "
"'--no-precompiled-interface'. If the options "
"'--kernel-install-path' and '--kernel-source-path' are not "
- "given, then they will be inferred from [KERNELNAME]; eg: "
- "'/lib/modules/[KERNELNAME]/kernel/drivers/video/' and "
- "'/lib/modules/[KERNELNAME]/build/', respectively." },
+ "given, then they will be inferred from [KERNEL-NAME]; eg: "
+ "'/lib/modules/[KERNEL-NAME]/kernel/drivers/video/' and "
+ "'/lib/modules/[KERNEL-NAME]/build/', respectively." },
{ "no-precompiled-interface", 'n', 0,
"Disable use of precompiled kernel interfaces." },
@@ -298,7 +301,7 @@ static const NVOption __options[] = {
"the installer will only search in the top-level directories." },
{ "kernel-module-only", 'K', 0,
- "Install a kernel module only, and don't uninstall the "
+ "Install a kernel module only, and do not uninstall the "
"existing driver. This is intended to be used to install kernel "
"modules for additional kernels (in cases where you might boot "
"between several different kernels). To use this option, you "
@@ -306,7 +309,15 @@ static const NVOption __options[] = {
"installed driver must match the version of this kernel "
"module." },
- { "precompiled-kernel-interfaces-path", PRECOMPILED_KERNEL_INTERFACES_PATH, NVOPT_HAS_ARGUMENT,
+ { "no-kernel-module", NO_KERNEL_MODULE_OPTION, 0,
+ "Install everything but the kernel module, and do not remove any "
+ "existing, possibly conflicting kernel modules. This can be "
+ "useful in some DEBUG environments. If you use this option, you "
+ "must be careful to ensure that a NVIDIA kernel module matching "
+ "this driver version is installed seperately." },
+
+ { "precompiled-kernel-interfaces-path",
+ PRECOMPILED_KERNEL_INTERFACES_PATH_OPTION, NVOPT_HAS_ARGUMENT,
"Before searching for a precompiled kernel interface in the "
".run file, search in the specified directory." },
@@ -320,18 +331,19 @@ static const NVOption __options[] = {
"'yes'. This is useful with the '--no-questions' or '--silent' "
"options, which assume the default values for all questions." },
- { "force-selinux", FORCE_SELINUX, NVOPT_HAS_ARGUMENT,
+ { "force-selinux", FORCE_SELINUX_OPTION, NVOPT_HAS_ARGUMENT,
"Linux installations using SELinux (Security-Enhanced Linux) "
"require that the security type of all shared libraries be set "
"to 'shlib_t'. nvidia-installer will detect when to set "
"the security type, and set it using chcon(1) on the shared "
"libraries it installs. Use this option to override "
- "nvidia-installer's detection of when to set the security type. "
- "Valid values are 'yes' (force setting of the security type), "
+ "nvidia-installer's detection of when to set the security type. "
+ "Valid values for [FORCE-SELINUX] are 'yes' (force setting of the "
+ "security type), "
"'no' (prevent setting of the security type), and 'default' "
"(let nvidia-installer decide when to set the security type)." },
- { "no-sigwinch-workaround", NO_SIGWINCH_WORKAROUND, 0,
+ { "no-sigwinch-workaround", NO_SIGWINCH_WORKAROUND_OPTION, 0,
"Normally, nvidia-installer ignores the SIGWINCH signal before it "
"forks to execute commands, e.g. to build the kernel module, and "
"restores the SIGWINCH signal handler after the child process "
diff --git a/pci/config.h b/pci/config.h
new file mode 100755
index 0000000..d41f3ae
--- /dev/null
+++ b/pci/config.h
@@ -0,0 +1,11 @@
+#define PCI_ARCH_I386
+#define PCI_OS_LINUX
+#define PCI_HAVE_PM_LINUX_SYSFS
+#define PCI_HAVE_PM_LINUX_PROC
+#define PCI_HAVE_LINUX_BYTEORDER_H
+#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
+#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
+#define PCI_HAVE_PM_INTEL_CONF
+#define PCI_HAVE_64BIT_ADDRESS
+#define PCI_PATH_IDS "/usr/local/pciutils-2.2.1/share/pci.ids"
+#define PCILIB_VERSION "2.2.1"
diff --git a/pci/header.h b/pci/header.h
new file mode 100755
index 0000000..f064ab8
--- /dev/null
+++ b/pci/header.h
@@ -0,0 +1,935 @@
+/*
+ * The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
+ *
+ * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
+ *
+ * Can be freely distributed and used under the terms of the GNU GPL.
+ */
+
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#define PCI_COMMAND 0x04 /* 16 bits */
+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
+#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
+#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
+#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
+#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
+#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
+#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
+#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
+
+#define PCI_STATUS 0x06 /* 16 bits */
+#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
+#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
+#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
+#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
+#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
+#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
+#define PCI_STATUS_DEVSEL_FAST 0x000
+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define PCI_STATUS_DEVSEL_SLOW 0x400
+#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
+ revision */
+#define PCI_REVISION_ID 0x08 /* Revision ID */
+#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE 0x0a /* Device class */
+
+#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
+#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
+#define PCI_HEADER_TYPE 0x0e /* 8 bits */
+#define PCI_HEADER_TYPE_NORMAL 0
+#define PCI_HEADER_TYPE_BRIDGE 1
+#define PCI_HEADER_TYPE_CARDBUS 2
+
+#define PCI_BIST 0x0f /* 8 bits */
+#define PCI_BIST_CODE_MASK 0x0f /* Return result */
+#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
+
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back. Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
+#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
+#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
+#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
+#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
+#define PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
+#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
+#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
+#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
+#define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f)
+#define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03)
+/* bit 1 is reserved if address_space = 1 */
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS 0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID 0x2e
+#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
+#define PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff)
+
+#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
+
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
+#define PCI_MIN_GNT 0x3e /* 8 bits */
+#define PCI_MAX_LAT 0x3f /* 8 bits */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
+#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
+#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
+#define PCI_IO_LIMIT 0x1d
+#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
+#define PCI_IO_RANGE_TYPE_16 0x00
+#define PCI_IO_RANGE_TYPE_32 0x01
+#define PCI_IO_RANGE_MASK ~0x0f
+#define PCI_SEC_STATUS 0x1e /* Secondary status register */
+#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
+#define PCI_MEMORY_LIMIT 0x22
+#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define PCI_MEMORY_RANGE_MASK ~0x0f
+#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT 0x26
+#define PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define PCI_PREF_RANGE_TYPE_32 0x00
+#define PCI_PREF_RANGE_TYPE_64 0x01
+#define PCI_PREF_RANGE_MASK ~0x0f
+#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32 0x2c
+#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16 0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL 0x3e
+#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
+#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
+#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
+#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
+#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
+#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
+#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
+
+/* Header type 2 (CardBus bridges) */
+/* 0x14-0x15 reserved */
+#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
+#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
+#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0 0x1c
+#define PCI_CB_MEMORY_LIMIT_0 0x20
+#define PCI_CB_MEMORY_BASE_1 0x24
+#define PCI_CB_MEMORY_LIMIT_1 0x28
+#define PCI_CB_IO_BASE_0 0x2c
+#define PCI_CB_IO_BASE_0_HI 0x2e
+#define PCI_CB_IO_LIMIT_0 0x30
+#define PCI_CB_IO_LIMIT_0_HI 0x32
+#define PCI_CB_IO_BASE_1 0x34
+#define PCI_CB_IO_BASE_1_HI 0x36
+#define PCI_CB_IO_LIMIT_1 0x38
+#define PCI_CB_IO_LIMIT_1_HI 0x3a
+#define PCI_CB_IO_RANGE_MASK ~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL 0x3e
+#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
+#define PCI_CB_BRIDGE_CTL_SERR 0x02
+#define PCI_CB_BRIDGE_CTL_ISA 0x04
+#define PCI_CB_BRIDGE_CTL_VGA 0x08
+#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
+#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
+#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define PCI_CB_SUBSYSTEM_ID 0x42
+#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID 0 /* Capability ID */
+#define PCI_CAP_ID_PM 0x01 /* Power Management */
+#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
+#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
+#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
+#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
+#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
+#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
+#define PCI_CAP_ID_DBG 0x0A /* Debug port */
+#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
+#define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */
+#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
+#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
+#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
+#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF 4
+
+/* Capabilities residing in the PCI Express extended configuration space */
+
+#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
+#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
+#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
+
+/* Power Management Registers */
+
+#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
+#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
+#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
+#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
+#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
+#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
+#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
+#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
+#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
+#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
+#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
+#define PCI_PM_CTRL 4 /* PM control and status register */
+#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
+#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
+#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
+#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
+#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
+#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
+#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
+#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
+#define PCI_PM_SIZEOF 8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION 2 /* BCD version number */
+#define PCI_AGP_RFU 3 /* Rest of capability flags */
+#define PCI_AGP_STATUS 4 /* Status register */
+#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
+#define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */
+#define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
+#define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */
+#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
+#define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */
+#define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */
+#define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */
+#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */
+#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */
+#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */
+#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */
+#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */
+#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */
+#define PCI_AGP_COMMAND 8 /* Control register */
+#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
+#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
+#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */
+#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
+#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
+#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */
+#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */
+#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
+#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
+#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
+#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
+#define PCI_AGP_SIZEOF 12
+
+/* Slot Identification */
+
+#define PCI_SID_ESR 2 /* Expansion Slot Register */
+#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
+#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS 2 /* Various flags */
+#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
+#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
+#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
+#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
+#define PCI_MSI_RFU 3 /* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
+
+/* PCI-X */
+#define PCI_PCIX_COMMAND 2 /* Command register offset */
+#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
+#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
+#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
+#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
+#define PCI_PCIX_COMMAND_RESERVED 0xf80
+#define PCI_PCIX_STATUS 4 /* Status register offset */
+#define PCI_PCIX_STATUS_FUNCTION 0x00000007
+#define PCI_PCIX_STATUS_DEVICE 0x000000f8
+#define PCI_PCIX_STATUS_BUS 0x0000ff00
+#define PCI_PCIX_STATUS_64BIT 0x00010000
+#define PCI_PCIX_STATUS_133MHZ 0x00020000
+#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
+#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
+#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
+#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
+#define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
+#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
+#define PCI_PCIX_SIZEOF 4
+
+/* PCI-X Bridges */
+#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
+#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
+#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
+#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
+#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
+#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
+#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
+#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
+#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
+#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
+#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
+#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
+#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
+#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
+#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
+#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
+#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
+#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
+#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
+#define PCI_PCIX_BRIDGE_SIZEOF 12
+
+/* HyperTransport (as of spec rev. 2.00) */
+#define PCI_HT_CMD 2 /* Command Register */
+#define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */
+#define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */
+#define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */
+#define PCI_HT_CMD_TYP 0xf800 /* Capability Type */
+#define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */
+#define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */
+#define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */
+#define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */
+#define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */
+#define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */
+#define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */
+#define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */
+#define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */
+#define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */
+#define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */
+
+ /* Link Control Register */
+#define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */
+#define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */
+#define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */
+#define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */
+#define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */
+#define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */
+#define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */
+#define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */
+#define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */
+#define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */
+#define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */
+#define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */
+
+ /* Link Configuration Register */
+#define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */
+#define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */
+#define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */
+#define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */
+#define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */
+#define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */
+#define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */
+#define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */
+#define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */
+#define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */
+#define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */
+#define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */
+#define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */
+#define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */
+
+ /* Revision ID Register */
+#define PCI_HT_RID_MIN 0x1f /* Minor Revision */
+#define PCI_HT_RID_MAJ 0xe0 /* Major Revision */
+
+ /* Link Frequency/Error Register */
+#define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */
+#define PCI_HT_LFRER_200 0x00 /* 200MHz */
+#define PCI_HT_LFRER_300 0x01 /* 300MHz */
+#define PCI_HT_LFRER_400 0x02 /* 400MHz */
+#define PCI_HT_LFRER_500 0x03 /* 500MHz */
+#define PCI_HT_LFRER_600 0x04 /* 600MHz */
+#define PCI_HT_LFRER_800 0x05 /* 800MHz */
+#define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */
+#define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */
+#define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */
+#define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */
+#define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */
+#define PCI_HT_LFRER_ERR 0xf0 /* Link Error */
+#define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */
+#define PCI_HT_LFRER_OV 0x20 /* Overflow Error */
+#define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */
+#define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */
+
+ /* Link Frequency Capability Register */
+#define PCI_HT_LFCAP_200 0x0001 /* 200MHz */
+#define PCI_HT_LFCAP_300 0x0002 /* 300MHz */
+#define PCI_HT_LFCAP_400 0x0004 /* 400MHz */
+#define PCI_HT_LFCAP_500 0x0008 /* 500MHz */
+#define PCI_HT_LFCAP_600 0x0010 /* 600MHz */
+#define PCI_HT_LFCAP_800 0x0020 /* 800MHz */
+#define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */
+#define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */
+#define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */
+#define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */
+#define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */
+
+ /* Feature Register */
+#define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */
+#define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */
+#define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */
+#define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */
+#define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */
+#define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */
+
+ /* Error Handling Register */
+#define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */
+#define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */
+#define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */
+#define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */
+#define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */
+#define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */
+#define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */
+#define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */
+#define PCI_HT_EH_CF 0x0100 /* Chain Fail */
+#define PCI_HT_EH_RE 0x0200 /* Response Error */
+#define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */
+#define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */
+#define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */
+#define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */
+#define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */
+#define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable */
+
+/* HyperTransport: Slave or Primary Interface */
+#define PCI_HT_PRI_CMD 2 /* Command Register */
+#define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */
+#define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */
+#define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */
+#define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */
+#define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
+
+#define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */
+#define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */
+#define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */
+#define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */
+#define PCI_HT_PRI_RID 12 /* Revision ID Register */
+#define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */
+#define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */
+#define PCI_HT_PRI_FTR 16 /* Feature Register */
+#define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */
+#define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */
+#define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */
+#define PCI_HT_PRI_EH 22 /* Error Handling Register */
+#define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */
+#define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */
+#define PCI_HT_PRI_BN 26 /* Bus Number Register */
+#define PCI_HT_PRI_SIZEOF 28
+
+/* HyperTransport: Host or Secondary Interface */
+#define PCI_HT_SEC_CMD 2 /* Command Register */
+#define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */
+#define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */
+#define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */
+#define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */
+#define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */
+#define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */
+#define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */
+#define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
+
+#define PCI_HT_SEC_LCTR 4 /* Link Control Register */
+#define PCI_HT_SEC_LCNF 6 /* Link Config Register */
+#define PCI_HT_SEC_RID 8 /* Revision ID Register */
+#define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */
+#define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */
+#define PCI_HT_SEC_FTR 12 /* Feature Register */
+#define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */
+#define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */
+#define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */
+#define PCI_HT_SEC_EH 18 /* Error Handling Register */
+#define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */
+#define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */
+#define PCI_HT_SEC_SIZEOF 24
+
+/* HyperTransport: Switch */
+#define PCI_HT_SW_CMD 2 /* Switch Command Register */
+#define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */
+#define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */
+#define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */
+#define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */
+#define PCI_HT_SW_PMASK 4 /* Partition Mask Register */
+#define PCI_HT_SW_SWINF 8 /* Switch Info Register */
+#define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */
+#define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */
+#define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */
+#define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */
+#define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */
+#define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */
+#define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */
+#define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */
+#define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */
+#define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */
+#define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */
+#define PCI_HT_SW_SIZEOF 24
+
+ /* Counter indices */
+#define PCI_HT_SW_PC_PCR 0x0 /* Posted Command Receive */
+#define PCI_HT_SW_PC_NPCR 0x1 /* Nonposted Command Receive */
+#define PCI_HT_SW_PC_RCR 0x2 /* Response Command Receive */
+#define PCI_HT_SW_PC_PDWR 0x3 /* Posted DW Receive */
+#define PCI_HT_SW_PC_NPDWR 0x4 /* Nonposted DW Receive */
+#define PCI_HT_SW_PC_RDWR 0x5 /* Response DW Receive */
+#define PCI_HT_SW_PC_PCT 0x6 /* Posted Command Transmit */
+#define PCI_HT_SW_PC_NPCT 0x7 /* Nonposted Command Transmit */
+#define PCI_HT_SW_PC_RCT 0x8 /* Response Command Transmit */
+#define PCI_HT_SW_PC_PDWT 0x9 /* Posted DW Transmit */
+#define PCI_HT_SW_PC_NPDWT 0xa /* Nonposted DW Transmit */
+#define PCI_HT_SW_PC_RDWT 0xb /* Response DW Transmit */
+
+ /* Base/Limit Range indices */
+#define PCI_HT_SW_BLR_BASE0_LO 0x0 /* Base 0[31:1], Enable */
+#define PCI_HT_SW_BLR_BASE0_HI 0x1 /* Base 0 Upper */
+#define PCI_HT_SW_BLR_LIM0_LO 0x2 /* Limit 0 Lower */
+#define PCI_HT_SW_BLR_LIM0_HI 0x3 /* Limit 0 Upper */
+
+ /* Secondary Base indices */
+#define PCI_HT_SW_SB_LO 0x0 /* Secondary Base[31:1], Enable */
+#define PCI_HT_SW_S0_HI 0x1 /* Secondary Base Upper */
+
+/* HyperTransport: Interrupt Discovery and Configuration */
+#define PCI_HT_IDC_IDX 2 /* Index Register */
+#define PCI_HT_IDC_DATA 4 /* Data Register */
+#define PCI_HT_IDC_SIZEOF 8
+
+ /* Register indices */
+#define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */
+#define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */
+#define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */
+ /* Low part (at index) */
+#define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */
+#define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */
+#define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */
+#define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */
+#define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */
+#define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */
+ /* High part (at index + 1) */
+#define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */
+#define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */
+#define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */
+
+/* HyperTransport: Revision ID */
+#define PCI_HT_RID_RID 2 /* Revision Register */
+#define PCI_HT_RID_SIZEOF 4
+
+/* HyperTransport: UnitID Clumping */
+#define PCI_HT_UIDC_CS 4 /* Clumping Support Register */
+#define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */
+#define PCI_HT_UIDC_SIZEOF 12
+
+/* HyperTransport: Extended Configuration Space Access */
+#define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */
+#define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */
+#define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */
+#define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */
+#define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */
+#define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */
+#define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */
+#define PCI_HT_ECSA_SIZEOF 12
+
+/* HyperTransport: Address Mapping */
+#define PCI_HT_AM_CMD 2 /* Command Register */
+#define PCI_HT_AM_CMD_NDMA 0x000f /* Number of DMA Mappings */
+#define PCI_HT_AM_CMD_IOSIZ 0x01f0 /* I/O Size */
+#define PCI_HT_AM_CMD_MT 0x0600 /* Map Type */
+#define PCI_HT_AM_CMD_MT_40B 0x0000 /* 40-bit */
+#define PCI_HT_AM_CMD_MT_64B 0x0200 /* 64-bit */
+
+ /* Window Control Register bits */
+#define PCI_HT_AM_SBW_CTR_COMP 0x1 /* Compat */
+#define PCI_HT_AM_SBW_CTR_NCOH 0x2 /* NonCoherent */
+#define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */
+#define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */
+
+/* HyperTransport: 40-bit Address Mapping */
+#define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */
+#define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */
+#define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */
+#define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */
+#define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */
+#define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */
+#define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */
+#define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */
+#define PCI_HT_AM40_DMA_SBASE0 18 /* DMA Window Secondary Base 0 Register */
+#define PCI_HT_AM40_SIZEOF 12 /* size is variable: 12 + 8 * NDMA */
+
+/* HyperTransport: 64-bit Address Mapping */
+#define PCI_HT_AM64_IDX 4 /* Index Register */
+#define PCI_HT_AM64_DATA_LO 8 /* Data Lower Register */
+#define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */
+#define PCI_HT_AM64_SIZEOF 16
+
+ /* Register indices */
+#define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */
+#define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */
+#define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */
+#define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */
+#define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */
+#define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */
+#define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */
+#define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */
+
+/* HyperTransport: MSI Mapping */
+#define PCI_HT_MSIM_CMD 2 /* Command Register */
+#define PCI_HT_MSIM_CMD_EN 0x0001 /* Mapping Active */
+#define PCI_HT_MSIM_CMD_FIXD 0x0002 /* MSI Mapping Address Fixed */
+#define PCI_HT_MSIM_ADDR_LO 4 /* MSI Mapping Address Lower Register */
+#define PCI_HT_MSIM_ADDR_HI 8 /* MSI Mapping Address Upper Register */
+#define PCI_HT_MSIM_SIZEOF 12
+
+/* HyperTransport: DirectRoute */
+#define PCI_HT_DR_CMD 2 /* Command Register */
+#define PCI_HT_DR_CMD_NDRS 0x000f /* Number of DirectRoute Spaces */
+#define PCI_HT_DR_CMD_IDX 0x01f0 /* Index */
+#define PCI_HT_DR_EN 4 /* Enable Vector Register */
+#define PCI_HT_DR_DATA 8 /* Data Register */
+#define PCI_HT_DR_SIZEOF 12
+
+ /* Register indices */
+#define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */
+#define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */
+#define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */
+#define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */
+#define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */
+#define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */
+
+/* HyperTransport: VCSet */
+#define PCI_HT_VCS_SUP 4 /* VCSets Supported Register */
+#define PCI_HT_VCS_L1EN 5 /* Link 1 VCSets Enabled Register */
+#define PCI_HT_VCS_L0EN 6 /* Link 0 VCSets Enabled Register */
+#define PCI_HT_VCS_SBD 8 /* Stream Bucket Depth Register */
+#define PCI_HT_VCS_SINT 9 /* Stream Interval Register */
+#define PCI_HT_VCS_SSUP 10 /* Number of Streaming VCs Supported Register */
+#define PCI_HT_VCS_SSUP_0 0x00 /* Streaming VC 0 */
+#define PCI_HT_VCS_SSUP_3 0x01 /* Streaming VCs 0-3 */
+#define PCI_HT_VCS_SSUP_15 0x02 /* Streaming VCs 0-15 */
+#define PCI_HT_VCS_NFCBD 12 /* Non-FC Bucket Depth Register */
+#define PCI_HT_VCS_NFCINT 13 /* Non-FC Bucket Interval Register */
+#define PCI_HT_VCS_SIZEOF 16
+
+/* HyperTransport: Retry Mode */
+#define PCI_HT_RM_CTR0 4 /* Control 0 Register */
+#define PCI_HT_RM_CTR_LRETEN 0x01 /* Link Retry Enable */
+#define PCI_HT_RM_CTR_FSER 0x02 /* Force Single Error */
+#define PCI_HT_RM_CTR_ROLNEN 0x04 /* Rollover Nonfatal Enable */
+#define PCI_HT_RM_CTR_FSS 0x08 /* Force Single Stomp */
+#define PCI_HT_RM_CTR_RETNEN 0x10 /* Retry Nonfatal Enable */
+#define PCI_HT_RM_CTR_RETFEN 0x20 /* Retry Fatal Enable */
+#define PCI_HT_RM_CTR_AA 0xc0 /* Allowed Attempts */
+#define PCI_HT_RM_STS0 5 /* Status 0 Register */
+#define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */
+#define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */
+#define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */
+#define PCI_HT_RM_CTR1 6 /* Control 1 Register */
+#define PCI_HT_RM_STS1 7 /* Status 1 Register */
+#define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */
+#define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */
+#define PCI_HT_RM_SIZEOF 12
+
+/* PCI Express */
+#define PCI_EXP_FLAGS 0x2 /* Capabilities register */
+#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
+#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
+#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
+#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
+#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
+#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
+#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
+#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
+#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
+#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
+#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
+#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
+#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
+#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
+#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
+#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
+#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
+#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
+#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define PCI_EXP_DEVCTL 0x8 /* Device Control */
+#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
+#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
+#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
+#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
+#define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
+#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
+#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
+#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
+#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
+#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
+#define PCI_EXP_DEVSTA 0xa /* Device Status */
+#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
+#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
+#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
+#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
+#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
+#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
+#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
+#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
+#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
+#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
+#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
+#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
+#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
+#define PCI_EXP_LNKCTL 0x10 /* Link Control */
+#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
+#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
+#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
+#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
+#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
+#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
+#define PCI_EXP_LNKSTA 0x12 /* Link Status */
+#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
+#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
+#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error */
+#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
+#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
+#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
+#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
+#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
+#define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
+#define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
+#define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
+#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
+#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
+#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
+#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
+#define PCI_EXP_SLTCTL 0x18 /* Slot Control */
+#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
+#define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
+#define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
+#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
+#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
+#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
+#define PCI_EXP_SLTCTL_ATNI 0x00C0 /* Attention Indicator Control */
+#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
+#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
+#define PCI_EXP_SLTSTA 0x1a /* Slot Status */
+#define PCI_EXP_RTCTL 0x1c /* Root Control */
+#define PCI_EXP_RTCTL_SECEE 0x1 /* System Error on Correctable Error */
+#define PCI_EXP_RTCTL_SENFEE 0x1 /* System Error on Non-Fatal Error */
+#define PCI_EXP_RTCTL_SEFEE 0x1 /* System Error on Fatal Error */
+#define PCI_EXP_RTCTL_PMEIE 0x1 /* PME Interrupt Enable */
+#define PCI_EXP_RTSTA 0x20 /* Root Status */
+
+/* MSI-X */
+#define PCI_MSIX_ENABLE 0x8000
+#define PCI_MSIX_MASK 0x4000
+#define PCI_MSIX_TABSIZE 0x03ff
+#define PCI_MSIX_TABLE 4
+#define PCI_MSIX_PBA 8
+#define PCI_MSIX_BIR 0x7
+
+/* Advanced Error Reporting */
+#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
+#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
+#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
+#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
+#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
+#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
+#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
+#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
+#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
+#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
+#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
+#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
+#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
+ /* Same bits as above */
+#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
+ /* Same bits as above */
+#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
+#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
+#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
+#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
+#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
+#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
+#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
+ /* Same bits as above */
+#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
+#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
+#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
+#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
+#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
+#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
+#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
+#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
+#define PCI_ERR_ROOT_STATUS 48
+#define PCI_ERR_ROOT_COR_SRC 52
+#define PCI_ERR_ROOT_SRC 54
+
+/* Virtual Channel */
+#define PCI_VC_PORT_REG1 4
+#define PCI_VC_PORT_REG2 8
+#define PCI_VC_PORT_CTRL 12
+#define PCI_VC_PORT_STATUS 14
+#define PCI_VC_RES_CAP 16
+#define PCI_VC_RES_CTRL 20
+#define PCI_VC_RES_STATUS 26
+
+/* Power Budgeting */
+#define PCI_PWR_DSR 4 /* Data Select Register */
+#define PCI_PWR_DATA 8 /* Data Register */
+#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
+#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
+#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
+#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
+#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
+#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
+#define PCI_PWR_CAP 12 /* Capability */
+#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
+
+/*
+ * The PCI interface treats multi-function devices as independent
+ * devices. The slot/function address of each device is encoded
+ * in a single byte as follows:
+ *
+ * 7:3 = slot
+ * 2:0 = function
+ */
+#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
+#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
+#define PCI_FUNC(devfn) ((devfn) & 0x07)
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED 0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
+
+#define PCI_BASE_CLASS_STORAGE 0x01
+#define PCI_CLASS_STORAGE_SCSI 0x0100
+#define PCI_CLASS_STORAGE_IDE 0x0101
+#define PCI_CLASS_STORAGE_FLOPPY 0x0102
+#define PCI_CLASS_STORAGE_IPI 0x0103
+#define PCI_CLASS_STORAGE_RAID 0x0104
+#define PCI_CLASS_STORAGE_OTHER 0x0180
+
+#define PCI_BASE_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
+#define PCI_CLASS_NETWORK_FDDI 0x0202
+#define PCI_CLASS_NETWORK_ATM 0x0203
+#define PCI_CLASS_NETWORK_OTHER 0x0280
+
+#define PCI_BASE_CLASS_DISPLAY 0x03
+#define PCI_CLASS_DISPLAY_VGA 0x0300
+#define PCI_CLASS_DISPLAY_XGA 0x0301
+#define PCI_CLASS_DISPLAY_OTHER 0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA 0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
+#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
+
+#define PCI_BASE_CLASS_MEMORY 0x05
+#define PCI_CLASS_MEMORY_RAM 0x0500
+#define PCI_CLASS_MEMORY_FLASH 0x0501
+#define PCI_CLASS_MEMORY_OTHER 0x0580
+
+#define PCI_BASE_CLASS_BRIDGE 0x06
+#define PCI_CLASS_BRIDGE_HOST 0x0600
+#define PCI_CLASS_BRIDGE_ISA 0x0601
+#define PCI_CLASS_BRIDGE_EISA 0x0602
+#define PCI_CLASS_BRIDGE_MC 0x0603
+#define PCI_CLASS_BRIDGE_PCI 0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
+#define PCI_CLASS_BRIDGE_NUBUS 0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
+#define PCI_CLASS_BRIDGE_OTHER 0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION 0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
+
+#define PCI_BASE_CLASS_SYSTEM 0x08
+#define PCI_CLASS_SYSTEM_PIC 0x0800
+#define PCI_CLASS_SYSTEM_DMA 0x0801
+#define PCI_CLASS_SYSTEM_TIMER 0x0802
+#define PCI_CLASS_SYSTEM_RTC 0x0803
+#define PCI_CLASS_SYSTEM_OTHER 0x0880
+
+#define PCI_BASE_CLASS_INPUT 0x09
+#define PCI_CLASS_INPUT_KEYBOARD 0x0900
+#define PCI_CLASS_INPUT_PEN 0x0901
+#define PCI_CLASS_INPUT_MOUSE 0x0902
+#define PCI_CLASS_INPUT_OTHER 0x0980
+
+#define PCI_BASE_CLASS_DOCKING 0x0a
+#define PCI_CLASS_DOCKING_GENERIC 0x0a00
+#define PCI_CLASS_DOCKING_OTHER 0x0a01
+
+#define PCI_BASE_CLASS_PROCESSOR 0x0b
+#define PCI_CLASS_PROCESSOR_386 0x0b00
+#define PCI_CLASS_PROCESSOR_486 0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
+#define PCI_CLASS_PROCESSOR_CO 0x0b40
+
+#define PCI_BASE_CLASS_SERIAL 0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
+#define PCI_CLASS_SERIAL_ACCESS 0x0c01
+#define PCI_CLASS_SERIAL_SSA 0x0c02
+#define PCI_CLASS_SERIAL_USB 0x0c03
+#define PCI_CLASS_SERIAL_FIBER 0x0c04
+
+#define PCI_CLASS_OTHERS 0xff
+
+/* Several ID's we need in the library */
+
+#define PCI_VENDOR_ID_INTEL 0x8086
+#define PCI_VENDOR_ID_COMPAQ 0x0e11
diff --git a/pci/pci.h b/pci/pci.h
new file mode 100644
index 0000000..5b551ba
--- /dev/null
+++ b/pci/pci.h
@@ -0,0 +1,170 @@
+/*
+ * The PCI Library
+ *
+ * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
+ *
+ * Can be freely distributed and used under the terms of the GNU GPL.
+ */
+
+#ifndef _PCI_LIB_H
+#define _PCI_LIB_H
+
+#include "config.h"
+#include "header.h"
+#include "types.h"
+
+#define PCI_LIB_VERSION 0x020200
+
+/*
+ * PCI Access Structure
+ */
+
+struct pci_methods;
+
+enum pci_access_type {
+ /* Known access methods, remember to update access.c as well */
+ PCI_ACCESS_AUTO, /* Autodetection (params: none) */
+ PCI_ACCESS_SYS_BUS_PCI, /* Linux /sys/bus/pci (params: path) */
+ PCI_ACCESS_PROC_BUS_PCI, /* Linux /proc/bus/pci (params: path) */
+ PCI_ACCESS_I386_TYPE1, /* i386 ports, type 1 (params: none) */
+ PCI_ACCESS_I386_TYPE2, /* i386 ports, type 2 (params: none) */
+ PCI_ACCESS_FBSD_DEVICE, /* FreeBSD /dev/pci (params: path) */
+ PCI_ACCESS_AIX_DEVICE, /* /dev/pci0, /dev/bus0, etc. */
+ PCI_ACCESS_NBSD_LIBPCI, /* NetBSD libpci */
+ PCI_ACCESS_DUMP, /* Dump file (params: filename) */
+ PCI_ACCESS_MAX
+};
+
+struct pci_access {
+ /* Options you can change: */
+ unsigned int method; /* Access method */
+ char *method_params[PCI_ACCESS_MAX]; /* Parameters for the methods */
+ int writeable; /* Open in read/write mode */
+ int buscentric; /* Bus-centric view of the world */
+ char *id_file_name; /* Name of ID list file */
+ int numeric_ids; /* Don't resolve device IDs to names */
+ int debugging; /* Turn on debugging messages */
+
+ /* Functions you can override: */
+ void (*error)(char *msg, ...); /* Write error message and quit */
+ void (*warning)(char *msg, ...); /* Write a warning message */
+ void (*debug)(char *msg, ...); /* Write a debugging message */
+
+ struct pci_dev *devices; /* Devices found on this bus */
+
+ /* Fields used internally: */
+ struct pci_methods *methods;
+ struct id_entry **id_hash; /* names.c */
+ struct id_bucket *current_id_bucket;
+ int fd; /* proc: fd */
+ int fd_rw; /* proc: fd opened read-write */
+ struct pci_dev *cached_dev; /* proc: device the fd is for */
+ int fd_pos; /* proc: current position */
+};
+
+/* Initialize PCI access */
+struct pci_access *pci_alloc(void);
+void pci_init(struct pci_access *);
+void pci_cleanup(struct pci_access *);
+
+/* Scanning of devices */
+void pci_scan_bus(struct pci_access *acc);
+struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, int dev, int func); /* Raw access to specified device */
+void pci_free_dev(struct pci_dev *);
+
+/*
+ * Devices
+ */
+
+struct pci_dev {
+ struct pci_dev *next; /* Next device in the chain */
+ u16 domain; /* PCI domain (host bridge) */
+ u8 bus, dev, func; /* Bus inside domain, device and function */
+
+ /* These fields are set by pci_fill_info() */
+ int known_fields; /* Set of info fields already known */
+ u16 vendor_id, device_id; /* Identity of the device */
+ int irq; /* IRQ number */
+ pciaddr_t base_addr[6]; /* Base addresses */
+ pciaddr_t size[6]; /* Region sizes */
+ pciaddr_t rom_base_addr; /* Expansion ROM base address */
+ pciaddr_t rom_size; /* Expansion ROM size */
+
+ /* Fields used internally: */
+ struct pci_access *access;
+ struct pci_methods *methods;
+ u8 *cache; /* Cached config registers */
+ int cache_len;
+ int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */
+ void *aux; /* Auxillary data */
+};
+
+#define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3)
+#define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf)
+
+u8 pci_read_byte(struct pci_dev *, int pos); /* Access to configuration space */
+u16 pci_read_word(struct pci_dev *, int pos);
+u32 pci_read_long(struct pci_dev *, int pos);
+int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len);
+int pci_write_byte(struct pci_dev *, int pos, u8 data);
+int pci_write_word(struct pci_dev *, int pos, u16 data);
+int pci_write_long(struct pci_dev *, int pos, u32 data);
+int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len);
+
+int pci_fill_info(struct pci_dev *, int flags); /* Fill in device information */
+
+#define PCI_FILL_IDENT 1
+#define PCI_FILL_IRQ 2
+#define PCI_FILL_BASES 4
+#define PCI_FILL_ROM_BASE 8
+#define PCI_FILL_SIZES 16
+#define PCI_FILL_RESCAN 0x10000
+
+void pci_setup_cache(struct pci_dev *, u8 *cache, int len);
+
+/*
+ * Filters
+ */
+
+struct pci_filter {
+ int domain, bus, slot, func; /* -1 = ANY */
+ int vendor, device;
+};
+
+void pci_filter_init(struct pci_access *, struct pci_filter *);
+char *pci_filter_parse_slot(struct pci_filter *, char *);
+char *pci_filter_parse_id(struct pci_filter *, char *);
+int pci_filter_match(struct pci_filter *, struct pci_dev *);
+
+/*
+ * Conversion of PCI ID's to names (according to the pci.ids file)
+ *
+ * Call pci_lookup_name() to identify different types of ID's:
+ *
+ * VENDOR (vendorID) -> vendor
+ * DEVICE (vendorID, deviceID) -> device
+ * VENDOR | DEVICE (vendorID, deviceID) -> combined vendor and device
+ * SUBSYSTEM | VENDOR (subvendorID) -> subsystem vendor
+ * SUBSYSTEM | DEVICE (vendorID, deviceID, subvendorID, subdevID) -> subsystem device
+ * SUBSYSTEM | VENDOR | DEVICE (vendorID, deviceID, subvendorID, subdevID) -> combined subsystem v+d
+ * SUBSYSTEM | ... (-1, -1, subvendorID, subdevID) -> generic subsystem
+ * CLASS (classID) -> class
+ * PROGIF (classID, progif) -> programming interface
+ */
+
+char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...);
+
+int pci_load_name_list(struct pci_access *a); /* Called automatically by pci_lookup_*() when needed; returns success */
+void pci_free_name_list(struct pci_access *a); /* Called automatically by pci_cleanup() */
+
+enum pci_lookup_mode {
+ PCI_LOOKUP_VENDOR = 1, /* Vendor name (args: vendorID) */
+ PCI_LOOKUP_DEVICE = 2, /* Device name (args: vendorID, deviceID) */
+ PCI_LOOKUP_CLASS = 4, /* Device class (args: classID) */
+ PCI_LOOKUP_SUBSYSTEM = 8,
+ PCI_LOOKUP_PROGIF = 16, /* Programming interface (args: classID, prog_if) */
+ PCI_LOOKUP_NUMERIC = 0x10000, /* Want only formatted numbers; default if access->numeric_ids is set */
+ PCI_LOOKUP_NO_NUMBERS = 0x20000 /* Return NULL if not found in the database; default is to print numerically */
+};
+
+#endif
diff --git a/pci/types.h b/pci/types.h
new file mode 100755
index 0000000..4808f56
--- /dev/null
+++ b/pci/types.h
@@ -0,0 +1,53 @@
+/*
+ * The PCI Library -- Types and Format Strings
+ *
+ * Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
+ *
+ * Can be freely distributed and used under the terms of the GNU GPL.
+ */
+
+#include <sys/types.h>
+
+#ifndef PCI_HAVE_Uxx_TYPES
+
+#ifdef PCI_OS_WINDOWS
+typedef unsigned __int8 u8;
+typedef unsigned __int16 u16;
+typedef unsigned __int32 u32;
+#else
+typedef u_int8_t u8;
+typedef u_int16_t u16;
+typedef u_int32_t u32;
+#endif
+
+#ifdef PCI_HAVE_64BIT_ADDRESS
+#include <limits.h>
+#if ULONG_MAX > 0xffffffff
+typedef unsigned long u64;
+#define PCI_U64_FMT "l"
+#else
+typedef unsigned long long u64;
+#define PCI_U64_FMT "ll"
+#endif
+#endif
+
+#endif /* PCI_HAVE_Uxx_TYPES */
+
+#ifdef PCI_HAVE_64BIT_ADDRESS
+typedef u64 pciaddr_t;
+#define PCIADDR_T_FMT "%08" PCI_U64_FMT "x"
+#define PCIADDR_PORT_FMT "%04" PCI_U64_FMT "x"
+#else
+typedef u32 pciaddr_t;
+#define PCIADDR_T_FMT "%08x"
+#define PCIADDR_PORT_FMT "%04x"
+#endif
+
+#ifdef PCI_ARCH_SPARC64
+/* On sparc64 Linux the kernel reports remapped port addresses and IRQ numbers */
+#undef PCIADDR_PORT_FMT
+#define PCIADDR_PORT_FMT PCIADDR_T_FMT
+#define PCIIRQ_FMT "%08x"
+#else
+#define PCIIRQ_FMT "%d"
+#endif
diff --git a/snarf-ftp.c b/snarf-ftp.c
index 0f282df..1a26aa1 100644
--- a/snarf-ftp.c
+++ b/snarf-ftp.c
@@ -107,7 +107,7 @@ static char *get_line(UrlResource *rsrc, int control)
char *end;
char buf[SNARF_BUFSIZE+1];
- while ((bytes_read = read(control, buf, SNARF_BUFSIZE))) {
+ while ((bytes_read = read(control, buf, SNARF_BUFSIZE)) > 0) {
if (buf[0] == '4' || buf[0] == '5') return NULL;
diff --git a/snarf-http.c b/snarf-http.c
index 002ae33..7a089f0 100644
--- a/snarf-http.c
+++ b/snarf-http.c
@@ -224,6 +224,9 @@ static void free_http_header(HttpHeader *h)
free(l);
l = l1;
}
+
+ free(h);
+
} /* free_http_header() */
@@ -287,6 +290,7 @@ static char *get_request(UrlResource *rsrc)
{
char *request = NULL;
char *auth = NULL;
+ char *tmp_auth = NULL;
Url *u;
u = rsrc->url;
@@ -295,34 +299,38 @@ static char *get_request(UrlResource *rsrc)
"Host: ", u->host, "\r\n", NULL);
if (u->username && u->password) {
- auth = nvstrcat(u->username, ":", u->password, NULL);
- auth = base64(auth, strlen(auth));
- request = nvstrcat(request, "Authorization: Basic ",
- auth, "\r\n", NULL);
+ tmp_auth = nvstrcat(u->username, ":", u->password, NULL);
+ auth = base64(tmp_auth, strlen(tmp_auth));
+ nvfree(tmp_auth);
+ NV_STRCAT(request, "Authorization: Basic ",
+ auth, "\r\n", NULL);
+ nvfree(auth);
}
if (rsrc->proxy_username && rsrc->proxy_password) {
- auth = nvstrcat(rsrc->proxy_username, ":",
- rsrc->proxy_password, NULL);
- auth = base64(auth, strlen(auth));
- request = nvstrcat(request, "Proxy-Authorization: Basic ",
- auth, "\r\n", NULL);
+ tmp_auth = nvstrcat(rsrc->proxy_username, ":",
+ rsrc->proxy_password, NULL);
+ auth = base64(tmp_auth, strlen(tmp_auth));
+ nvfree(tmp_auth);
+ NV_STRCAT(request, "Proxy-Authorization: Basic ",
+ auth, "\r\n", NULL);
+ nvfree(auth);
}
- request = nvstrcat(request, "User-Agent: ", PROGRAM_NAME, "/",
- NVIDIA_INSTALLER_VERSION, NULL);
+ NV_STRCAT(request, "User-Agent: ", PROGRAM_NAME, "/",
+ NVIDIA_INSTALLER_VERSION, NULL);
/* This CRLF pair closes the User-Agent key-value set. */
- request = nvstrcat(request, "\r\n", NULL);
+ NV_STRCAT(request, "\r\n", NULL);
/* If SNARF_HTTP_REFERER is set, spoof it. */
if (getenv("SNARF_HTTP_REFERER")) {
- request = nvstrcat(request, "Referer: ",
- getenv("SNARF_HTTP_REFERER"),
- "\r\n", NULL);
+ NV_STRCAT(request, "Referer: ",
+ getenv("SNARF_HTTP_REFERER"),
+ "\r\n", NULL);
}
- request = nvstrcat(request, "\r\n", NULL);
+ NV_STRCAT(request, "\r\n", NULL);
return request;
@@ -336,6 +344,7 @@ int http_transfer(UrlResource *rsrc)
Url *redir_u = NULL;
char *request = NULL;
char *raw_header = NULL;
+ char *tmp_header = NULL;
HttpHeader *header = NULL;
char *len_string = NULL;
char *new_location = NULL;
@@ -422,7 +431,7 @@ int http_transfer(UrlResource *rsrc)
bytes_read = read(sock, buf, 8);
- if (bytes_read == 0) {
+ if (bytes_read <= 0) {
close(sock);
return FALSE;
}
@@ -433,8 +442,9 @@ int http_transfer(UrlResource *rsrc)
} else {
/* skip the header */
buf[bytes_read] = '\0';
- raw_header = get_raw_header(sock);
- raw_header = nvstrcat(buf, raw_header, NULL);
+ tmp_header = get_raw_header(sock);
+ raw_header = nvstrcat(buf, tmp_header, NULL);
+ free(tmp_header);
header = make_http_header(raw_header);
/* if in expert mode, write the raw_header to the log */
diff --git a/snarf.c b/snarf.c
index 2788e4f..147fcb5 100644
--- a/snarf.c
+++ b/snarf.c
@@ -231,7 +231,7 @@ int dump_data(UrlResource *rsrc, int sock)
ui_status_begin(rsrc->op, msg, "Downloading");
}
- while ((bytes_read = read(sock, buf, SNARF_BUFSIZE))) {
+ while ((bytes_read = read(sock, buf, SNARF_BUFSIZE)) > 0) {
if (rsrc->flags & SNARF_FLAGS_STATUS_BAR) {
total_bytes_read += bytes_read;
diff --git a/update.c b/update.c
index fd3e8aa..3a7985d 100644
--- a/update.c
+++ b/update.c
@@ -195,13 +195,6 @@ char *append_update_arguments(char *s, int c, const char *arg,
if (!s) s = nvstrcat(" ", NULL);
- /*
- * don't place "--update" or "--force-update" in the update
- * argument list (avoid infinite loop)
- */
-
- if ((c == 'u') || (c == 'f')) return s;
-
do {
if (l[i].val == c) {
t = nvstrcat(s, " --", l[i].name, NULL);
@@ -230,6 +223,7 @@ static char *get_latest_driver_version_and_filename(Options *op, int *major,
int *minor, int *patch)
{
int fd = -1;
+ int length;
char *tmpfile = NULL;
char *url = NULL;
char *str = (void *) -1;
@@ -259,8 +253,10 @@ static char *get_latest_driver_version_and_filename(Options *op, int *major,
strerror(errno));
goto done;
}
+
+ length = stat_buf.st_size;
- str = mmap(0, stat_buf.st_size, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
+ str = mmap(0, length, PROT_READ, MAP_FILE | MAP_SHARED, fd, 0);
if (str == (void *) -1) {
ui_error(op, "Unable to determine most recent NVIDIA %s-%s driver "
"version (%s).", INSTALLER_OS, INSTALLER_ARCH,
@@ -268,7 +264,7 @@ static char *get_latest_driver_version_and_filename(Options *op, int *major,
goto done;
}
- buf = get_next_line(str, NULL);
+ buf = get_next_line(str, NULL, str, length);
if (!nvid_version(buf, major, minor, patch)) {
ui_error(op, "Unable to determine latest NVIDIA %s-%s driver "
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 16:31:55 +0000