From 02844d4dc0995f07dd438997ecc39bd9e3c4779b Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyu.z.wang@intel.com>
Date: Mon, 11 Aug 2008 15:16:09 +0800
Subject: Disable display clock gating for 4 series chips (cherry picked from
 commit d0018a96064ee0adfe87c2d50c341bf7d2e45eb0)

---
 src/i830_driver.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/i830_driver.c b/src/i830_driver.c
index f5aa114d..f27d9575 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -973,7 +973,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
 
     /* Disable clock gating reported to work incorrectly according to the specs.
      */
-    if (IS_GM45(pI830)) {
+    if (IS_GM45(pI830) || IS_G4X(pI830)) {
 	OUTREG(RENCLK_GATE_D1, 0);
 	OUTREG(RENCLK_GATE_D2, 0);
 	OUTREG(RAMCLK_GATE_D, 0);
-- 
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