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The code was not consistently using XV_PIPE when the desired crtc contained
any portion of the video output.
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This requires EXA 2.2 (server 1.3) for rotated performance with EXA, because
the i830_memory.c allocation may not fall within what EXA considers the
offscreen area, so the PixmapIsOffscreen hook is needed.
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This should fix issues with XV being allocated into XAA's tiled pixmap
cache and resulting bad rendering. Its also brings us closer to being able
to shrink the size of the pixmap cache on XAA, which is of limited utility.
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
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Add a new 'plane' field to the intel_crtc private structure for tracking
planes separate from pipes. This allows pre-965 chips to use plane A
on pipe B, enabling framebuffer compression for builtin LVDS displays.
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When TV does load detect, fb hasn't been setup, so we should check
that in i830_display_tiled(). Caught by Nanhai.
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Now that the driver sets these registers, they must be saved and restored.
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DSPATILEOFF and DSPBTILEOFF replace DSPASURF and DSPBSURF when the frame
buffer is in tiled mode.
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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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TV mode names used to contain the signalling standard along with the pixel
size. The signalling has been moved to the TV_FORMAT property, but the
allocation and initialization of the mode name was left a bit messy as a
result.
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Remove an extra "FBC enabled" message from i830_memory.c (only report errors
if they occur), and don't print the "forcing FBC on" message if tiling was
already enabled, as it's redundant and confusing.
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
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Conflicts:
src/i830_exa.c
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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be called many times for the same pixmap, and we don't want
to keep dividing the pitch by 4.
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Reading the docs too literally can cause you to hide bugs with false fixes...
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
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Fence setting is in mapstate actually. This fixes rotation in
tiled fb case, thanks Keith to report this.
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which do have new host bridge ids
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I probably need to release a libdrm with this interface in it now..
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CRT blanking needn't be adjusted to perform load detection on 9xx chips, and
the 8xx load detection path now adjusts blanking just during load detection.
Adjusting the blanking interval turned out to cause many monitors to fail to
sync.
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If the pipe or output have been set to DPMSOff, then load detection will not
work correctly. Also, share the load detection configuration code between
crt and tv outputs.
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Instead of always adding blanking to mode lines, use the FORCE_BORDER option
on i9xx hardware where it works, and dynamically add a bit of border if
necessary on i8xx hardware to make load detection work. This may cause
flashing when a usable crtc is not otherwise idle when load detection is
requested.
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Make it to check fence register for dest buffer.
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The upper bits would have been inappropriately dropped on G33-class hardware,
and on G965-class hardware in a 32-bit environment. The only use of physical
addresses on these should be for FBC, though, and FBC requires addresses
below 4GB. This is unresolved.
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- allow FBC and Tiling to be forced off if configured to do so
- only touch FBC registers if pI830->fb_compression is true
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