| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2007-11-15 | Move fb compression reg definition into i810_reg.h | Zhenyu Wang | 1 | -33/+0 |
| 2007-11-14 | Add more FBC regs | Jesse Barnes | 1 | -0/+2 |
| 2007-08-03 | Tiled rendering & fbc fixes: | Jesse Barnes | 1 | -0/+7 |
| 2007-07-06 | Fix naming of FBC plane enable bits (mistakenly called them pipes earlier). | Jesse Barnes | 1 | -2/+2 |
| 2007-07-03 | Fixup line length buffer padding, add kludge for front buffer tile | Jesse Barnes | 1 | -1/+2 |
| 2007-07-02 | Framebuffer compression changes: | Jesse Barnes | 1 | -0/+23 |
| 2007-04-16 | EXA: Add i830 supported pict format XRGB8888, XBGR8888 | Wang Zhenyu | 1 | -0/+2 |
| 2007-03-27 | EXA: fix i830 texture setup | Wang Zhenyu | 1 | -0/+1 |
| 2006-07-21 | Take from i915, blend ctl code cleanup. | Wang Zhenyu | 1 | -0/+16 |
| 2006-07-14 | Current exa render implement for i830 and i915, test on | Wang Zhenyu | 1 | -5/+96 |
| 2006-06-19 | Set some invarient state, cures some problems with | Alan Hourihane | 1 | -0/+637 |
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index : ~anholt/xf86-video-intel | |
| Unnamed repository; edit this file to name it for gitweb. | anholt |
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