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authorZhenyu Wang <zhenyu.z.wang@intel.com>2008-06-26 14:20:05 +0800
committerZhenyu Wang <zhenyu.z.wang@intel.com>2008-07-21 11:01:52 +0800
commita5867a55abca1d16ff57c0e39008e7c7738a724c (patch)
tree80bff5d51ccf128cec65c08606e425a2a62c7054 /src/i915_hwmc.c
parent35a40f3df2d8707f61a3f9f0d3357bfe6bd57ed6 (diff)
xvmc: only allocate memory requiring physical address on 915G
Later 945-ish chipset can use graphics address instead. (cherry picked from commit d50cec6ef9e2178ea663e58d548390f0f3da7692)
Diffstat (limited to 'src/i915_hwmc.c')
-rw-r--r--src/i915_hwmc.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/src/i915_hwmc.c b/src/i915_hwmc.c
index 973cabf8..c3451750 100644
--- a/src/i915_hwmc.c
+++ b/src/i915_hwmc.c
@@ -319,8 +319,8 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr pScrn, I915XvMCContextPriv *c
I830Ptr pI830 = I830PTR(pScrn);
int flags = ALIGN_BOTH_ENDS;
- if (IS_I915G(pI830) || IS_I915GM(pI830) ||
- IS_I945G(pI830) || IS_I945GM(pI830))
+ /* on 915G/GM, load indirect can only use physical address...sigh */
+ if (IS_I915G(pI830) || IS_I915GM(pI830))
flags |= NEED_PHYSICAL_ADDR;
if (!i830_allocate_xvmc_buffer(pScrn, "[XvMC]Static Indirect State",
@@ -353,14 +353,14 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr pScrn, I915XvMCContextPriv *c
return FALSE;
}
- if (!i830_allocate_xvmc_buffer(pScrn, "[XvMC]Correction Data Buffer",
+ if (!i830_allocate_xvmc_buffer(pScrn, "[XvMC]Correction Data Buffer",
&(ctxpriv->mcCorrdata), 512 * 1024,
ALIGN_BOTH_ENDS)) {
return FALSE;
}
- if (0)
- i830_describe_allocations(pScrn, 1, "");
+ if (1)
+ i830_describe_allocations(pScrn, 1, "i915_mc: ");
return TRUE;
}
@@ -500,29 +500,32 @@ static int i915_xvmc_create_context (ScrnInfoPtr pScrn, XvMCContextPtr pContext,
contextRec->sis.handle = ctxpriv->sis_handle;
contextRec->sis.offset = ctxpriv->mcStaticIndirectState->offset;
contextRec->sis.size = ctxpriv->mcStaticIndirectState->size;
- contextRec->sis.bus_addr = ctxpriv->mcStaticIndirectState->bus_addr;
contextRec->ssb.handle = ctxpriv->ssb_handle;
contextRec->ssb.offset = ctxpriv->mcSamplerState->offset;
contextRec->ssb.size = ctxpriv->mcSamplerState->size;
- contextRec->ssb.bus_addr = ctxpriv->mcSamplerState->bus_addr;
contextRec->msb.handle = ctxpriv->msb_handle;
contextRec->msb.offset = ctxpriv->mcMapState->offset;
contextRec->msb.size = ctxpriv->mcMapState->size;
- contextRec->msb.bus_addr = ctxpriv->mcMapState->bus_addr;
contextRec->psp.handle = ctxpriv->psp_handle;
contextRec->psp.offset = ctxpriv->mcPixelShaderProgram->offset;
contextRec->psp.size = ctxpriv->mcPixelShaderProgram->size;
- contextRec->psp.bus_addr = ctxpriv->mcPixelShaderProgram->bus_addr;
contextRec->psc.handle = ctxpriv->psc_handle;
contextRec->psc.offset = ctxpriv->mcPixelShaderConstants->offset;
contextRec->psc.size = ctxpriv->mcPixelShaderConstants->size;
- contextRec->psc.bus_addr = ctxpriv->mcPixelShaderConstants->bus_addr;
contextRec->corrdata.handle = ctxpriv->corrdata_handle;
contextRec->corrdata.offset = ctxpriv->mcCorrdata->offset;
contextRec->corrdata.size = ctxpriv->mcCorrdata->size;
contextRec->sarea_priv_offset = sizeof(XF86DRISAREARec);
contextRec->deviceID = pI830DRI->deviceID;
+ if (IS_I915G(pI830) || IS_I915GM(pI830)) {
+ contextRec->sis.bus_addr = ctxpriv->mcStaticIndirectState->bus_addr;
+ contextRec->ssb.bus_addr = ctxpriv->mcSamplerState->bus_addr;
+ contextRec->msb.bus_addr = ctxpriv->mcMapState->bus_addr;
+ contextRec->psp.bus_addr = ctxpriv->mcPixelShaderProgram->bus_addr;
+ contextRec->psc.bus_addr = ctxpriv->mcPixelShaderConstants->bus_addr;
+ }
+
pXvMC->ncontexts++;
pXvMC->contexts[i] = pContext->context_id;
pXvMC->ctxprivs[i] = ctxpriv;