diff options
| author | Jesse Barnes <jesse.barnes@intel.com> | 2008-01-30 18:59:12 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-01-30 18:59:12 +0800 |
| commit | 2e43bec8731ba1b172f7a0bf867bbb5c1adbda2d (patch) | |
| tree | 01116531e6eb61bfd2ed3a7453c0613d6d4e47d7 /src/i810_reg.h | |
| parent | bf629466a46c4037ec7b7cc5ee16be947618bd68 (diff) | |
Frame buffer compression support on new chipset
Diffstat (limited to 'src/i810_reg.h')
| -rw-r--r-- | src/i810_reg.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/i810_reg.h b/src/i810_reg.h index bed3901e..79023668 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -2634,4 +2634,28 @@ typedef enum { #define FBC_LL_SIZE (1536) #define FBC_LL_PAD (32) +/* Framebuffer compression version 2 */ +#define DPFC_CB_BASE 0x3200 +#define DPFC_CONTROL 0x3208 +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_RECOMP_CTL 0x320c +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_STATUS 0x3210 +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_STATUS2 0x3214 +#define DPFC_FENCE_YOFF 0x3218 + #endif /* _I810_REG_H */ |