diff options
| author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 17:48:59 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 17:48:59 +0000 |
| commit | 43c3223de690b892759901386d8dc936b0dfbad1 (patch) | |
| tree | cbeed9ac6c6cc5777031d72b81b155b6f4c0c580 /shared-core/radeon_drm.h | |
| parent | 408376b2031cf301f1a8e35e89ceefc72f2fdc94 (diff) | |
(Stephane Marchesin,me) Add radeon framebuffer tiling support to radeon
drm. Add new ioctls to manage surfaces which cover the tiled areas
Diffstat (limited to 'shared-core/radeon_drm.h')
| -rw-r--r-- | shared-core/radeon_drm.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h index 78c3e611..5b9d35b2 100644 --- a/shared-core/radeon_drm.h +++ b/shared-core/radeon_drm.h @@ -227,6 +227,8 @@ typedef union { #define RADEON_MAX_TEXTURE_LEVELS 12 #define RADEON_MAX_TEXTURE_UNITS 3 +#define RADEON_MAX_SURFACES 8 + /* Blits have strict offset rules. All blit offset must be aligned on * a 1K-byte boundary. */ @@ -359,6 +361,7 @@ typedef struct { int pfState; /* number of 3d windows (0,1,2ormore) */ int pfCurrentPage; /* which buffer is being displayed? */ int crtc2_base; /* CRTC2 frame offset */ + int tiling_enabled; /* set by drm, read by 2d + 3d clients */ } drm_radeon_sarea_t; /* WARNING: If you change any of these defines, make sure to change the @@ -396,6 +399,8 @@ typedef struct { #define DRM_RADEON_IRQ_WAIT 0x17 #define DRM_RADEON_CP_RESUME 0x18 #define DRM_RADEON_SETPARAM 0x19 +#define DRM_RADEON_SURF_ALLOC 0x1a +#define DRM_RADEON_SURF_FREE 0x1b #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) @@ -422,6 +427,8 @@ typedef struct { #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) +#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) +#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) typedef struct drm_radeon_init { enum { @@ -619,5 +626,19 @@ typedef struct drm_radeon_setparam { } drm_radeon_setparam_t; #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ +#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ + +/* 1.14: Clients can allocate/free a surface + */ +typedef struct drm_radeon_surface_alloc { + unsigned int address; + unsigned int size; + unsigned int flags; +} drm_radeon_surface_alloc_t; + +typedef struct drm_radeon_surface_free { + unsigned int address; +} drm_radeon_surface_free_t; + #endif |