r600: prepare for tiled blits

7 files changed, 30 insertions, 15 deletions

diff --git a/src/mesa/drivers/dri/r600/evergreen_blit.c b/src/mesa/drivers/dri/r600/evergreen_blit.c
index 1ed8a08b78..853fffe019 100644
--- a/src/mesa/drivers/dri/r600/evergreen_blit.c
+++ b/src/mesa/drivers/dri/r600/evergreen_blit.c
@@ -92,7 +92,7 @@ unsigned evergreen_check_blit(gl_format mesa_format)
 }
 
 static inline void
-eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
+eg_set_render_target(context_t *context, struct radeon_bo *bo, int dst_tiling, gl_format mesa_format,
 		     int nPitchInPixel, int w, int h, intptr_t dst_offset)
 {
     uint32_t cb_color0_base, cb_color0_info = 0;
@@ -115,7 +115,8 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
              EG_CB_COLOR0_SLICE__TILE_MAX_mask);
 
     /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
-    SETbit(cb_color0_attrib,
+    if(!dst_tiling)
+           SETbit(cb_color0_attrib,
            EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
 
     SETfield(cb_color0_info,
@@ -123,7 +124,7 @@ eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_fo
              EG_CB_COLOR0_INFO__ENDIAN_shift,
              EG_CB_COLOR0_INFO__ENDIAN_mask);
     SETfield(cb_color0_info,
-             ARRAY_LINEAR_GENERAL,
+             dst_tiling,
              EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
              EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 
@@ -578,7 +579,8 @@ eg_set_vtx_resource(context_t *context)
 
 static inline void
 eg_set_tex_resource(context_t * context,
-		    gl_format mesa_format, struct radeon_bo *bo, int w, int h,
+		    gl_format mesa_format, struct radeon_bo *bo, int src_tiling,
+                    int w, int h,
 		    int TexelPitch, intptr_t src_offset)
 {
     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource7;
@@ -587,7 +589,7 @@ eg_set_tex_resource(context_t * context,
     BATCH_LOCALS(&context->radeon);
 
     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
-    SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
+    SETfield(sq_tex_resource0, src_tiling,
                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 
@@ -1692,6 +1694,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 			struct radeon_bo *src_bo,
 			intptr_t src_offset,
 			gl_format src_mesaformat,
+			unsigned src_tiling,
 			unsigned src_pitch,
 			unsigned src_width,
 			unsigned src_height,
@@ -1700,6 +1703,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 			struct radeon_bo *dst_bo,
 			intptr_t dst_offset,
 			gl_format dst_mesaformat,
+			unsigned dst_tiling,
 			unsigned dst_pitch,
 			unsigned dst_width,
 			unsigned dst_height,
@@ -1755,7 +1759,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 
     /* src */
     /* 21 */
-    eg_set_tex_resource(context, src_mesaformat, src_bo,
+    eg_set_tex_resource(context, src_mesaformat, src_bo, src_tiling,
 			src_width, src_height, src_pitch, src_offset);
 
     /* 5 */
@@ -1763,7 +1767,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 
     /* dst */
     /* 19 */
-    eg_set_render_target(context, dst_bo, dst_mesaformat,
+    eg_set_render_target(context, dst_bo, dst_tiling, dst_mesaformat, 
 			 dst_pitch, dst_width, dst_height, dst_offset);
     /* scissors */
     /* 17 */
diff --git a/src/mesa/drivers/dri/r600/evergreen_blit.h b/src/mesa/drivers/dri/r600/evergreen_blit.h
index 68d072ecb0..88fce477db 100644
--- a/src/mesa/drivers/dri/r600/evergreen_blit.h
+++ b/src/mesa/drivers/dri/r600/evergreen_blit.h
@@ -34,6 +34,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 			struct radeon_bo *src_bo,
 			intptr_t src_offset,
 			gl_format src_mesaformat,
+			unsigned src_tiling,
 			unsigned src_pitch,
 			unsigned src_width,
 			unsigned src_height,
@@ -42,6 +43,7 @@ unsigned evergreen_blit(GLcontext *ctx,
 			struct radeon_bo *dst_bo,
 			intptr_t dst_offset,
 			gl_format dst_mesaformat,
+			unsigned dst_tiling,
 			unsigned dst_pitch,
 			unsigned dst_width,
 			unsigned dst_height,
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 3090c9f613..5e68b5b836 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -89,7 +89,7 @@ unsigned r600_check_blit(gl_format mesa_format)
 }
 
 static inline void
-set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
+set_render_target(context_t *context, struct radeon_bo *bo, int tiling, gl_format mesa_format,
                   int nPitchInPixel, int w, int h, intptr_t dst_offset)
 {
     uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
@@ -105,7 +105,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
 
     SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
-    SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
+    SETfield(cb_color0_info, tiling,
              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 
     SETbit(cb_color0_info, BLEND_BYPASS_bit);
@@ -565,7 +565,7 @@ set_vtx_resource(context_t *context)
 
 static inline void
 set_tex_resource(context_t * context,
-		 gl_format mesa_format, struct radeon_bo *bo, int w, int h,
+		 gl_format mesa_format, struct radeon_bo *bo, int tiling, int w, int h,
 		 int TexelPitch, intptr_t src_offset)
 {
     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource6;
@@ -574,7 +574,7 @@ set_tex_resource(context_t * context,
     BATCH_LOCALS(&context->radeon);
 
     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
-    SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
+    SETfield(sq_tex_resource0, tiling,
                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 
@@ -1570,6 +1570,7 @@ unsigned r600_blit(GLcontext *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
                    gl_format src_mesaformat,
+                   unsigned src_tiling,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -1578,6 +1579,7 @@ unsigned r600_blit(GLcontext *ctx,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
                    gl_format dst_mesaformat,
+                   unsigned dst_tiling,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
@@ -1633,7 +1635,7 @@ unsigned r600_blit(GLcontext *ctx,
 
     /* src */
     /* 20 */
-    set_tex_resource(context, src_mesaformat, src_bo,
+    set_tex_resource(context, src_mesaformat, src_bo, src_tiling,
 		     src_width, src_height, src_pitch, src_offset);
 
     /* 5 */
@@ -1641,7 +1643,7 @@ unsigned r600_blit(GLcontext *ctx,
 
     /* dst */
     /* 31 */
-    set_render_target(context, dst_bo, dst_mesaformat,
+    set_render_target(context, dst_bo, dst_tiling, dst_mesaformat,
 		      dst_pitch, dst_width, dst_height, dst_offset);
     /* scissors */
     /* 17 */
diff --git a/src/mesa/drivers/dri/r600/r600_blit.h b/src/mesa/drivers/dri/r600/r600_blit.h
index d56b21ba9b..814812cb5f 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.h
+++ b/src/mesa/drivers/dri/r600/r600_blit.h
@@ -34,6 +34,7 @@ unsigned r600_blit(GLcontext *ctx,
                    struct radeon_bo *src_bo,
                    intptr_t src_offset,
                    gl_format src_mesaformat,
+                   unsigned src_tiling,
                    unsigned src_pitch,
                    unsigned src_width,
                    unsigned src_height,
@@ -42,6 +43,7 @@ unsigned r600_blit(GLcontext *ctx,
                    struct radeon_bo *dst_bo,
                    intptr_t dst_offset,
                    gl_format dst_mesaformat,
+                   unsigned dst_tiling,
                    unsigned dst_pitch,
                    unsigned dst_width,
                    unsigned dst_height,
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 024e31f8ec..1281aaa722 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -532,6 +532,7 @@ struct radeon_context {
                         struct radeon_bo *src_bo,
                         intptr_t src_offset,
                         gl_format src_mesaformat,
+                        unsigned src_tiling,
                         unsigned src_pitch,
                         unsigned src_width,
                         unsigned src_height,
@@ -540,6 +541,7 @@ struct radeon_context {
                         struct radeon_bo *dst_bo,
                         intptr_t dst_offset,
                         gl_format dst_mesaformat,
+                        unsigned dst_tiling,
                         unsigned dst_pitch,
                         unsigned dst_width,
                         unsigned dst_height,
diff --git a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
index 216eb932db..6895167879 100644
--- a/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
+++ b/src/mesa/drivers/dri/radeon/radeon_pixel_read.c
@@ -158,6 +158,7 @@ do_blit_readpixels(GLcontext * ctx,
                           rrb->bo,
                           rrb->draw_offset,
                           rrb->base.Format,
+                          0,
                           rrb->pitch / rrb->cpp,
                           rrb->base.Width,
                           rrb->base.Height,
@@ -166,6 +167,7 @@ do_blit_readpixels(GLcontext * ctx,
                           dst_buffer,
                           dst_offset,
                           dst_format,
+                          0,
                           aligned_rowstride / _mesa_get_format_bytes(dst_format),
                           width,
                           height,
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
index 4cb0bb60c8..7cd8f972cf 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex_copy.c
@@ -132,9 +132,10 @@ do_copy_texsubimage(GLcontext *ctx,
     }
 
     /* blit from src buffer to texture */
-    return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
+    return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, 0,
+                             rrb->pitch/rrb->cpp,
                              src_width, rrb->base.Height, x, y,
-                             timg->mt->bo, dst_offset, dst_mesaformat,
+                             timg->mt->bo, dst_offset, dst_mesaformat, 0,
                              timg->mt->levels[level].rowstride / dst_bpp,
                              dst_width, timg->base.Height,
                              dstx, dsty, width, height, flip_y);