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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-07-17 11:56:58 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-07-17 11:56:58 +0200 |
| commit | b279b1fe5799cf653de3822ca253f5d21639d90a (patch) | |
| tree | 3e01b46fcf6741b82a19c8135db09ca4e160d07a /Documentation | |
| parent | 3e543a4d30014d45b6bb5d2095554be02153cefc (diff) | |
| parent | 788cacf308871db0a619952321bedfec8f1773e2 (diff) | |
Merge tag 'misc-habanalabs-fixes-2020-07-10' of git://people.freedesktop.org/~gabbayo/linux into char-misc-linus
This tag contains the following fixes for 5.8-rc4/5:
- Prevent user from using command WREG_BULK in PCI DMA channel. The command
won't be parsed correctly by the driver and will cause unknown behavior.
As the user doesn't need to use that command in that channel, its better
to just prevent it completely.
- Change the interface of the clock gating debugfs property from true/false
to bitmask with bit per engine. This will allow the user to debug the
ASIC while disabling the clock gating feature with fine-grain
granularity.
- Increase message-to-ASIC-CPU timeout to 4s (from 100ms/1s). The ASIC CPU
might respond sometimes after a large delay due to slow external
interfaces (such as temperature sensors) and that will result in a driver
timeout which will lead to ASIC reset.
* tag 'misc-habanalabs-fixes-2020-07-10' of git://people.freedesktop.org/~gabbayo/linux:
habanalabs: set 4s timeout for message to device CPU
habanalabs: set clock gating per engine
habanalabs: block WREG_BULK packet on PDMA
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/ABI/testing/debugfs-driver-habanalabs | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index f6d9c2a8d528..2e9ae311e02d 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -16,7 +16,16 @@ Description: Allow the root user to disable/enable in runtime the clock gating mechanism in Gaudi. Due to how Gaudi is built, the clock gating needs to be disabled in order to access the registers of the TPC and MME engines. This is sometimes needed - during debug by the user and hence the user needs this option + during debug by the user and hence the user needs this option. + The user can supply a bitmask value, each bit represents + a different engine to disable/enable its clock gating feature. + The bitmask is composed of 20 bits: + 0 - 7 : DMA channels + 8 - 11 : MME engines + 12 - 19 : TPC engines + The bit's location of a specific engine can be determined + using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values + are defined in uapi habanalabs.h file in enum gaudi_engine_id What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers Date: Jan 2019 |