diff options
| author | Marc Zyngier <maz@kernel.org> | 2022-04-19 19:27:47 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-04-20 13:00:35 +0100 |
| commit | bdcc2f280334e4e3f42a5a740494444f1026fb65 (patch) | |
| tree | a6cfcdbec6a76087dca539686ee2c75afb353e55 | |
| parent | 6a437208cb942a2dd98f7e1c3fd347ed3d425ffc (diff) | |
arm64: Add RV and RN fields for ESR_ELx_WFx_ISS
The ISS field exposed by ESR_ELx contain two additional subfields
with FEAT_WFxT:
- RN, the register number containing the timeout
- RV, indicating if the register number is valid
Describe these two fields according to the arch spec.
No functional change.
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419182755.601427-3-maz@kernel.org
| -rw-r--r-- | arch/arm64/include/asm/esr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 65c2201b11b2..15156c478054 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -133,6 +133,8 @@ #define ESR_ELx_CV (UL(1) << 24) #define ESR_ELx_COND_SHIFT (20) #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) +#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) +#define ESR_ELx_WFx_ISS_RV (UL(1) << 2) #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) |