diff options
| -rw-r--r-- | dyngen-exec.h | 62 | ||||
| -rw-r--r-- | dyngen.h | 59 |
2 files changed, 41 insertions, 80 deletions
diff --git a/dyngen-exec.h b/dyngen-exec.h index 8ceb2301d..9f5fcc6ce 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -89,21 +89,19 @@ extern int printf(const char *, ...); #undef NULL #define NULL 0 -#ifdef __i386__ +#if defined(__i386__) #define AREG0 "ebp" #define AREG1 "ebx" #define AREG2 "esi" #define AREG3 "edi" -#endif -#ifdef __x86_64__ +#elif defined(__x86_64__) #define AREG0 "r14" #define AREG1 "r15" #define AREG2 "r12" #define AREG3 "r13" //#define AREG4 "rbp" //#define AREG5 "rbx" -#endif -#ifdef __powerpc__ +#elif defined(__powerpc__) #define AREG0 "r27" #define AREG1 "r24" #define AREG2 "r25" @@ -121,14 +119,12 @@ extern int printf(const char *, ...); #endif #define USE_INT_TO_FLOAT_HELPERS #define BUGGY_GCC_DIV64 -#endif -#ifdef __arm__ +#elif defined(__arm__) #define AREG0 "r7" #define AREG1 "r4" #define AREG2 "r5" #define AREG3 "r6" -#endif -#ifdef __mips__ +#elif defined(__mips__) #define AREG0 "fp" #define AREG1 "s0" #define AREG2 "s1" @@ -138,8 +134,7 @@ extern int printf(const char *, ...); #define AREG6 "s5" #define AREG7 "s6" #define AREG8 "s7" -#endif -#ifdef __sparc__ +#elif defined(__sparc__) #ifdef HOST_SOLARIS #define AREG0 "g2" #define AREG1 "g3" @@ -168,14 +163,12 @@ extern int printf(const char *, ...); #endif #endif #define USE_FP_CONVERT -#endif -#ifdef __s390__ +#elif defined(__s390__) #define AREG0 "r10" #define AREG1 "r7" #define AREG2 "r8" #define AREG3 "r9" -#endif -#ifdef __alpha__ +#elif defined(__alpha__) /* Note $15 is the frame pointer, so anything in op-i386.c that would require a frame pointer, like alloca, would probably loose. */ #define AREG0 "$15" @@ -185,19 +178,19 @@ extern int printf(const char *, ...); #define AREG4 "$12" #define AREG5 "$13" #define AREG6 "$14" -#endif -#ifdef __mc68000 +#elif defined(__mc68000) #define AREG0 "%a5" #define AREG1 "%a4" #define AREG2 "%d7" #define AREG3 "%d6" #define AREG4 "%d5" -#endif -#ifdef __ia64__ +#elif defined(__ia64__) #define AREG0 "r7" #define AREG1 "r4" #define AREG2 "r5" #define AREG3 "r6" +#else +#error unsupported CPU #endif /* force GCC to generate only one epilog at the end of the function */ @@ -250,44 +243,37 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; #define ASM_NAME(x) #x #endif -#ifdef __i386__ +#if defined(__i386__) #define EXIT_TB() asm volatile ("ret") #define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __x86_64__ +#elif defined(__x86_64__) #define EXIT_TB() asm volatile ("ret") #define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __powerpc__ +#elif defined(__powerpc__) #define EXIT_TB() asm volatile ("blr") #define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __s390__ +#elif defined(__s390__) #define EXIT_TB() asm volatile ("br %r14") #define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __alpha__ +#elif defined(__alpha__) #define EXIT_TB() asm volatile ("ret") -#endif -#ifdef __ia64__ +#elif defined(__ia64__) #define EXIT_TB() asm volatile ("br.ret.sptk.many b0;;") #define GOTO_LABEL_PARAM(n) asm volatile ("br.sptk.many " \ ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __sparc__ +#elif defined(__sparc__) #define EXIT_TB() asm volatile ("jmpl %i0 + 8, %g0; nop") #define GOTO_LABEL_PARAM(n) asm volatile ("ba " ASM_NAME(__op_gen_label) #n ";nop") -#endif -#ifdef __arm__ +#elif defined(__arm__) #define EXIT_TB() asm volatile ("b exec_loop") #define GOTO_LABEL_PARAM(n) asm volatile ("b " ASM_NAME(__op_gen_label) #n) -#endif -#ifdef __mc68000 +#elif defined(__mc68000) #define EXIT_TB() asm volatile ("rts") -#endif -#ifdef __mips__ +#elif defined(__mips__) #define EXIT_TB() asm volatile ("jr $ra") #define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at") +#else +#error unsupported CPU #endif #endif /* !defined(__DYNGEN_EXEC_H__) */ @@ -28,25 +28,11 @@ int __op_param1, __op_param2, __op_param3; #endif int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; -#ifdef __i386__ +#if defined(__i386__) || defined(__x86_64__) || defined(__s390__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { } -#endif - -#ifdef __x86_64__ -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ -} -#endif - -#ifdef __s390__ -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ -} -#endif - -#ifdef __ia64__ +#elif defined(__ia64__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { while (start < stop) { @@ -55,9 +41,7 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop) } asm volatile (";;sync.i;;srlz.i;;"); } -#endif - -#ifdef __powerpc__ +#elif defined(__powerpc__) #define MIN_CACHE_LINE_SIZE 8 /* conservative value */ @@ -78,17 +62,12 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop) asm volatile ("sync" : : : "memory"); asm volatile ("isync" : : : "memory"); } -#endif - -#ifdef __alpha__ +#elif defined(__alpha__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { asm ("imb"); } -#endif - -#ifdef __sparc__ - +#elif defined(__sparc__) static void inline flush_icache_range(unsigned long start, unsigned long stop) { unsigned long p; @@ -99,10 +78,7 @@ static void inline flush_icache_range(unsigned long start, unsigned long stop) for (; p < stop; p += 8) __asm__ __volatile__("flush\t%0" : : "r" (p)); } - -#endif - -#ifdef __arm__ +#elif defined(__arm__) static inline void flush_icache_range(unsigned long start, unsigned long stop) { register unsigned long _beg __asm ("a1") = start; @@ -110,14 +86,22 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop) register unsigned long _flg __asm ("a3") = 0; __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); } -#endif +#elif defined(__mc68000) -#ifdef __mc68000 -#include <asm/cachectl.h> +# include <asm/cachectl.h> static inline void flush_icache_range(unsigned long start, unsigned long stop) { cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16); } +#elif defined(__mips__) + +#include <sys/cachectl.h> +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + _flush_cache ((void *)start, stop - start, BCACHE); +} +#else +#error unsupported CPU #endif #ifdef __alpha__ @@ -248,7 +232,6 @@ static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr, #ifdef __ia64 - /* Patch instruction with "val" where "mask" has 1 bits. */ static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val) { @@ -463,11 +446,3 @@ static inline void ia64_apply_fixes (uint8_t **gen_code_pp, } #endif - -#ifdef __mips__ -#include <sys/cachectl.h> -static inline void flush_icache_range(unsigned long start, unsigned long stop) -{ - _flush_cache ((void *)start, stop - start, BCACHE); -} -#endif |