diff options
author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-12-08 22:28:39 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-12-08 22:28:39 +0000 |
commit | 88920f344d5352dc0bb57539c4639344e9e0e0fe (patch) | |
tree | 828581dde703bcea895a153ea5a54f447112d7cf /target-arm | |
parent | f7cce898821ff2a050e3de7317fe05b1a3e155fb (diff) |
ARM shift fix (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1167 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r-- | target-arm/op.c | 13 | ||||
-rw-r--r-- | target-arm/translate.c | 5 |
2 files changed, 18 insertions, 0 deletions
diff --git a/target-arm/op.c b/target-arm/op.c index a27db0085..7545bb0f1 100644 --- a/target-arm/op.c +++ b/target-arm/op.c @@ -485,6 +485,11 @@ void OPPROTO op_rorl_T1_im(void) T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift)); } +void OPPROTO op_rrxl_T1(void) +{ + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); +} + /* T1 based, set C flag */ void OPPROTO op_shll_T1_im_cc(void) { @@ -512,6 +517,14 @@ void OPPROTO op_rorl_T1_im_cc(void) T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift)); } +void OPPROTO op_rrxl_T1_cc(void) +{ + uint32_t c; + c = T1 & 1; + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); + env->CF = c; +} + /* T2 based */ void OPPROTO op_shll_T2_im(void) { diff --git a/target-arm/translate.c b/target-arm/translate.c index 69bc8e224..18caa8121 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -365,6 +365,11 @@ static void disas_arm_insn(DisasContext *s) } else { gen_shift_T1_im[shiftop](shift); } + } else if (shiftop == 3) { + if (logic_cc) + gen_op_rrxl_T1_cc(); + else + gen_op_rrxl_T1(); } } else { rs = (insn >> 8) & 0xf; |