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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-25 18:15:32 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-25 18:15:32 +0000
commit26a76461f259031f2c30cd5843a5ca91e056cf03 (patch)
treeb8b67fe1ebe3cebc89dda18045dd3810dc07228a /target-arm
parent3b42c9794cb17f6af380dab2f08e1b1618f3b247 (diff)
C99 64 bit printf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/nwfpe/fpa11_cprt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/nwfpe/fpa11_cprt.c b/target-arm/nwfpe/fpa11_cprt.c
index fe295e1aa..91f2d8001 100644
--- a/target-arm/nwfpe/fpa11_cprt.c
+++ b/target-arm/nwfpe/fpa11_cprt.c
@@ -133,7 +133,7 @@ unsigned int PerformFIX(const unsigned int opcode)
case typeDouble:
{
- //printf("F%d is 0x%llx\n",Fn,fpa11->fpreg[Fn].fDouble);
+ //printf("F%d is 0x%" PRIx64 "\n",Fn,fpa11->fpreg[Fn].fDouble);
writeRegister(getRd(opcode),
float64_to_int32(fpa11->fpreg[Fn].fDouble, &fpa11->fp_status));
}