Merge branch 'master' into glsl2

21 files changed, 2858 insertions, 1055 deletions

diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile
index 8f1e1366b5..fc94ae71f4 100644
--- a/src/gallium/drivers/r600/Makefile
+++ b/src/gallium/drivers/r600/Makefile
@@ -9,6 +9,7 @@ LIBRARY_INCLUDES = \
 C_SOURCES = \
 	r600_buffer.c \
 	r600_context.c \
+	r600_shader.c \
 	r600_draw.c \
 	r600_blit.c \
 	r600_helper.c \
@@ -17,7 +18,6 @@ C_SOURCES = \
 	r600_screen.c \
 	r600_state.c \
 	r600_texture.c \
-	r600_shader.c \
 	r600_asm.c \
 	r700_asm.c
 
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index e678a2fdf2..f1dc3dc3a9 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -91,6 +91,7 @@ static int r600_bc_add_cf(struct r600_bc *bc)
 	bc->cf_last = cf;
 	bc->ncf++;
 	bc->ndw += 2;
+	bc->force_add_cf = 0;
 	return 0;
 }
 
@@ -118,7 +119,9 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 	nalu->nliteral = 0;
 
 	/* cf can contains only alu or only vtx or only tex */
-	if (bc->cf_last == NULL || bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) {
+	if (bc->cf_last == NULL || bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) ||
+		bc->force_add_cf) {
+		/* at most 128 slots, one add alu can add 4 slots + 4 constant worst case */
 		r = r600_bc_add_cf(bc);
 		if (r) {
 			free(nalu);
@@ -126,6 +129,9 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 		}
 		bc->cf_last->inst = V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3;
 	}
+	if (alu->last && (bc->cf_last->ndw >> 1) >= 124) {
+		bc->force_add_cf = 1;
+	}
 	/* number of gpr == the last gpr used in any alu */
 	for (i = 0; i < 3; i++) {
 		if (alu->src[i].sel >= bc->ngpr && alu->src[i].sel < 128) {
@@ -294,6 +300,7 @@ int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
 					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
 					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
@@ -309,6 +316,7 @@ int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
 					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 88fb957440..3fd94dbda0 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -127,6 +127,7 @@ struct r600_bc {
 	unsigned			ncf;
 	unsigned			ngpr;
 	unsigned			nresource;
+	unsigned			force_add_cf;
 	u32				*bytecode;
 };
 
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 1dcb19babc..f4eedfe4cb 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -34,31 +34,37 @@
 
 static void r600_blitter_save_states(struct r600_context *rctx)
 {
-	util_blitter_save_blend(rctx->blitter,
-					rctx->draw->state[R600_BLEND]);
-	util_blitter_save_depth_stencil_alpha(rctx->blitter,
-					rctx->draw->state[R600_DSA]);
-	util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
-	util_blitter_save_rasterizer(rctx->blitter,
-					rctx->draw->state[R600_RASTERIZER]);
-	util_blitter_save_fragment_shader(rctx->blitter,
-					rctx->ps_shader);
-	util_blitter_save_vertex_shader(rctx->blitter,
-					rctx->vs_shader);
-	util_blitter_save_vertex_elements(rctx->blitter,
-					rctx->vertex_elements);
-	util_blitter_save_viewport(rctx->blitter,
-					&rctx->viewport);
+	util_blitter_save_blend(rctx->blitter, rctx->blend);
+	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
+	if (rctx->stencil_ref) {
+		util_blitter_save_stencil_ref(rctx->blitter,
+					&rctx->stencil_ref->state.stencil_ref);
+	}
+	util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
+	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
+	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
+	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
+	if (rctx->viewport) {
+		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
+	}
 	/* XXX util_blitter_save_clip(rctx->blitter, &rctx->clip); */
 	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
-					 rctx->vertex_buffer);
+					rctx->vertex_buffer);
+
+	/* remove ptr so they don't get deleted */
+	rctx->blend = NULL;
+	rctx->vs_shader = NULL;
+	rctx->ps_shader = NULL;
+	rctx->rasterizer = NULL;
+	rctx->dsa = NULL;
+	rctx->vertex_elements = NULL;
 }
 
 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 		       const float *rgba, double depth, unsigned stencil)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->fb_state;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
@@ -73,9 +79,10 @@ static void r600_clear_render_target(struct pipe_context *pipe,
 				     unsigned width, unsigned height)
 {
 	struct r600_context *rctx = r600_context(pipe);
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
-	util_blitter_save_framebuffer(rctx->blitter, &rctx->fb_state);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
@@ -90,9 +97,10 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
 				     unsigned width, unsigned height)
 {
 	struct r600_context *rctx = r600_context(pipe);
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
-	util_blitter_save_framebuffer(rctx->blitter, &rctx->fb_state);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index bc6e336ba7..7829a479c2 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -32,10 +32,11 @@
 #include "state_tracker/drm_driver.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 
 extern struct u_resource_vtbl r600_buffer_vtbl;
 
-static u32 r600_domain_from_usage(unsigned usage)
+u32 r600_domain_from_usage(unsigned usage)
 {
 	u32 domain = RADEON_GEM_DOMAIN_GTT;
 
@@ -63,47 +64,47 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 					 const struct pipe_resource *templ)
 {
 	struct r600_screen *rscreen = r600_screen(screen);
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct radeon_bo *bo;
 	struct pb_desc desc;
 	/* XXX We probably want a different alignment for buffers and textures. */
 	unsigned alignment = 4096;
 
-	rbuffer = CALLOC_STRUCT(r600_buffer);
+	rbuffer = CALLOC_STRUCT(r600_resource);
 	if (rbuffer == NULL)
 		return NULL;
 
-	rbuffer->b.b = *templ;
-	pipe_reference_init(&rbuffer->b.b.reference, 1);
-	rbuffer->b.b.screen = screen;
-	rbuffer->b.vtbl = &r600_buffer_vtbl;
+	rbuffer->base.b = *templ;
+	pipe_reference_init(&rbuffer->base.b.reference, 1);
+	rbuffer->base.b.screen = screen;
+	rbuffer->base.vtbl = &r600_buffer_vtbl;
 
-	if (rbuffer->b.b.bind & PIPE_BIND_CONSTANT_BUFFER) {
+	if (rbuffer->base.b.bind & PIPE_BIND_CONSTANT_BUFFER) {
 		desc.alignment = alignment;
-		desc.usage = rbuffer->b.b.bind;
-		rbuffer->pb = pb_malloc_buffer_create(rbuffer->b.b.width0,
+		desc.usage = rbuffer->base.b.bind;
+		rbuffer->pb = pb_malloc_buffer_create(rbuffer->base.b.width0,
 						      &desc);
 		if (rbuffer->pb == NULL) {
 			free(rbuffer);
 			return NULL;
 		}
-		return &rbuffer->b.b;
+		return &rbuffer->base.b;
 	}
-	rbuffer->domain = r600_domain_from_usage(rbuffer->b.b.bind);
-	bo = radeon_bo(rscreen->rw, 0, rbuffer->b.b.width0, alignment, NULL);
+	rbuffer->domain = r600_domain_from_usage(rbuffer->base.b.bind);
+	bo = radeon_bo(rscreen->rw, 0, rbuffer->base.b.width0, alignment, NULL);
 	if (bo == NULL) {
 		FREE(rbuffer);
 		return NULL;
 	}
 	rbuffer->bo = bo;
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 					      void *ptr, unsigned bytes,
 					      unsigned bind)
 {
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct r600_screen *rscreen = r600_screen(screen);
 	struct pipe_resource templ;
 
@@ -116,20 +117,20 @@ struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 	templ.height0 = 1;
 	templ.depth0 = 1;
 
-	rbuffer = (struct r600_buffer*)r600_buffer_create(screen, &templ);
+	rbuffer = (struct r600_resource*)r600_buffer_create(screen, &templ);
 	if (rbuffer == NULL) {
 		return NULL;
 	}
 	radeon_bo_map(rscreen->rw, rbuffer->bo);
 	memcpy(rbuffer->bo->data, ptr, bytes);
 	radeon_bo_unmap(rscreen->rw, rbuffer->bo);
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 static void r600_buffer_destroy(struct pipe_screen *screen,
 				struct pipe_resource *buf)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)buf;
+	struct r600_resource *rbuffer = (struct r600_resource*)buf;
 	struct r600_screen *rscreen = r600_screen(screen);
 
 	if (rbuffer->pb) {
@@ -140,13 +141,14 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 	if (rbuffer->bo) {
 		radeon_bo_decref(rscreen->rw, rbuffer->bo);
 	}
+	memset(rbuffer, 0, sizeof(struct r600_resource));
 	FREE(rbuffer);
 }
 
 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				      struct pipe_transfer *transfer)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)transfer->resource;
+	struct r600_resource *rbuffer = (struct r600_resource*)transfer->resource;
 	struct r600_screen *rscreen = r600_screen(pipe->screen);
 	int write = 0;
 
@@ -166,9 +168,9 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 }
 
 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
-				       struct pipe_transfer *transfer)
+					struct pipe_transfer *transfer)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)transfer->resource;
+	struct r600_resource *rbuffer = (struct r600_resource*)transfer->resource;
 	struct r600_screen *rscreen = r600_screen(pipe->screen);
 
 	if (rbuffer->pb) {
@@ -188,7 +190,7 @@ unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
 					 struct pipe_resource *buf,
 					 unsigned face, unsigned level)
 {
-	/* XXX */
+	/* FIXME */
 	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 }
 
@@ -196,7 +198,7 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 					      struct winsys_handle *whandle)
 {
 	struct radeon *rw = (struct radeon*)screen->winsys;
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct radeon_bo *bo = NULL;
 
 	bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
@@ -204,18 +206,18 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 		return NULL;
 	}
 
-	rbuffer = CALLOC_STRUCT(r600_buffer);
+	rbuffer = CALLOC_STRUCT(r600_resource);
 	if (rbuffer == NULL) {
 		radeon_bo_decref(rw, bo);
 		return NULL;
 	}
 
-	pipe_reference_init(&rbuffer->b.b.reference, 1);
-	rbuffer->b.b.target = PIPE_BUFFER;
-	rbuffer->b.b.screen = screen;
-	rbuffer->b.vtbl = &r600_buffer_vtbl;
+	pipe_reference_init(&rbuffer->base.b.reference, 1);
+	rbuffer->base.b.target = PIPE_BUFFER;
+	rbuffer->base.b.screen = screen;
+	rbuffer->base.vtbl = &r600_buffer_vtbl;
 	rbuffer->bo = bo;
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 struct u_resource_vtbl r600_buffer_vtbl =
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 05575b5767..ae1780a1d4 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -29,9 +29,9 @@
 #include <util/u_format.h>
 #include <util/u_memory.h>
 #include <util/u_blitter.h>
-#include "r600_resource.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 #include "r600d.h"
 
 static void r600_destroy_context(struct pipe_context *context)
@@ -41,7 +41,7 @@ static void r600_destroy_context(struct pipe_context *context)
 	FREE(rctx);
 }
 
-static void r600_flush(struct pipe_context *ctx, unsigned flags,
+void r600_flush(struct pipe_context *ctx, unsigned flags,
 			struct pipe_fence_handle **fence)
 {
 	struct r600_context *rctx = r600_context(ctx);
@@ -55,7 +55,7 @@ static void r600_flush(struct pipe_context *ctx, unsigned flags,
 	 */
 	if (!dc)
 		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
-#if 0
+#if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
 	rctx->ctx = radeon_ctx_decref(rctx->ctx);
@@ -220,9 +220,9 @@ static void r600_init_config(struct r600_context *rctx)
 	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
 	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
 
-	rctx->config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -231,75 +231,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->config);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(rctx->hw_states.config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -313,9 +313,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 	rctx->context.screen = screen;
 	rctx->context.priv = priv;
 	rctx->context.destroy = r600_destroy_context;
-	rctx->context.draw_arrays = r600_draw_arrays;
-	rctx->context.draw_elements = r600_draw_elements;
-	rctx->context.draw_range_elements = r600_draw_range_elements;
+	rctx->context.draw_vbo = r600_draw_vbo;
 	rctx->context.flush = r600_flush;
 
 	/* Easy accessing of screen/winsys. */
@@ -333,20 +331,6 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 		return NULL;
 	}
 
-	rctx->cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rctx->cb_cntl);
-
 	r600_init_config(rctx);
 
 	rctx->ctx = radeon_ctx(rscreen->rw);
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 669aaec0b2..431f8951b2 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -23,6 +23,7 @@
 #ifndef R600_CONTEXT_H
 #define R600_CONTEXT_H
 
+#include <stdio.h>
 #include <pipe/p_state.h>
 #include <pipe/p_context.h>
 #include <tgsi/tgsi_scan.h>
@@ -33,16 +34,74 @@
 #include "r600_shader.h"
 
 /* XXX move this to a more appropriate place */
-struct r600_vertex_elements_state
+union pipe_states {
+	struct pipe_rasterizer_state		rasterizer;
+	struct pipe_poly_stipple		poly_stipple;
+	struct pipe_scissor_state		scissor;
+	struct pipe_clip_state			clip;
+	struct pipe_shader_state		shader;
+	struct pipe_depth_state			depth;
+	struct pipe_stencil_state		stencil;
+	struct pipe_alpha_state			alpha;
+	struct pipe_depth_stencil_alpha_state	dsa;
+	struct pipe_blend_state			blend;
+	struct pipe_blend_color			blend_color;
+	struct pipe_stencil_ref			stencil_ref;
+	struct pipe_framebuffer_state		framebuffer;
+	struct pipe_sampler_state		sampler;
+	struct pipe_sampler_view		sampler_view;
+	struct pipe_viewport_state		viewport;
+};
+
+enum pipe_state_type {
+	pipe_rasterizer_type = 1,
+	pipe_poly_stipple_type,
+	pipe_scissor_type,
+	pipe_clip_type,
+	pipe_shader_type,
+	pipe_depth_type,
+	pipe_stencil_type,
+	pipe_alpha_type,
+	pipe_dsa_type,
+	pipe_blend_type,
+	pipe_stencil_ref_type,
+	pipe_framebuffer_type,
+	pipe_sampler_type,
+	pipe_sampler_view_type,
+	pipe_viewport_type,
+	pipe_type_count
+};
+
+struct r600_context_state {
+	union pipe_states		state;
+	unsigned			refcount;
+	unsigned			type;
+	struct radeon_state		*rstate;
+	struct r600_shader		shader;
+	struct radeon_bo		*bo;
+};
+
+struct r600_vertex_element
 {
-	unsigned count;
-	struct pipe_vertex_element elements[32];
+	unsigned			refcount;
+	unsigned			count;
+	struct pipe_vertex_element	elements[32];
 };
 
-struct r600_pipe_shader {
-	struct r600_shader			shader;
-	struct radeon_bo			*bo;
-	struct radeon_state			*state;
+struct r600_context_hw_states {
+	struct radeon_state	*rasterizer;
+	struct radeon_state	*scissor;
+	struct radeon_state	*dsa;
+	struct radeon_state	*blend;
+	struct radeon_state	*viewport;
+	struct radeon_state	*cb[7];
+	struct radeon_state	*config;
+	struct radeon_state	*cb_cntl;
+	struct radeon_state	*db;
+	unsigned		ps_nresource;
+	unsigned		ps_nsampler;
+	struct radeon_state	*ps_resource[160];
+	struct radeon_state	*ps_sampler[16];
 };
 
 struct r600_context {
@@ -50,20 +109,39 @@ struct r600_context {
 	struct r600_screen		*screen;
 	struct radeon			*rw;
 	struct radeon_ctx		*ctx;
-	struct radeon_state		*cb_cntl;
-	struct radeon_state		*db;
-	struct radeon_state		*config;
-	struct r600_pipe_shader		*ps_shader;
-	struct r600_pipe_shader		*vs_shader;
+	struct blitter_context		*blitter;
+	struct radeon_draw		*draw;
+	/* hw states */
+	struct r600_context_hw_states	hw_states;
+	/* pipe states */
 	unsigned			flat_shade;
+	unsigned			ps_nsampler;
+	unsigned			vs_nsampler;
+	unsigned			ps_nsampler_view;
+	unsigned			vs_nsampler_view;
 	unsigned			nvertex_buffer;
-	struct r600_vertex_elements_state *vertex_elements;
+	struct r600_context_state	*rasterizer;
+	struct r600_context_state	*poly_stipple;
+	struct r600_context_state	*scissor;
+	struct r600_context_state	*clip;
+	struct r600_context_state	*ps_shader;
+	struct r600_context_state	*vs_shader;
+	struct r600_context_state	*depth;
+	struct r600_context_state	*stencil;
+	struct r600_context_state	*alpha;
+	struct r600_context_state	*dsa;
+	struct r600_context_state	*blend;
+	struct r600_context_state	*stencil_ref;
+	struct r600_context_state	*viewport;
+	struct r600_context_state	*framebuffer;
+	struct r600_context_state	*ps_sampler[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*vs_sampler[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*ps_sampler_view[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*vs_sampler_view[PIPE_MAX_ATTRIBS];
+	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
-	struct blitter_context		*blitter;
-	struct pipe_stencil_ref		stencil_ref;
-	struct pipe_framebuffer_state	fb_state;
-	struct radeon_draw		*draw;
-	struct pipe_viewport_state	viewport;
+	struct pipe_index_buffer	index_buffer;
+	struct pipe_blend_color         blend_color;
 };
 
 /* Convenience cast wrapper. */
@@ -72,27 +150,27 @@ static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
     return (struct r600_context*)pipe;
 }
 
-void r600_draw_arrays(struct pipe_context *ctx, unsigned mode,
-			unsigned start, unsigned count);
-void r600_draw_elements(struct pipe_context *ctx,
-		struct pipe_resource *index_buffer,
-		unsigned index_size, int index_bias, unsigned mode,
-		unsigned start, unsigned count);
-void r600_draw_range_elements(struct pipe_context *ctx,
-		struct pipe_resource *index_buffer,
-		unsigned index_size, int index_bias, unsigned min_index,
-		unsigned max_index, unsigned mode,
-		unsigned start, unsigned count);
+struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state);
+struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
+struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
+void r600_flush(struct pipe_context *ctx, unsigned flags,
+			struct pipe_fence_handle **fence);
+
+int r600_context_hw_states(struct r600_context *rctx);
+
+void r600_draw_vbo(struct pipe_context *ctx,
+                   const struct pipe_draw_info *info);
 
 void r600_init_blit_functions(struct r600_context *rctx);
 void r600_init_state_functions(struct r600_context *rctx);
 void r600_init_query_functions(struct r600_context* rctx);
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv);
 
-void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *rpshader);
-struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
-						const struct tgsi_token *tokens);
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader);
+extern int r600_pipe_shader_create(struct pipe_context *ctx,
+			struct r600_context_state *rstate,
+			const struct tgsi_token *tokens);
+extern int r600_pipe_shader_update(struct pipe_context *ctx,
+				struct r600_context_state *rstate);
 
 #define R600_ERR(fmt, args...) \
 	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 724fb6c988..2420b76318 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -33,7 +33,8 @@
 #include <util/u_memory.h>
 #include "r600_screen.h"
 #include "r600_context.h"
-#include "r600d.h"
+#include "r600_resource.h"
+#include "r600_state_inlines.h"
 
 struct r600_draw {
 	struct pipe_context	*ctx;
@@ -51,11 +52,15 @@ static int r600_draw_common(struct r600_draw *draw)
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *vs_resource;
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
+	struct pipe_vertex_buffer *vertex_buffer;
 	int r;
 
+	r = r600_context_hw_states(rctx);
+	if (r)
+		return r;
 	switch (draw->index_size) {
 	case 2:
 		vgt_draw_initiator = 0;
@@ -83,29 +88,19 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->vs_shader->state);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->ps_shader->state);
+	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->cb_cntl);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->db);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->config);
+	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
 	if (r)
 		return r;
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		rbuffer = (struct r600_buffer*)rctx->vertex_buffer[j].buffer;
-		offset = rctx->vertex_elements->elements[i].src_offset + rctx->vertex_buffer[j].buffer_offset;
-		r = r600_conv_pipe_format(rctx->vertex_elements->elements[i].src_format, &format);
-		if (r)
-			return r;
+		vertex_buffer = &rctx->vertex_buffer[j];
+		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
+		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
 		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
 		if (vs_resource == NULL)
 			return -ENOMEM;
@@ -113,7 +108,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		vs_resource->nbo = 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(rctx->vertex_buffer[j].stride) |
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
@@ -160,58 +155,39 @@ static int r600_draw_common(struct r600_draw *draw)
 		return r;
 	/* FIXME */
 	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	if (r == -EBUSY) {
+		r600_flush(draw->ctx, 0, NULL);
+		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	}
 	if (r)
 		return r;
 	rctx->draw = radeon_draw_duplicate(rctx->draw);
 	return 0;
 }
 
-void r600_draw_range_elements(struct pipe_context *ctx,
-		struct pipe_resource *index_buffer,
-		unsigned index_size, int index_bias, unsigned min_index,
-		unsigned max_index, unsigned mode,
-		unsigned start, unsigned count)
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
+	struct r600_context *rctx = r600_context(ctx);
 	struct r600_draw draw;
-	assert(index_bias == 0);
 
-	draw.ctx = ctx;
-	draw.mode = mode;
-	draw.start = start;
-	draw.count = count;
-	draw.index_size = index_size;
-	draw.index_buffer = index_buffer;
-printf("index_size %d min %d max %d  start %d  count %d\n", index_size, min_index, max_index, start, count);
-	r600_draw_common(&draw);
-}
-
-void r600_draw_elements(struct pipe_context *ctx,
-		struct pipe_resource *index_buffer,
-		unsigned index_size, int index_bias, unsigned mode,
-		unsigned start, unsigned count)
-{
-	struct r600_draw draw;
-	assert(index_bias == 0);
+	assert(info->index_bias == 0);
 
 	draw.ctx = ctx;
-	draw.mode = mode;
-	draw.start = start;
-	draw.count = count;
-	draw.index_size = index_size;
-	draw.index_buffer = index_buffer;
-	r600_draw_common(&draw);
-}
+	draw.mode = info->mode;
+	draw.start = info->start;
+	draw.count = info->count;
+	if (info->indexed && rctx->index_buffer.buffer) {
+		draw.index_size = rctx->index_buffer.index_size;
+		draw.index_buffer = rctx->index_buffer.buffer;
 
-void r600_draw_arrays(struct pipe_context *ctx, unsigned mode,
-			unsigned start, unsigned count)
-{
-	struct r600_draw draw;
-
-	draw.ctx = ctx;
-	draw.mode = mode;
-	draw.start = start;
-	draw.count = count;
-	draw.index_size = 0;
-	draw.index_buffer = NULL;
+		assert(rctx->index_buffer.offset %
+				rctx->index_buffer.index_size == 0);
+		draw.start += rctx->index_buffer.offset /
+			rctx->index_buffer.index_size;
+	}
+	else {
+		draw.index_size = 0;
+		draw.index_buffer = NULL;
+	}
 	r600_draw_common(&draw);
 }
diff --git a/src/gallium/drivers/r600/r600_helper.c b/src/gallium/drivers/r600/r600_helper.c
index 7241ab1c17..5e0e0aab57 100644
--- a/src/gallium/drivers/r600/r600_helper.c
+++ b/src/gallium/drivers/r600/r600_helper.c
@@ -30,97 +30,6 @@
 #include "r600_context.h"
 #include "r600d.h"
 
-int r600_conv_pipe_format(unsigned pformat, unsigned *format)
-{
-	switch (pformat) {
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-		*format = 0x30;
-		return 0;
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		*format = V_0280A0_COLOR_32_32_32_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_USCALED:
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_SSCALED:
-		*format = V_0280A0_COLOR_8_8_8_8;
-		return 0;
-	case PIPE_FORMAT_R32_FLOAT:
-		*format = V_0280A0_COLOR_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_R32G32_FLOAT:
-		*format = V_0280A0_COLOR_32_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L16_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-	case PIPE_FORMAT_Z32_UNORM:
-	case PIPE_FORMAT_Z32_FLOAT:
-	case PIPE_FORMAT_R64_FLOAT:
-	case PIPE_FORMAT_R64G64_FLOAT:
-	case PIPE_FORMAT_R64G64B64_FLOAT:
-	case PIPE_FORMAT_R64G64B64A64_FLOAT:
-	case PIPE_FORMAT_R32_UNORM:
-	case PIPE_FORMAT_R32G32_UNORM:
-	case PIPE_FORMAT_R32G32B32_UNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-	case PIPE_FORMAT_R32_USCALED:
-	case PIPE_FORMAT_R32G32_USCALED:
-	case PIPE_FORMAT_R32G32B32_USCALED:
-	case PIPE_FORMAT_R32G32B32A32_USCALED:
-	case PIPE_FORMAT_R32_SNORM:
-	case PIPE_FORMAT_R32G32_SNORM:
-	case PIPE_FORMAT_R32G32B32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32_SSCALED:
-	case PIPE_FORMAT_R32G32_SSCALED:
-	case PIPE_FORMAT_R32G32B32_SSCALED:
-	case PIPE_FORMAT_R32G32B32A32_SSCALED:
-	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_R16G16_UNORM:
-	case PIPE_FORMAT_R16G16B16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16_USCALED:
-	case PIPE_FORMAT_R16G16_USCALED:
-	case PIPE_FORMAT_R16G16B16_USCALED:
-	case PIPE_FORMAT_R16G16B16A16_USCALED:
-	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_R16G16_SNORM:
-	case PIPE_FORMAT_R16G16B16_SNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-	case PIPE_FORMAT_R16_SSCALED:
-	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8G8_UNORM:
-	case PIPE_FORMAT_R8G8B8_UNORM:
-	case PIPE_FORMAT_R8_USCALED:
-	case PIPE_FORMAT_R8G8_USCALED:
-	case PIPE_FORMAT_R8G8B8_USCALED:
-	case PIPE_FORMAT_R8_SNORM:
-	case PIPE_FORMAT_R8G8_SNORM:
-	case PIPE_FORMAT_R8G8B8_SNORM:
-	case PIPE_FORMAT_R8_SSCALED:
-	case PIPE_FORMAT_R8G8_SSCALED:
-	case PIPE_FORMAT_R8G8B8_SSCALED:
-	case PIPE_FORMAT_R32_FIXED:
-	case PIPE_FORMAT_R32G32_FIXED:
-	case PIPE_FORMAT_R32G32B32_FIXED:
-	case PIPE_FORMAT_R32G32B32A32_FIXED:
-	default:
-		R600_ERR("unsupported %d\n", pformat);
-		return -EINVAL;
-	}
-}
-
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 {
 	switch (pprim) {
diff --git a/src/gallium/drivers/r600/r600_resource.c b/src/gallium/drivers/r600/r600_resource.c
index d9aa1df04f..8dc411ef40 100644
--- a/src/gallium/drivers/r600/r600_resource.c
+++ b/src/gallium/drivers/r600/r600_resource.c
@@ -24,45 +24,44 @@
 #include "r600_context.h"
 #include "r600_resource.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 
-static struct pipe_resource *
-r600_resource_create(struct pipe_screen *screen,
-                    const struct pipe_resource *templ)
+static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
+						const struct pipe_resource *templ)
 {
-   if (templ->target == PIPE_BUFFER)
-      return r600_buffer_create(screen, templ);
-   else
-      return r600_texture_create(screen, templ);
+	if (templ->target == PIPE_BUFFER) {
+		return r600_buffer_create(screen, templ);
+	} else {
+		return r600_texture_create(screen, templ);
+	}
 }
 
-static struct pipe_resource *
-r600_resource_from_handle(struct pipe_screen * screen,
-			 const struct pipe_resource *templ,
-			 struct winsys_handle *whandle)
+static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * screen,
+							const struct pipe_resource *templ,
+							struct winsys_handle *whandle)
 {
-   if (templ->target == PIPE_BUFFER)
-      return NULL;
-   else
-      return r600_texture_from_handle(screen, templ, whandle);
+	if (templ->target == PIPE_BUFFER) {
+		return NULL;
+	} else {
+		return r600_texture_from_handle(screen, templ, whandle);
+	}
 }
 
 void r600_init_context_resource_functions(struct r600_context *r600)
 {
-   r600->context.get_transfer = u_get_transfer_vtbl;
-   r600->context.transfer_map = u_transfer_map_vtbl;
-   r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
-   r600->context.transfer_unmap = u_transfer_unmap_vtbl;
-   r600->context.transfer_destroy = u_transfer_destroy_vtbl;
-   r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
-   r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
+	r600->context.get_transfer = u_get_transfer_vtbl;
+	r600->context.transfer_map = u_transfer_map_vtbl;
+	r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+	r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+	r600->context.transfer_destroy = u_transfer_destroy_vtbl;
+	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
+	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
 }
 
 void r600_init_screen_resource_functions(struct r600_screen *r600screen)
 {
-   r600screen->screen.resource_create = r600_resource_create;
-   r600screen->screen.resource_from_handle = r600_resource_from_handle;
-   r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
-   r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
-   r600screen->screen.user_buffer_create = r600_user_buffer_create;
+	r600screen->screen.resource_create = r600_resource_create;
+	r600screen->screen.resource_from_handle = r600_resource_from_handle;
+	r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
+	r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
+	r600screen->screen.user_buffer_create = r600_user_buffer_create;
 }
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 95084a371b..bb90e76fb7 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -20,14 +20,47 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
+#include "util/u_transfer.h"
+
 struct r600_context;
 struct r600_screen;
 
+/* This gets further specialized into either buffer or texture
+ * structures. Use the vtbl struct to choose between the two
+ * underlying implementations.
+ */
+struct r600_resource {
+	struct u_resource		base;
+	struct radeon_bo		*bo;
+	u32				domain;
+	u32				flink;
+	struct pb_buffer		*pb;
+};
+
+struct r600_resource_texture {
+	struct r600_resource		resource;
+	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			pitch_override;
+	unsigned long			bpt;
+	unsigned long			size;
+};
+
 void r600_init_context_resource_functions(struct r600_context *r600);
 void r600_init_screen_resource_functions(struct r600_screen *r600screen);
 
+/* r600_buffer */
+u32 r600_domain_from_usage(unsigned usage);
+
+/* r600_texture */
+struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
+					const struct pipe_resource *templ);
+struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
+						const struct pipe_resource *base,
+						struct winsys_handle *whandle);
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index dec6fa8d27..4b87327a7c 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -24,15 +24,15 @@
  *      Jerome Glisse
  *      Corbin Simpson
  */
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include "r600_resource.h"
+#include <stdio.h>
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "util/u_memory.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 #include "r600_context.h"
 #include "r600_public.h"
-#include <stdio.h>
+#include "r600_resource.h"
+#include "r600_state_inlines.h"
 
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
@@ -107,7 +107,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 		return 0;
 	default:
-		debug_printf("r600: unknown param %d\n", param);
+		R600_ERR("r600: unknown param %d\n", param);
 		return 0;
 	}
 }
@@ -125,7 +125,7 @@ static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 		return 16.0f;
 	default:
-		debug_printf("r600: unsupported paramf %d\n", param);
+		R600_ERR("r600: unsupported paramf %d\n", param);
 		return 0.0f;
 	}
 }
@@ -134,108 +134,51 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
 					enum pipe_format format,
 					enum pipe_texture_target target,
 					unsigned sample_count,
-					unsigned bindings,
+					unsigned usage,
 					unsigned geom_flags)
 {
+	unsigned retval = 0;
 	if (target >= PIPE_MAX_TEXTURE_TYPES) {
-		debug_printf("r600: unsupported texture type %d\n", target);
+		R600_ERR("r600: unsupported texture type %d\n", target);
 		return FALSE;
 	}
-	switch (format) {
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B5G6R5_UNORM:
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_SRGB:
-	case PIPE_FORMAT_R8G8B8A8_SRGB:
-	case PIPE_FORMAT_DXT1_RGB:
-	case PIPE_FORMAT_DXT1_RGBA:
-	case PIPE_FORMAT_DXT3_RGBA:
-	case PIPE_FORMAT_DXT5_RGBA:
-	case PIPE_FORMAT_UYVY:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_L8A8_SRGB:
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-	case PIPE_FORMAT_Z32_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-	case PIPE_FORMAT_Z24X8_UNORM:
-		return TRUE;
-	default:
-		/* Unknown format... */
-		break;
-	}
-	return FALSE;
-}
-
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-						struct pipe_resource *texture,
-						struct pipe_subresource sr,
-						unsigned usage,
-						const struct pipe_box *box)
-{
-	struct r600_texture *rtex = (struct r600_texture*)texture;
-	struct r600_transfer *trans;
 
-	trans = CALLOC_STRUCT(r600_transfer);
-	if (trans == NULL)
-		return NULL;
-	pipe_resource_reference(&trans->transfer.resource, texture);
-	trans->transfer.sr = sr;
-	trans->transfer.usage = usage;
-	trans->transfer.box = *box;
-	trans->transfer.stride = rtex->stride[sr.level];
-	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
-	return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *trans)
-{
-	pipe_resource_reference(&trans->resource, NULL);
-	FREE(trans);
-}
+	/* Multisample */
+	if (sample_count > 1)
+		return FALSE;
 
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-				struct pipe_transfer* transfer)
-{
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct r600_texture *rtex = (struct r600_texture*)transfer->resource;
-	char *map;
-	enum pipe_format format = rtex->b.b.format;
+	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+	    r600_is_sampler_format_supported(format)) {
+		retval |= PIPE_BIND_SAMPLER_VIEW;
+	}
 
-	map = pipe_buffer_map(ctx, rtex->buffer,
-			      transfer->usage,
-			      &rtransfer->buffer_transfer);
+	if ((usage & (PIPE_BIND_RENDER_TARGET |
+                  PIPE_BIND_DISPLAY_TARGET |
+                  PIPE_BIND_SCANOUT |
+                  PIPE_BIND_SHARED)) &&
+	    r600_is_colorbuffer_format_supported(format)) {
+		retval |= usage &
+			(PIPE_BIND_RENDER_TARGET |
+			 PIPE_BIND_DISPLAY_TARGET |
+			 PIPE_BIND_SCANOUT |
+			 PIPE_BIND_SHARED);
+	}
 
-	if (!map) {
-		return NULL;
+	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+	    r600_is_zs_format_supported(format)) {
+		retval |= PIPE_BIND_DEPTH_STENCIL;
 	}
 
-	return map + rtransfer->offset +
-		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
-		transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
-}
+	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+	    r600_is_vertex_format_supported(format))
+		retval |= PIPE_BIND_VERTEX_BUFFER;
 
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-				 struct pipe_transfer* transfer)
-{
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct r600_texture *rtex = (struct r600_texture*)transfer->resource;
+	if (usage & PIPE_BIND_TRANSFER_READ)
+		retval |= PIPE_BIND_TRANSFER_READ;
+	if (usage & PIPE_BIND_TRANSFER_WRITE)
+		retval |= PIPE_BIND_TRANSFER_WRITE;
 
-	pipe_buffer_unmap(ctx, rtex->buffer, rtransfer->buffer_transfer);
+	return retval == usage;
 }
 
 static void r600_destroy_screen(struct pipe_screen* pscreen)
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 0a0286d96b..9a452ecfe3 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -40,14 +40,6 @@ struct r600_transfer {
 	unsigned			offset;
 };
 
-struct r600_buffer {
-	struct u_resource		b;
-	struct radeon_bo		*bo;
-	u32				domain;
-	u32				flink;
-	struct pb_buffer		*pb;
-};
-
 struct r600_screen {
 	struct pipe_screen		screen;
 	struct radeon			*rw;
@@ -88,17 +80,4 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 int r600_conv_pipe_format(unsigned pformat, unsigned *format);
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
 
-union r600_float_to_u32_u {
-	u32	u;
-	float	f;
-};
-
-static inline u32 r600_float_to_u32(float f)
-{
-	union r600_float_to_u32_u c;
-
-	c.f = f;
-	return c.u;
-}
-
 #endif
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index e5e6786fd0..dc8d4cb315 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -34,6 +34,30 @@
 #include <stdio.h>
 #include <errno.h>
 
+
+struct r600_shader_tgsi_instruction;
+
+struct r600_shader_ctx {
+	struct tgsi_shader_info			info;
+	struct tgsi_parse_context		parse;
+	const struct tgsi_token			*tokens;
+	unsigned				type;
+	unsigned				file_offset[TGSI_FILE_COUNT];
+	unsigned				temp_reg;
+	struct r600_shader_tgsi_instruction	*inst_info;
+	struct r600_bc				*bc;
+	struct r600_shader			*shader;
+	u32					value[4];
+};
+
+struct r600_shader_tgsi_instruction {
+	unsigned	tgsi_opcode;
+	unsigned	is_op3;
+	unsigned	r600_opcode;
+	int (*process)(struct r600_shader_ctx *ctx);
+};
+
+static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
 
 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
@@ -74,96 +98,105 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shad
 	return r600_bc_build(&shader->bc);
 }
 
-struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
-						const struct tgsi_token *tokens)
+int r600_pipe_shader_create(struct pipe_context *ctx,
+			struct r600_context_state *rpshader,
+			const struct tgsi_token *tokens)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_pipe_shader *rpshader = CALLOC_STRUCT(r600_pipe_shader);
 	int r;
 
 fprintf(stderr, "--------------------------------------------------------------\n");
 tgsi_dump(tokens, 0);
 	if (rpshader == NULL)
-		return NULL;
+		return -ENOMEM;
 	rpshader->shader.family = radeon_get_family(rscreen->rw);
 	r = r600_shader_from_tgsi(tokens, &rpshader->shader);
 	if (r) {
 		R600_ERR("translation from TGSI failed !\n");
-		goto out_err;
+		return r;
 	}
 	r = r600_bc_build(&rpshader->shader.bc);
 	if (r) {
 		R600_ERR("building bytecode failed !\n");
-		goto out_err;
+		return r;
 	}
 fprintf(stderr, "______________________________________________________________\n");
-	return rpshader;
-out_err:
-	free(rpshader);
-	return NULL;
+	return 0;
 }
 
-static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
-	unsigned i, j, tmp;
+	unsigned i, tmp;
 
-	rpshader->state = radeon_state_decref(rpshader->state);
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
 	}
-	for (i = 0, j = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name != TGSI_SEMANTIC_POSITION) {
-			tmp = rshader->output[i].sid << ((j & 3) * 8);
-			state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + j / 4] |= tmp;
-			j++;
-		}
+	/* so far never got proper semantic id from tgsi */
+	for (i = 0; i < 32; i++) {
+		tmp = i << ((i & 3) * 8);
+		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
 	}
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	rpshader->state = state;
-	rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->nbo = 2;
-	rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 2;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
-static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
-	unsigned i, tmp;
+	unsigned i, tmp, exports_ps, num_cout;
 
-	rpshader->state = radeon_state_decref(rpshader->state);
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < rshader->ninput; i++) {
-		tmp = S_028644_SEMANTIC(rshader->input[i].sid);
+		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
-		tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+			rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
 		state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
 	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			exports_ps |= (1 << (num_cout+1));
+			num_cout++;
+		}
+	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
-	rpshader->state = state;
-	rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->nbo = 1;
-	rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 1;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
@@ -197,7 +230,7 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *r
 	return r;
 }
 
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	int r;
@@ -216,29 +249,6 @@ int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *r
 	return r600_pipe_shader(ctx, rpshader);
 }
 
-struct r600_shader_tgsi_instruction;
-
-struct r600_shader_ctx {
-	struct tgsi_shader_info			info;
-	struct tgsi_parse_context		parse;
-	const struct tgsi_token			*tokens;
-	unsigned				type;
-	unsigned				file_offset[TGSI_FILE_COUNT];
-	unsigned				temp_reg;
-	struct r600_shader_tgsi_instruction	*inst_info;
-	struct r600_bc				*bc;
-	struct r600_shader			*shader;
-};
-
-struct r600_shader_tgsi_instruction {
-	unsigned	tgsi_opcode;
-	unsigned	is_op3;
-	unsigned	r600_opcode;
-	int (*process)(struct r600_shader_ctx *ctx);
-};
-
-static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
-
 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
@@ -248,10 +258,6 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 		R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
 		return -EINVAL;
 	}
-	if (i->Instruction.Saturate) {
-		R600_ERR("staturate unsupported\n");
-		return -EINVAL;
-	}
 	if (i->Instruction.Predicate) {
 		R600_ERR("predicate unsupported\n");
 		return -EINVAL;
@@ -289,6 +295,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		i = ctx->shader->ninput++;
 		ctx->shader->input[i].name = d->Semantic.Name;
 		ctx->shader->input[i].sid = d->Semantic.Index;
+		ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
 		ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
 		if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 			/* turn input into fetch */
@@ -315,6 +322,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		ctx->shader->output[i].name = d->Semantic.Name;
 		ctx->shader->output[i].sid = d->Semantic.Index;
 		ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
+		ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
 		break;
 	case TGSI_FILE_CONSTANT:
 	case TGSI_FILE_TEMPORARY:
@@ -334,7 +342,6 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	struct r600_bc_output output;
 	unsigned opcode;
 	int i, r = 0, pos0;
-	u32 value[4];
 
 	ctx.bc = &shader->bc;
 	ctx.shader = shader;
@@ -380,10 +387,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		switch (ctx.parse.FullToken.Token.Type) {
 		case TGSI_TOKEN_TYPE_IMMEDIATE:
 			immediate = &ctx.parse.FullToken.FullImmediate;
-			value[0] = immediate->u[0].Uint;
-			value[1] = immediate->u[1].Uint;
-			value[2] = immediate->u[2].Uint;
-			value[3] = immediate->u[3].Uint;
+			ctx.value[0] = immediate->u[0].Uint;
+			ctx.value[1] = immediate->u[1].Uint;
+			ctx.value[2] = immediate->u[2].Uint;
+			ctx.value[3] = immediate->u[3].Uint;
 			break;
 		case TGSI_TOKEN_TYPE_DECLARATION:
 			r = tgsi_declaration(&ctx);
@@ -399,7 +406,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			r = ctx.inst_info->process(&ctx);
 			if (r)
 				goto out_err;
-			r = r600_bc_add_literal(ctx.bc, value);
+			r = r600_bc_add_literal(ctx.bc, ctx.value);
 			if (r)
 				goto out_err;
 			break;
@@ -435,6 +442,9 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
 				output.array_base = 0;
 				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
+				output.array_base = 61;
+				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
 				r = -EINVAL;
@@ -473,30 +483,14 @@ static int tgsi_end(struct r600_shader_ctx *ctx)
 
 static int tgsi_src(struct r600_shader_ctx *ctx,
 			const struct tgsi_full_src_register *tgsi_src,
-			unsigned swizzle,
 			struct r600_bc_alu_src *r600_src)
 {
+	memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
 	r600_src->sel = tgsi_src->Register.Index;
 	if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
 		r600_src->sel = 0;
 	}
 	r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
-	switch (swizzle) {
-	case 0:
-		r600_src->chan = tgsi_src->Register.SwizzleX;
-		break;
-	case 1:
-		r600_src->chan = tgsi_src->Register.SwizzleY;
-		break;
-	case 2:
-		r600_src->chan = tgsi_src->Register.SwizzleZ;
-		break;
-	case 3:
-		r600_src->chan = tgsi_src->Register.SwizzleW;
-		break;
-	default:
-		return -EINVAL;
-	}
 	return 0;
 }
 
@@ -505,29 +499,92 @@ static int tgsi_dst(struct r600_shader_ctx *ctx,
 			unsigned swizzle,
 			struct r600_bc_alu_dst *r600_dst)
 {
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+
 	r600_dst->sel = tgsi_dst->Register.Index;
 	r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
 	r600_dst->chan = swizzle;
 	r600_dst->write = 1;
+	if (inst->Instruction.Saturate) {
+		r600_dst->clamp = 1;
+	}
+	return 0;
+}
+
+static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
+{
+	switch (swizzle) {
+	case 0:
+		return tgsi_src->Register.SwizzleX;
+	case 1:
+		return tgsi_src->Register.SwizzleY;
+	case 2:
+		return tgsi_src->Register.SwizzleZ;
+	case 3:
+		return tgsi_src->Register.SwizzleW;
+	default:
+		return 0;
+	}
+}
+
+static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, j, k, nconst, r;
+
+	for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
+		if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
+			nconst++;
+		}
+		r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
+		if (r) {
+			return r;
+		}
+	}
+	for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
+		if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
+			for (k = 0; k < 4; k++) {
+				memset(&alu, 0, sizeof(struct r600_bc_alu));
+				alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+				alu.src[0].sel = r600_src[0].sel;
+				alu.src[0].chan = k;
+				alu.dst.sel = ctx->temp_reg + j;
+				alu.dst.chan = k;
+				alu.dst.write = 1;
+				if (k == 3)
+					alu.last = 1;
+				r = r600_bc_add_alu(ctx->bc, &alu);
+				if (r)
+					return r;
+			}
+			r600_src[0].sel = ctx->temp_reg + j;
+			j--;
+		}
+	}
 	return 0;
 }
 
 static int tgsi_op2(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, j, r;
 
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+			alu.dst.chan = i;
 		} else {
 			alu.inst = ctx->inst_info->r600_opcode;
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-				r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
-				if (r)
-					return r;
+				alu.src[j] = r600_src[j];
+				alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
 			}
 			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 			if (r)
@@ -538,6 +595,9 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 		case TGSI_OPCODE_SUB:
 			alu.src[1].neg = 1;
 			break;
+		case TGSI_OPCODE_ABS:
+			alu.src[0].abs = 1;
+			break;
 		default:
 			break;
 		}
@@ -551,24 +611,52 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_kill(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, r;
+
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = ctx->inst_info->r600_opcode;
+		alu.dst.chan = i;
+		alu.src[0].sel = 248;
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
+		if (r)
+			return r;
+		alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+		if (i == 3) {
+			alu.last = 1;
+		}
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
 static int tgsi_slt(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, r;
 
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+			alu.dst.chan = i;
 		} else {
 			alu.inst = ctx->inst_info->r600_opcode;
-			r = tgsi_src(ctx, &inst->Src[0], i, &alu.src[1]);
-			if (r)
-				return r;
-			r = tgsi_src(ctx, &inst->Src[1], i, &alu.src[0]);
-			if (r)
-				return r;
+			alu.src[1] = r600_src[0];
+			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+			alu.src[0] = r600_src[1];
+			alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
 			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 			if (r)
 				return r;
@@ -587,73 +675,71 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu alu;
-
 	int r;
 
+	/* dst.x, <- 1.0  */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+	alu.src[0].sel  = 249; /*1.0*/
+	alu.src[0].chan = 0;
+	r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+	if (r)
+		return r;
+	alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
-	if (inst->Dst[0].Register.WriteMask & (1 << 0))
-	{
-		/* dst.x, <- 1.0  */
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel  = 249; /*1.0*/
-		alu.src[0].chan = 0;
-		r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
-		if (r)
-			return r;
-		if ((inst->Dst[0].Register.WriteMask & 0xe) == 0)
-			alu.last = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-	}
-
+	/* dst.y = max(src.x, 0.0) */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[1].sel  = 248; /*0.0*/
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
+	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+	if (r)
+		return r;
+	alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
-	if (inst->Dst[0].Register.WriteMask & (1 << 1))
-	{
-		/* dst.y = max(src.x, 0.0) */
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
-		r = tgsi_src(ctx, &inst->Src[0], 0, &alu.src[0]);
-		if (r)
-			return r;
-		alu.src[1].sel  = 248; /*0.0*/
-		alu.src[1].chan = 0;
-		r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
-		if (r)
-			return r;
-		if ((inst->Dst[0].Register.WriteMask & 0xa) == 0)
-			alu.last = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-	}
+	/* dst.z = NOP - fill Z slot */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+	alu.dst.chan = 2;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
-	if (inst->Dst[0].Register.WriteMask & (1 << 3))
-	{
-		/* dst.w, <- 1.0  */
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel  = 249;
-		alu.src[0].chan = 0;
-		r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
-		if (r)
-			return r;
-		if ((inst->Dst[0].Register.WriteMask & 0x4) == 0)
-			alu.last = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-	}
+	/* dst.w, <- 1.0  */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+	alu.src[0].sel  = 249;
+	alu.src[0].chan = 0;
+	r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
+	if (r)
+		return r;
+	alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
 	if (inst->Dst[0].Register.WriteMask & (1 << 2))
 	{
+		int chan;
+		int sel;
+
 		/* dst.z = log(src.y) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
-		r = tgsi_src(ctx, &inst->Src[0], 1, &alu.src[0]);
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 		if (r)
 			return r;
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
 		r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
 		if (r)
 			return r;
@@ -662,20 +748,22 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
-		int chan = alu.dst.chan;
-		int sel = alu.dst.sel;
+		chan = alu.dst.chan;
+		sel = alu.dst.sel;
 
 		/* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
-		r = tgsi_src(ctx, &inst->Src[0], 3, &alu.src[0]);
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 		if (r)
-		return r;
+			return r;
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
 		alu.src[1].sel  = sel;
 		alu.src[1].chan = chan;
-		r = tgsi_src(ctx, &inst->Src[0], 0, &alu.src[2]);
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
 		if (r)
 			return r;
+		alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 0;
 		alu.dst.write = 1;
@@ -712,9 +800,10 @@ static int tgsi_trans(struct r600_shader_ctx *ctx)
 		if (inst->Dst[0].Register.WriteMask & (1 << i)) {
 			alu.inst = ctx->inst_info->r600_opcode;
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-				r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
+				r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
 				if (r)
 					return r;
+				alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
 			}
 			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 			if (r)
@@ -728,15 +817,58 @@ static int tgsi_trans(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, j, r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = ctx->inst_info->r600_opcode;
+	for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
+		r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
+		if (r)
+			return r;
+		alu.src[j].chan = tgsi_chan(&inst->Src[j], 0);
+	}
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	/* replicate result */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.src[0].sel = ctx->temp_reg;
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.dst.chan = i;
+		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		if (r)
+			return r;
+		alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
 {
 	struct r600_bc_alu alu;
 	int i, r;
 
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+			alu.dst.chan = i;
 		} else {
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
 			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
@@ -758,17 +890,20 @@ static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instru
 static int tgsi_op3(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, j, r;
 
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
 	/* do it in 2 step as op3 doesn't support writemask */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-			r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
-			if (r)
-				return r;
+			alu.src[j] = r600_src[j];
+			alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
 		}
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
@@ -787,16 +922,19 @@ static int tgsi_op3(struct r600_shader_ctx *ctx)
 static int tgsi_dp(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, j, r;
 
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
 		for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-			r = tgsi_src(ctx, &inst->Src[j], i, &alu.src[j]);
-			if (r)
-				return r;
+			alu.src[j] = r600_src[j];
+			alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
 		}
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
@@ -832,13 +970,81 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_tex tex;
+	struct r600_bc_alu alu;
+	unsigned src_gpr;
+	int r;
+
+	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
 
+	/* Add perspective divide */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+	alu.src[0].sel = src_gpr;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 0;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 2;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+	alu.src[0].sel = 249;
+	alu.src[0].chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	src_gpr = ctx->temp_reg;
+
+	/* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
 	tex.inst = ctx->inst_info->r600_opcode;
 	tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
 	tex.sampler_id = tex.resource_id;
-	tex.src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
-	tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Src[0].Register.Index;
+	tex.src_gpr = src_gpr;
+	tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
 	tex.dst_sel_x = 0;
 	tex.dst_sel_y = 1;
 	tex.dst_sel_z = 2;
@@ -847,15 +1053,101 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	tex.src_sel_y = 1;
 	tex.src_sel_z = 2;
 	tex.src_sel_w = 3;
+
+	if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
+		tex.coord_type_x = 1;
+		tex.coord_type_y = 1;
+		tex.coord_type_z = 1;
+		tex.coord_type_w = 1;
+	}
 	return r600_bc_add_tex(ctx->bc, &tex);
 }
 
+static int tgsi_lrp(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	unsigned i;
+	int r;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+	/* 1 - src0 */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
+		alu.src[0].sel = 249;
+		alu.src[0].chan = 0;
+		alu.src[1] = r600_src[0];
+		alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+		alu.src[1].neg = 1;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = i;
+		if (i == 3) {
+			alu.last = 1;
+		}
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
+
+	/* (1 - src0) * src2 */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = i;
+		alu.src[1] = r600_src[2];
+		alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = i;
+		if (i == 3) {
+			alu.last = 1;
+		}
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
+
+	/* src0 * src1 + (1 - src0) * src2 */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+		alu.is_op3 = 1;
+		alu.src[0] = r600_src[0];
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
+		alu.src[1] = r600_src[1];
+		alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
+		alu.src[2].sel = ctx->temp_reg;
+		alu.src[2].chan = i;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = i;
+		if (i == 3) {
+			alu.last = 1;
+		}
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return tgsi_helper_copy(ctx, inst);
+}
+
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_LIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
-	{TGSI_OPCODE_RCP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_RSQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans},
+	{TGSI_OPCODE_RCP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
+	{TGSI_OPCODE_RSQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_EXP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_LOG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MUL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
@@ -863,13 +1155,13 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_DP3,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_DP4,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
 	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
 	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
 	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MAD,	1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
 	{TGSI_OPCODE_SUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-	{TGSI_OPCODE_LRP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LRP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
 	{TGSI_OPCODE_CND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{20,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -881,13 +1173,13 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_CLAMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -906,7 +1198,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, 0x10, tgsi_tex},
 	{TGSI_OPCODE_TXD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXP,	0, 0x10, tgsi_tex},
 	{TGSI_OPCODE_UP2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -975,7 +1267,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_CALLNZ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_IFC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_BREAKC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_KIL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},  /* conditional kill */
+	{TGSI_OPCODE_KIL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* conditional kill */
 	{TGSI_OPCODE_END,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
 	/* gap */
 	{118,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 23b6a83b9a..ee0381e8bd 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -29,6 +29,7 @@ struct r600_shader_io {
 	unsigned		name;
 	unsigned		gpr;
 	int			sid;
+	unsigned		interpolate;
 };
 
 struct r600_shader {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 84a13e4ef7..deb9bf3395 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -24,36 +24,600 @@
  *      Jerome Glisse
  */
 #include <stdio.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
+#include <errno.h>
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "util/u_memory.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 #include "r600d.h"
+#include "r600_state_inlines.h"
 
+static void *r600_create_blend_state(struct pipe_context *ctx,
+					const struct pipe_blend_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_blend_type, state);
+}
+
+static void *r600_create_dsa_state(struct pipe_context *ctx,
+					const struct pipe_depth_stencil_alpha_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_dsa_type, state);
+}
+
+static void *r600_create_rs_state(struct pipe_context *ctx,
+					const struct pipe_rasterizer_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_rasterizer_type, state);
+}
+
+static void *r600_create_sampler_state(struct pipe_context *ctx,
+					const struct pipe_sampler_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_sampler_type, state);
+}
+
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+				      struct pipe_sampler_view *state)
+{
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	r600_context_state_decref(rstate);
+}
+
+static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
+							struct pipe_resource *texture,
+							const struct pipe_sampler_view *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_sampler_type, state);
+	pipe_reference(NULL, &texture->reference);
+	rstate->state.sampler_view.texture = texture;
+	rstate->state.sampler_view.reference.count = 1;
+	rstate->state.sampler_view.context = ctx;
+	return &rstate->state.sampler_view;
+}
+
+static void *r600_create_shader_state(struct pipe_context *ctx,
+					const struct pipe_shader_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_shader_type, state);
+}
+
+static void *r600_create_vertex_elements(struct pipe_context *ctx,
+				unsigned count,
+				const struct pipe_vertex_element *elements)
+{
+	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+	assert(count < 32);
+	v->count = count;
+	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+	v->refcount = 1;
+	return v;
+}
+
+static void r600_bind_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	if (state == NULL)
+		return;
+	switch (rstate->type) {
+	case pipe_rasterizer_type:
+		rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
+		rctx->rasterizer = r600_context_state_incref(rstate);
+		break;
+	case pipe_poly_stipple_type:
+		rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
+		rctx->poly_stipple = r600_context_state_incref(rstate);
+		break;
+	case pipe_scissor_type:
+		rctx->scissor = r600_context_state_decref(rctx->scissor);
+		rctx->scissor = r600_context_state_incref(rstate);
+		break;
+	case pipe_clip_type:
+		rctx->clip = r600_context_state_decref(rctx->clip);
+		rctx->clip = r600_context_state_incref(rstate);
+		break;
+	case pipe_depth_type:
+		rctx->depth = r600_context_state_decref(rctx->depth);
+		rctx->depth = r600_context_state_incref(rstate);
+		break;
+	case pipe_stencil_type:
+		rctx->stencil = r600_context_state_decref(rctx->stencil);
+		rctx->stencil = r600_context_state_incref(rstate);
+		break;
+	case pipe_alpha_type:
+		rctx->alpha = r600_context_state_decref(rctx->alpha);
+		rctx->alpha = r600_context_state_incref(rstate);
+		break;
+	case pipe_dsa_type:
+		rctx->dsa = r600_context_state_decref(rctx->dsa);
+		rctx->dsa = r600_context_state_incref(rstate);
+		break;
+	case pipe_blend_type:
+		rctx->blend = r600_context_state_decref(rctx->blend);
+		rctx->blend = r600_context_state_incref(rstate);
+		break;
+	case pipe_framebuffer_type:
+		rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
+		rctx->framebuffer = r600_context_state_incref(rstate);
+		break;
+	case pipe_stencil_ref_type:
+		rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
+		rctx->stencil_ref = r600_context_state_incref(rstate);
+		break;
+	case pipe_viewport_type:
+		rctx->viewport = r600_context_state_decref(rctx->viewport);
+		rctx->viewport = r600_context_state_incref(rstate);
+		break;
+	case pipe_shader_type:
+	case pipe_sampler_type:
+	case pipe_sampler_view_type:
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		return;
+	}
+}
+
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
+	rctx->ps_shader = r600_context_state_incref(rstate);
+}
+
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
+	rctx->vs_shader = r600_context_state_incref(rstate);
+}
+
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	if (v == NULL)
+		return;
+	if (--v->refcount)
+		return;
+	free(v);
+}
+
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	r600_delete_vertex_element(ctx, rctx->vertex_elements);
+	rctx->vertex_elements = v;
+	if (v) {
+		v->refcount++;
+	}
+}
+
+static void r600_bind_ps_sampler(struct pipe_context *ctx,
+					unsigned count, void **states)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->ps_nsampler; i++) {
+		rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
+	}
+	rctx->ps_nsampler = count;
+}
+
+static void r600_bind_vs_sampler(struct pipe_context *ctx,
+					unsigned count, void **states)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->vs_nsampler; i++) {
+		rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
+	}
+	rctx->vs_nsampler = count;
+}
 
 static void r600_delete_state(struct pipe_context *ctx, void *state)
 {
-	struct radeon_state *rstate = state;
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
 
-	radeon_state_decref(rstate);
+	r600_context_state_decref(rstate);
 }
 
-static void *r600_create_blend_state(struct pipe_context *ctx,
-					const struct pipe_blend_state *state)
+static void r600_set_blend_color(struct pipe_context *ctx,
+					const struct pipe_blend_color *color)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	rctx->blend_color = *color;
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+				const struct pipe_clip_state *state)
+{
+}
+
+static void r600_set_constant_buffer(struct pipe_context *ctx,
+					uint shader, uint index,
+					struct pipe_resource *buffer)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned nconstant = 0, i, type, id;
 	struct radeon_state *rstate;
+	struct pipe_transfer *transfer;
+	u32 *ptr;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		id = R600_VS_CONSTANT;
+		type = R600_VS_CONSTANT_TYPE;
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		id = R600_PS_CONSTANT;
+		type = R600_PS_CONSTANT_TYPE;
+		break;
+	default:
+		R600_ERR("unsupported %d\n", shader);
+		return;
+	}
+	if (buffer && buffer->width0 > 0) {
+		nconstant = buffer->width0 / 16;
+		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
+		if (ptr == NULL)
+			return;
+		for (i = 0; i < nconstant; i++) {
+			rstate = radeon_state(rscreen->rw, type, id + i);
+			if (rstate == NULL)
+				return;
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
+			if (radeon_state_pm4(rstate))
+				return;
+			if (radeon_draw_set_new(rctx->draw, rstate))
+				return;
+		}
+		pipe_buffer_unmap(ctx, buffer, transfer);
+	}
+}
+
+static void r600_set_ps_sampler_view(struct pipe_context *ctx,
+					unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->ps_nsampler_view; i++) {
+		rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
+	}
+	rctx->ps_nsampler_view = count;
+}
+
+static void r600_set_vs_sampler_view(struct pipe_context *ctx,
+					unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->vs_nsampler_view; i++) {
+		rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
+	}
+	rctx->vs_nsampler_view = count;
+}
+
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+					const struct pipe_framebuffer_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_polygon_stipple(struct pipe_context *ctx,
+					 const struct pipe_poly_stipple *state)
+{
+}
+
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void r600_set_scissor_state(struct pipe_context *ctx,
+					const struct pipe_scissor_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_scissor_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_stencil_ref(struct pipe_context *ctx,
+				const struct pipe_stencil_ref *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_vertex_buffers(struct pipe_context *ctx,
+					unsigned count,
+					const struct pipe_vertex_buffer *buffers)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned i;
+
+	for (i = 0; i < rctx->nvertex_buffer; i++) {
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	}
+	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+	for (i = 0; i < count; i++) {
+		rctx->vertex_buffer[i].buffer = NULL;
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	}
+	rctx->nvertex_buffer = count;
+}
+
+static void r600_set_index_buffer(struct pipe_context *ctx,
+				  const struct pipe_index_buffer *ib)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	if (ib) {
+		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+	} else {
+		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+	}
+
+	/* TODO make this more like a state */
+}
+
+static void r600_set_viewport_state(struct pipe_context *ctx,
+					const struct pipe_viewport_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_viewport_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+void r600_init_state_functions(struct r600_context *rctx)
+{
+	rctx->context.create_blend_state = r600_create_blend_state;
+	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
+	rctx->context.create_fs_state = r600_create_shader_state;
+	rctx->context.create_rasterizer_state = r600_create_rs_state;
+	rctx->context.create_sampler_state = r600_create_sampler_state;
+	rctx->context.create_sampler_view = r600_create_sampler_view;
+	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
+	rctx->context.create_vs_state = r600_create_shader_state;
+	rctx->context.bind_blend_state = r600_bind_state;
+	rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
+	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
+	rctx->context.bind_fs_state = r600_bind_ps_shader;
+	rctx->context.bind_rasterizer_state = r600_bind_state;
+	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
+	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
+	rctx->context.bind_vs_state = r600_bind_vs_shader;
+	rctx->context.delete_blend_state = r600_delete_state;
+	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
+	rctx->context.delete_fs_state = r600_delete_state;
+	rctx->context.delete_rasterizer_state = r600_delete_state;
+	rctx->context.delete_sampler_state = r600_delete_state;
+	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
+	rctx->context.delete_vs_state = r600_delete_state;
+	rctx->context.set_blend_color = r600_set_blend_color;
+	rctx->context.set_clip_state = r600_set_clip_state;
+	rctx->context.set_constant_buffer = r600_set_constant_buffer;
+	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
+	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
+	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
+	rctx->context.set_sample_mask = r600_set_sample_mask;
+	rctx->context.set_scissor_state = r600_set_scissor_state;
+	rctx->context.set_stencil_ref = r600_set_stencil_ref;
+	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+	rctx->context.set_index_buffer = r600_set_index_buffer;
+	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
+	rctx->context.set_viewport_state = r600_set_viewport_state;
+	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
+}
+
+struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
+{
+	if (rstate == NULL)
+		return NULL;
+	rstate->refcount++;
+	return rstate;
+}
+
+struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
+{
+	unsigned i;
+
+	if (rstate == NULL)
+		return NULL;
+	if (--rstate->refcount)
+		return NULL;
+	switch (rstate->type) {
+	case pipe_sampler_view_type:
+		pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
+		break;
+	case pipe_framebuffer_type:
+		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
+			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
+		}
+		pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
+		break;
+	case pipe_viewport_type:
+	case pipe_depth_type:
+	case pipe_rasterizer_type:
+	case pipe_poly_stipple_type:
+	case pipe_scissor_type:
+	case pipe_clip_type:
+	case pipe_stencil_type:
+	case pipe_alpha_type:
+	case pipe_dsa_type:
+	case pipe_blend_type:
+	case pipe_stencil_ref_type:
+	case pipe_shader_type:
+	case pipe_sampler_type:
+		break;
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		return NULL;
+	}
+	radeon_state_decref(rstate->rstate);
+	FREE(rstate);
+	return NULL;
+}
+
+struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
+{
+	struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
+	const union pipe_states *states = state;
+	unsigned i;
+	int r;
+
+	if (rstate == NULL)
+		return NULL;
+	rstate->type = type;
+	rstate->refcount = 1;
+
+	switch (rstate->type) {
+	case pipe_sampler_view_type:
+		rstate->state.sampler_view = (*states).sampler_view;
+		rstate->state.sampler_view.texture = NULL;
+		break;
+	case pipe_framebuffer_type:
+		rstate->state.framebuffer = (*states).framebuffer;
+		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
+			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
+						(*states).framebuffer.cbufs[i]);
+		}
+		pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
+					(*states).framebuffer.zsbuf);
+		break;
+	case pipe_viewport_type:
+		rstate->state.viewport = (*states).viewport;
+		break;
+	case pipe_depth_type:
+		rstate->state.depth = (*states).depth;
+		break;
+	case pipe_rasterizer_type:
+		rstate->state.rasterizer = (*states).rasterizer;
+		break;
+	case pipe_poly_stipple_type:
+		rstate->state.poly_stipple = (*states).poly_stipple;
+		break;
+	case pipe_scissor_type:
+		rstate->state.scissor = (*states).scissor;
+		break;
+	case pipe_clip_type:
+		rstate->state.clip = (*states).clip;
+		break;
+	case pipe_stencil_type:
+		rstate->state.stencil = (*states).stencil;
+		break;
+	case pipe_alpha_type:
+		rstate->state.alpha = (*states).alpha;
+		break;
+	case pipe_dsa_type:
+		rstate->state.dsa = (*states).dsa;
+		break;
+	case pipe_blend_type:
+		rstate->state.blend = (*states).blend;
+		break;
+	case pipe_stencil_ref_type:
+		rstate->state.stencil_ref = (*states).stencil_ref;
+		break;
+	case pipe_shader_type:
+		rstate->state.shader = (*states).shader;
+		r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
+		if (r) {
+			r600_context_state_decref(rstate);
+			return NULL;
+		}
+		break;
+	case pipe_sampler_type:
+		rstate->state.sampler = (*states).sampler;
+		break;
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		FREE(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blend(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	const struct pipe_blend_state *state = &rctx->blend->state.blend;
+	int i;
 
 	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
-	rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
+	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
+	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
+	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
+	rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
+	rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
@@ -62,6 +626,36 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
 	rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
+
+	for (i = 0; i < 8; i++) {
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+		uint32_t bc = 0;
+
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
+			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+		}
+
+		rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
+		if (i == 0)
+			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
+	}
+
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -69,38 +663,25 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
 	return rstate;
 }
 
-static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
-}
-
-static void r600_set_blend_color(struct pipe_context *ctx,
-					const struct pipe_blend_color *color)
+static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 {
-}
-
-static void r600_set_clip_state(struct pipe_context *ctx,
-				const struct pipe_clip_state *state)
-{
-}
-
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
-					const struct pipe_framebuffer_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_texture *rtex;
-	struct r600_buffer *rbuffer;
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
-	unsigned level = state->cbufs[0]->level;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
+	unsigned level = state->cbufs[cb]->level;
 	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+	int id = R600_CB0 + cb;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, id);
 	if (rstate == NULL)
-		return;
-	rtex = (struct r600_texture*)state->cbufs[0]->texture;
-	rbuffer = (struct r600_buffer*)rtex->buffer;
+		return NULL;
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -108,10 +689,25 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 3;
-	pitch = rtex->pitch[level] / 8 - 1;
-	slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_SOURCE_FORMAT(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
@@ -120,71 +716,85 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
-		return;
+		return NULL;
 	}
-	radeon_draw_set_new(rctx->draw, rstate);
-	rctx->db = radeon_state_decref(rctx->db);
-	if(state->zsbuf) {
-		rtex = (struct r600_texture*)state->zsbuf->texture;
-		rbuffer = (struct r600_buffer*)rtex->buffer;
-		rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
-		if(rctx->db == NULL)
-		     return;
-		rctx->db->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		rctx->db->nbo = 1;
-		rctx->db->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-		level = state->zsbuf->level;
-		pitch = rtex->pitch[level] / 8 - 1;
-		slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
-
-		rctx->db->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
-		rctx->db->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
-		rctx->db->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-		rctx->db->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-		rctx->db->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	} else 
-		rctx->db = NULL;
-	rctx->fb_state = *state;
-}
-
-static void *r600_create_fs_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *shader)
-{
-	return r600_pipe_shader_create(ctx, shader->tokens);
-}
-
-static void r600_bind_fs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	rctx->ps_shader = state;
+	return rstate;
 }
 
-static void *r600_create_vs_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *shader)
+static struct radeon_state *r600_db(struct r600_context *rctx)
 {
-	return r600_pipe_shader_create(ctx, shader->tokens);
-}
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
+	unsigned level = state->cbufs[0]->level;
+	unsigned pitch, slice, format;
 
-static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
+	if (state->zsbuf == NULL)
+		return NULL;
 
-	rctx->vs_shader = state;
-}
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	if (rstate == NULL)
+		return NULL;
 
-static void r600_set_polygon_stipple(struct pipe_context *ctx,
-					 const struct pipe_poly_stipple *state)
-{
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rbuffer = &rtex->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	level = state->zsbuf->level;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
+					S_028010_FORMAT(format);
+	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
+	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+						S_028000_SLICE_TILE_MAX(slice);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static void *r600_create_rs_state(struct pipe_context *ctx,
-					const struct pipe_rasterizer_state *state)
+static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
+	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	float offset_units = 0, offset_scale = 0;
+	char depth = 0;
+	unsigned offset_db_fmt_cntl = 0;
+
+	if (fb->zsbuf) {
+		offset_units = state->offset_units;
+		offset_scale = state->offset_scale * 12.0f;
+		switch (fb->zsbuf->texture->format) {
+		case PIPE_FORMAT_Z24X8_UNORM:
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			depth = -24;
+			offset_units *= 2.0f;
+			break;
+		case PIPE_FORMAT_Z32_FLOAT:
+			depth = -23;
+			offset_units *= 1.0f;
+			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			depth = -16;
+			offset_units *= 4.0f;
+			break;
+		default:
+			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
+			return NULL;
+		}
+	}
+	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
 	rctx->flat_shade = state->flatshade;
 	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
@@ -192,7 +802,13 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000;
+	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
+			S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+			S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+			S_028814_FACE(!state->front_ccw) |
+			S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+			S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+			S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
 	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
@@ -205,12 +821,12 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
 	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -218,56 +834,10 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
 	return rstate;
 }
 
-static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
-}
-
-static void *r600_create_sampler_state(struct pipe_context *ctx,
-					const struct pipe_sampler_state *state)
-{
-	return NULL;
-}
-
-static void r600_bind_sampler_states(struct pipe_context *ctx,
-					unsigned count, void **states)
-{
-}
-
-static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
-							  struct pipe_resource *texture,
-							  const struct pipe_sampler_view *templ)
-{
-	struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
-
-	*view = *templ;
-	return view;
-}
-
-static void r600_sampler_view_destroy(struct pipe_context *ctx,
-				      struct pipe_sampler_view *view)
+static struct radeon_state *r600_scissor(struct r600_context *rctx)
 {
-	FREE(view);
-}
-
-static void r600_set_fragment_sampler_views(struct pipe_context *ctx,
-					    unsigned count,
-					    struct pipe_sampler_view **views)
-{
-}
-
-static void r600_set_vertex_sampler_views(struct pipe_context *ctx,
-					  unsigned count,
-					  struct pipe_sampler_view **views)
-{
-}
-
-static void r600_set_scissor_state(struct pipe_context *ctx,
-					const struct pipe_scissor_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
+	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 	u32 tl, br;
 
@@ -275,7 +845,7 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
 	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
 	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 	if (rstate == NULL)
-		return;
+		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
@@ -297,97 +867,104 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
-		return;
+		return NULL;
 	}
-	radeon_draw_set_new(rctx->draw, rstate);
+	return rstate;
 }
 
-static void r600_set_viewport_state(struct pipe_context *ctx,
-					const struct pipe_viewport_state *state)
+static struct radeon_state *r600_viewport(struct r600_context *rctx)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
+	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
 	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 	if (rstate == NULL)
-		return;
+		return NULL;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = r600_float_to_u32(state->scale[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = r600_float_to_u32(state->scale[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = r600_float_to_u32(state->scale[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = r600_float_to_u32(state->translate[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = r600_float_to_u32(state->translate[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = r600_float_to_u32(state->translate[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
-		return;
+		return NULL;
 	}
-	radeon_draw_set_new(rctx->draw, rstate);
-	rctx->viewport = *state;
-}
-
-static void r600_set_vertex_buffers(struct pipe_context *ctx,
-					unsigned count,
-					const struct pipe_vertex_buffer *buffers)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
-	rctx->nvertex_buffer = count;
+	return rstate;
 }
 
-
-static void *r600_create_vertex_elements_state(struct pipe_context *ctx,
-					       unsigned count,
-					       const struct pipe_vertex_element *elements)
+static struct radeon_state *r600_dsa(struct r600_context *rctx)
 {
-	struct r600_vertex_elements_state *v = CALLOC_STRUCT(r600_vertex_elements_state);
+	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
+	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
+	struct r600_screen *rscreen = rctx->screen;
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf;
+	struct r600_shader *rshader = &rctx->ps_shader->shader;
+	struct radeon_state *rstate;
+	int i;
 
-	assert(count < 32);
-	v->count = count;
-	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
-	return v;
-}
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	if (rstate == NULL)
+		return NULL;
 
-static void r600_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_vertex_elements_state *v = (struct r600_vertex_elements_state*)state;
+	db_shader_control = 0x210;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			db_shader_control |= 1;
+	}
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+	/* set stencil enable */
 
-	rctx->vertex_elements = v;
-}
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 
-static void r600_delete_vertex_elements_state(struct pipe_context *ctx, void *state)
-{
-	FREE(state);
-}
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+			stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
+		}
+	}
 
-static void *r600_create_dsa_state(struct pipe_context *ctx,
-					const struct pipe_depth_stencil_alpha_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct radeon_state *rstate;
-	unsigned db_depth_control;
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+		alpha_ref = fui(state->alpha.ref_value);
+	}
 
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
-	if (rstate == NULL)
-		return NULL;
-	db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
-	
 	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
-	rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
-	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
-	rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
+	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
+	rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
+	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
+	rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
 	rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
+	rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
 	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
@@ -400,105 +977,381 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
 	return rstate;
 }
 
-static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
+static inline unsigned r600_tex_wrap(unsigned wrap)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
+	switch (wrap) {
+	default:
+	case PIPE_TEX_WRAP_REPEAT:
+		return V_03C000_SQ_TEX_WRAP;
+	case PIPE_TEX_WRAP_CLAMP:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_CLAMP_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_REPEAT:
+		return V_03C000_SQ_TEX_MIRROR;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+	}
 }
 
-static void r600_set_constant_buffer(struct pipe_context *ctx,
-				     uint shader, uint index,
-				     struct pipe_resource *buffer)
+static inline unsigned r600_tex_filter(unsigned filter)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, type, id;
+	switch (filter) {
+	default:
+	case PIPE_TEX_FILTER_NEAREST:
+		return V_03C000_SQ_TEX_XY_FILTER_POINT;
+	case PIPE_TEX_FILTER_LINEAR:
+		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+	}
+}
+
+static inline unsigned r600_tex_mipfilter(unsigned filter)
+{
+	switch (filter) {
+	case PIPE_TEX_MIPFILTER_NEAREST:
+		return V_03C000_SQ_TEX_Z_FILTER_POINT;
+	case PIPE_TEX_MIPFILTER_LINEAR:
+		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+	default:
+	case PIPE_TEX_MIPFILTER_NONE:
+		return V_03C000_SQ_TEX_Z_FILTER_NONE;
+	}
+}
+
+static inline unsigned r600_tex_compare(unsigned compare)
+{
+	switch (compare) {
+	default:
+	case PIPE_FUNC_NEVER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+	case PIPE_FUNC_LESS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+	case PIPE_FUNC_EQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+	case PIPE_FUNC_GREATER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+	case PIPE_FUNC_NOTEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+	}
+}
+
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+
+static struct radeon_state *r600_sampler(struct r600_context *rctx,
+				const struct pipe_sampler_state *state,
+				unsigned id)
+{
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	struct pipe_transfer *transfer;
-	u32 *ptr;
 
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		id = R600_VS_CONSTANT;
-		type = R600_VS_CONSTANT_TYPE;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		id = R600_PS_CONSTANT;
-		type = R600_PS_CONSTANT_TYPE;
-		break;
+	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
+	/* FIXME LOD it depends on texture base level ... */
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
+			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static inline unsigned r600_tex_swizzle(unsigned swizzle)
+{
+	switch (swizzle) {
+	case PIPE_SWIZZLE_RED:
+		return V_038010_SQ_SEL_X;
+	case PIPE_SWIZZLE_GREEN:
+		return V_038010_SQ_SEL_Y;
+	case PIPE_SWIZZLE_BLUE:
+		return V_038010_SQ_SEL_Z;
+	case PIPE_SWIZZLE_ALPHA:
+		return V_038010_SQ_SEL_W;
+	case PIPE_SWIZZLE_ZERO:
+		return V_038010_SQ_SEL_0;
 	default:
-		fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
-		return;
+	case PIPE_SWIZZLE_ONE:
+		return V_038010_SQ_SEL_1;
 	}
-	if (buffer && buffer->width0 > 0) {
-		nconstant = buffer->width0 / 16;
-		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
-		if (ptr == NULL)
-			return;
-		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, type, id + i);
-			if (rstate == NULL)
-				return;
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
-			if (radeon_state_pm4(rstate))
-				return;
-			if (radeon_draw_set_new(rctx->draw, rstate))
-				return;
-		}
-		pipe_buffer_unmap(ctx, buffer, transfer);
+}
+
+static inline unsigned r600_format_type(unsigned format_type)
+{
+	switch (format_type) {
+	default:
+	case UTIL_FORMAT_TYPE_UNSIGNED:
+		return V_038010_SQ_FORMAT_COMP_UNSIGNED;
+	case UTIL_FORMAT_TYPE_SIGNED:
+		return V_038010_SQ_FORMAT_COMP_SIGNED;
+	case UTIL_FORMAT_TYPE_FIXED:
+		return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
 	}
 }
 
-static void r600_set_stencil_ref(struct pipe_context *ctx,
-				const struct pipe_stencil_ref *sr)
+static inline unsigned r600_tex_dim(unsigned dim)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	rctx->stencil_ref = *sr;
+	switch (dim) {
+	default:
+	case PIPE_TEXTURE_1D:
+		return V_038000_SQ_TEX_DIM_1D;
+	case PIPE_TEXTURE_2D:
+		return V_038000_SQ_TEX_DIM_2D;
+	case PIPE_TEXTURE_3D:
+		return V_038000_SQ_TEX_DIM_3D;
+	case PIPE_TEXTURE_CUBE:
+		return V_038000_SQ_TEX_DIM_CUBEMAP;
+	}
 }
 
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+static struct radeon_state *r600_resource(struct r600_context *rctx,
+					const struct pipe_sampler_view *view,
+					unsigned id)
 {
+	struct r600_screen *rscreen = rctx->screen;
+	const struct util_format_description *desc;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
+	unsigned format;
+
+	format = r600_translate_colorformat(view->texture->format);
+	if (format == ~0)
+		return NULL;
+	desc = util_format_description(view->texture->format);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", view->texture->format);
+		return NULL;
+	}
+	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	if (rstate == NULL) {
+		return NULL;
+	}
+	tmp = (struct r600_resource_texture*)view->texture;
+	rbuffer = &tmp->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 2;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
+
+	/* FIXME properly handle first level != 0 */
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
+			S_038000_DIM(r600_tex_dim(view->texture->target)) |
+			S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
+			S_038000_TEX_WIDTH(view->texture->width0 - 1);
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
+			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
+			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
+			S_038004_DATA_FORMAT(format);
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
+			S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
+			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
+			S_038010_REQUEST_SIZE(1) |
+			S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
+			S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
+			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
+			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
+		        S_038010_FORCE_DEGAMMA(desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB ? 1 : 0) |
+			S_038010_BASE_LEVEL(view->first_level);
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
+			S_038014_LAST_LEVEL(view->last_level) |
+			S_038014_BASE_ARRAY(0) |
+			S_038014_LAST_ARRAY(0);
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
+			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-void r600_init_state_functions(struct r600_context *rctx)
+static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 {
-	rctx->context.set_sample_mask = r600_set_sample_mask;
-	rctx->context.create_blend_state = r600_create_blend_state;
-	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.delete_blend_state = r600_delete_state;
-	rctx->context.set_blend_color = r600_set_blend_color;
-	rctx->context.set_clip_state = r600_set_clip_state;
-	rctx->context.set_constant_buffer = r600_set_constant_buffer;
-	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
-	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
-	rctx->context.create_fs_state = r600_create_fs_state;
-	rctx->context.bind_fs_state = r600_bind_fs_state;
-	rctx->context.delete_fs_state = r600_delete_state;
-	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
-	rctx->context.create_rasterizer_state = r600_create_rs_state;
-	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
-	rctx->context.delete_rasterizer_state = r600_delete_state;
-	rctx->context.create_sampler_state = r600_create_sampler_state;
-	rctx->context.bind_fragment_sampler_states = r600_bind_sampler_states;
-	rctx->context.bind_vertex_sampler_states = r600_bind_sampler_states;
-	rctx->context.delete_sampler_state = r600_delete_state;
-	rctx->context.create_sampler_view = r600_create_sampler_view;
-	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
-	rctx->context.set_fragment_sampler_views = r600_set_fragment_sampler_views;
-	rctx->context.set_vertex_sampler_views = r600_set_vertex_sampler_views;
-	rctx->context.set_scissor_state = r600_set_scissor_state;
-	rctx->context.set_viewport_state = r600_set_viewport_state;
-	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
-	rctx->context.create_vertex_elements_state = r600_create_vertex_elements_state;
-	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements_state;
-	rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements_state;
-	rctx->context.create_vs_state = r600_create_vs_state;
-	rctx->context.bind_vs_state = r600_bind_vs_state;
-	rctx->context.delete_vs_state = r600_delete_state;
-	rctx->context.set_stencil_ref = r600_set_stencil_ref;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;	
+	uint32_t color_control, target_mask, shader_mask;
+	int i;
+
+	target_mask = 0;
+	shader_mask = 0;
+	color_control = S_028808_PER_MRT_BLEND(1);
+
+	for (i = 0; i < nr_cbufs; i++) {
+		shader_mask |= 0xf << i;
+	}
+
+	if (pbs->logicop_enable) {
+		color_control |= (pbs->logicop_func) << 16;
+	} else
+		color_control |= (0xcc << 16);
+
+	for (i = 0; i < 8; i++) {
+		if (pbs->rt[i].blend_enable) {
+			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+		}
+		target_mask |= (pbs->rt[i].colormask << (4 * i));
+		
+	}
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
+	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
+	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+int r600_context_hw_states(struct r600_context *rctx)
+{
+	unsigned i;
+	int r;
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
+
+	/* free previous TODO determine what need to be updated, what
+	 * doesn't
+	 */
+	//radeon_state_decref(rctx->hw_states.config);
+	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
+	rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
+	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
+	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
+	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
+	rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
+	rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
+	for (i = 0; i < 8; i++) {
+		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
+	}
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		radeon_state_decref(rctx->hw_states.ps_resource[i]);
+		rctx->hw_states.ps_resource[i] = NULL;
+	}
+	rctx->hw_states.ps_nresource = 0;
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
+		rctx->hw_states.ps_sampler[i] = NULL;
+	}
+	rctx->hw_states.ps_nsampler = 0;
+
+	/* build new states */
+	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
+	rctx->hw_states.scissor = r600_scissor(rctx);
+	rctx->hw_states.dsa = r600_dsa(rctx);
+	rctx->hw_states.blend = r600_blend(rctx);
+	rctx->hw_states.viewport = r600_viewport(rctx);
+	for (i = 0; i < nr_cbufs; i++) {
+		rctx->hw_states.cb[i] = r600_cb(rctx, i);
+	}
+	rctx->hw_states.db = r600_db(rctx);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+
+	for (i = 0; i < rctx->ps_nsampler; i++) {
+		if (rctx->ps_sampler[i]) {
+			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
+							&rctx->ps_sampler[i]->state.sampler,
+							R600_PS_SAMPLER + i);
+		}
+	}
+	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
+	for (i = 0; i < rctx->ps_nsampler_view; i++) {
+		if (rctx->ps_sampler_view[i]) {
+			rctx->hw_states.ps_resource[i] = r600_resource(rctx,
+							&rctx->ps_sampler_view[i]->state.sampler_view,
+							R600_PS_RESOURCE + i);
+		}
+	}
+	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
+
+	/* bind states */
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
+	if (r)
+		return r;
+	for (i = 0; i < nr_cbufs; i++) {
+		r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
+		if (r)
+			return r;
+	}
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
+	if (r)
+		return r;
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		if (rctx->hw_states.ps_resource[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
+			if (r)
+				return r;
+		}
+	}
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		if (rctx->hw_states.ps_sampler[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
+			if (r)
+				return r;
+		}
+	}
+	return 0;
 }
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
new file mode 100644
index 0000000000..8271ad19fb
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef R600_STATE_INLINES_H
+#define R600_STATE_INLINES_H
+
+#include "util/u_format.h"
+#include "r600d.h"
+
+static INLINE uint32_t r600_translate_blend_function(int blend_func)
+{
+	switch (blend_func) {
+	case PIPE_BLEND_ADD:
+		return V_028804_COMB_DST_PLUS_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return V_028804_COMB_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return V_028804_COMB_DST_MINUS_SRC;
+	case PIPE_BLEND_MIN:
+		return V_028804_COMB_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return V_028804_COMB_MAX_DST_SRC;
+	default:
+		R600_ERR("Unknown blend function %d\n", blend_func);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
+{
+	switch (blend_fact) {
+	case PIPE_BLENDFACTOR_ONE:
+		return V_028804_BLEND_ONE;
+	case PIPE_BLENDFACTOR_SRC_COLOR:
+		return V_028804_BLEND_SRC_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return V_028804_BLEND_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_DST_ALPHA:
+		return V_028804_BLEND_DST_ALPHA;
+	case PIPE_BLENDFACTOR_DST_COLOR:
+		return V_028804_BLEND_DST_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return V_028804_BLEND_SRC_ALPHA_SATURATE;
+	case PIPE_BLENDFACTOR_CONST_COLOR:
+		return V_028804_BLEND_CONST_COLOR;
+	case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return V_028804_BLEND_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_ZERO:
+		return V_028804_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return V_028804_BLEND_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return V_028804_BLEND_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return V_028804_BLEND_INV_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return V_028804_BLEND_INV_SRC1_ALPHA;
+	default:
+		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static INLINE uint32_t r600_translate_stencil_op(int s_op)
+{
+	switch (s_op) {
+	case PIPE_STENCIL_OP_KEEP:
+		return V_028800_STENCIL_KEEP;
+	case PIPE_STENCIL_OP_ZERO:
+		return V_028800_STENCIL_ZERO;
+	case PIPE_STENCIL_OP_REPLACE:
+		return V_028800_STENCIL_REPLACE;
+	case PIPE_STENCIL_OP_INCR:
+		return V_028800_STENCIL_INCR;
+	case PIPE_STENCIL_OP_DECR:
+		return V_028800_STENCIL_DECR;
+	case PIPE_STENCIL_OP_INCR_WRAP:
+		return V_028800_STENCIL_INVERT;
+	case PIPE_STENCIL_OP_DECR_WRAP:
+		return V_028800_STENCIL_DECR_WRAP;
+	case PIPE_STENCIL_OP_INVERT:
+		return V_028800_STENCIL_INVERT;
+	default:
+		R600_ERR("Unknown stencil op %d", s_op);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+/* translates straight */
+static INLINE uint32_t r600_translate_ds_func(int func)
+{
+	return func;
+}
+
+static uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028010_DEPTH_16;
+	case PIPE_FORMAT_Z24X8_UNORM:
+		return V_028010_DEPTH_X8_24;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028010_DEPTH_8_24;
+	default:
+		return ~0;
+	}
+}
+
+static uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_SWAP_STD;
+
+		/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_SWAP_STD_REV;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_SWAP_ALT;
+		/* 32-bit buffers. */
+
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return V_0280A0_SWAP_STD_REV;
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_0280A0_SWAP_ALT_REV;
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+		//        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+		return V_0280A0_SWAP_STD_REV;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_SWAP_STD_REV;
+
+		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		//		return V_0280A0_COLOR_16_16_16_16;
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		//		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+
+		/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		//		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+		return 0;
+	default:
+		R600_ERR("unsupported colorswap format %d\n", format);
+		return ~0;
+	}
+	return ~0;
+}
+
+static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_COLOR_8;
+
+		/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_COLOR_5_6_5;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_COLOR_1_5_5_5;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_COLOR_4_4_4_4;
+
+		/* 32-bit buffers. */
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_0280A0_COLOR_8_8_8_8;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_COLOR_10_10_10_2;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_0280A0_COLOR_24_8;
+
+		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		return V_0280A0_COLOR_16_16_16_16;
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+	case PIPE_FORMAT_R32G32_FLOAT:
+		return V_0280A0_COLOR_32_32_FLOAT;
+
+		/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32_FLOAT:
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+
+		/* YUV buffers. */
+	case PIPE_FORMAT_UYVY:
+	case PIPE_FORMAT_YUYV:
+	default:
+		R600_ERR("unsupported color format %d\n", format);
+		return ~0; /* Unsupported. */
+	}
+}
+
+static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0;
+}
+
+static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0 &&
+		r600_translate_colorswap(format) != ~0;
+}
+
+static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
+{
+	return r600_translate_dbformat(format) != ~0;
+}
+
+static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0;
+}
+
+#endif
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 903cfad80a..1bce911306 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -31,15 +31,18 @@
 #include <util/u_memory.h>
 #include "state_tracker/drm_driver.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
+#include "r600_context.h"
+#include "r600_resource.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
-unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face)
+static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
+					unsigned level, unsigned zslice,
+					unsigned face)
 {
 	unsigned long offset = rtex->offset[level];
 
-	switch (rtex->b.b.target) {
+	switch (rtex->resource.base.b.target) {
 	case PIPE_TEXTURE_3D:
 		assert(face == 0);
 		return offset + zslice * rtex->layer_size[level];
@@ -52,67 +55,68 @@ unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
 	}
 }
 
-static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_texture *rtex)
+static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
 {
-	struct pipe_resource *ptex = &rtex->b.b;
-	unsigned long w, h, stride, size, layer_size, i, offset;
+	struct pipe_resource *ptex = &rtex->resource.base.b;
+	unsigned long w, h, pitch, size, layer_size, i, offset;
 
+	rtex->bpt = util_format_get_blocksize(ptex->format);
 	for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 		w = u_minify(ptex->width0, i);
 		h = u_minify(ptex->height0, i);
-		stride = align(util_format_get_stride(ptex->format, w), 32);
-		layer_size = stride * h;
+		pitch = util_format_get_stride(ptex->format, align(w, 64));
+		layer_size = pitch * h;
 		if (ptex->target == PIPE_TEXTURE_CUBE)
 			size = layer_size * 6;
 		else
 			size = layer_size * u_minify(ptex->depth0, i);
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
-		rtex->pitch[i] = stride / util_format_get_blocksize(ptex->format);
-		rtex->stride[i] = stride;
-		offset += align(size, 32);
+		rtex->pitch[i] = pitch;
+		offset += size;
 	}
 	rtex->size = offset;
 }
 
 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
-					  const struct pipe_resource *templ)
+						const struct pipe_resource *templ)
 {
-	struct r600_texture *rtex = CALLOC_STRUCT(r600_texture);
+	struct r600_resource_texture *rtex;
+	struct r600_resource *resource;
 	struct r600_screen *rscreen = r600_screen(screen);
-	struct pipe_resource templ_buf;
 
+	rtex = CALLOC_STRUCT(r600_resource_texture);
 	if (!rtex) {
 		return NULL;
 	}
-	rtex->b.b = *templ;
-	rtex->b.vtbl = &r600_texture_vtbl;
-	pipe_reference_init(&rtex->b.b.reference, 1);
-	rtex->b.b.screen = screen;
+	resource = &rtex->resource;
+	resource->base.b = *templ;
+	resource->base.vtbl = &r600_texture_vtbl;
+	pipe_reference_init(&resource->base.b.reference, 1);
+	resource->base.b.screen = screen;
 	r600_setup_miptree(rscreen, rtex);
 
-	memset(&templ_buf, 0, sizeof(struct pipe_resource));
-	templ_buf.target = PIPE_BUFFER;
-	templ_buf.format = PIPE_FORMAT_R8_UNORM;
-	templ_buf.usage = templ->usage;
-	templ_buf.bind = templ->bind;
-	templ_buf.width0 = rtex->size;
-	templ_buf.height0 = 1;
-	templ_buf.depth0 = 1;
-
-	rtex->buffer = screen->resource_create(screen, &templ_buf);
-	if (!rtex->buffer) {
+	/* FIXME alignment 4096 enought ? too much ? */
+	resource->domain = r600_domain_from_usage(resource->base.b.bind);
+	resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
+	if (resource->bo == NULL) {
 		FREE(rtex);
 		return NULL;
 	}
-	return &rtex->b.b;
+
+	return &resource->base.b;
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
-	struct r600_texture *rtex = (struct r600_texture*)ptex;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+	struct r600_resource *resource = &rtex->resource;
+	struct r600_screen *rscreen = r600_screen(screen);
 
+	if (resource->bo) {
+		radeon_bo_decref(rscreen->rw, resource->bo);
+	}
 	FREE(rtex);
 }
 
@@ -121,7 +125,7 @@ static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 						unsigned face, unsigned level,
 						unsigned zslice, unsigned flags)
 {
-	struct r600_texture *rtex = (struct r600_texture*)texture;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 	struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
 	unsigned long offset;
 
@@ -149,71 +153,115 @@ static void r600_tex_surface_destroy(struct pipe_surface *surface)
 }
 
 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
-					       const struct pipe_resource *base,
+					       const struct pipe_resource *templ,
 					       struct winsys_handle *whandle)
 {
-	struct pipe_resource *buffer;
-	struct r600_texture *rtex;
+	struct radeon *rw = (struct radeon*)screen->winsys;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *resource;
+	struct radeon_bo *bo = NULL;
 
-	buffer = r600_buffer_from_handle(screen, whandle);
-	if (buffer == NULL) {
+	bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
+	if (bo == NULL) {
 		return NULL;
 	}
 
 	/* Support only 2D textures without mipmaps */
-	if (base->target != PIPE_TEXTURE_2D || base->depth0 != 1 || base->last_level != 0)
+	if (templ->target != PIPE_TEXTURE_2D || templ->depth0 != 1 || templ->last_level != 0)
 		return NULL;
 
-	rtex = CALLOC_STRUCT(r600_texture);
+	rtex = CALLOC_STRUCT(r600_resource_texture);
 	if (rtex == NULL)
 		return NULL;
 
-	/* one ref already taken */
-	rtex->buffer = buffer;
-
-	rtex->b.b = *base;
-	rtex->b.vtbl = &r600_texture_vtbl;
-	pipe_reference_init(&rtex->b.b.reference, 1);
-	rtex->b.b.screen = screen;
-	rtex->stride_override = whandle->stride;
-	rtex->pitch[0] = whandle->stride / util_format_get_blocksize(base->format);
-	rtex->stride[0] = whandle->stride;
+	resource = &rtex->resource;
+	resource->base.b = *templ;
+	resource->base.vtbl = &r600_texture_vtbl;
+	pipe_reference_init(&resource->base.b.reference, 1);
+	resource->base.b.screen = screen;
+	resource->bo = bo;
+	rtex->pitch_override = whandle->stride;
+	rtex->bpt = util_format_get_blocksize(templ->format);
+	rtex->pitch[0] = whandle->stride;
 	rtex->offset[0] = 0;
-	rtex->size = align(rtex->stride[0] * base->height0, 32);
+	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 
-	return &rtex->b.b;
+	return &resource->base.b;
 }
 
-static boolean r600_texture_get_handle(struct pipe_screen* screen,
-				       struct pipe_resource *texture,
-				       struct winsys_handle *whandle)
+static unsigned int r600_texture_is_referenced(struct pipe_context *context,
+						struct pipe_resource *texture,
+						unsigned face, unsigned level)
 {
-	struct r600_screen *rscreen = r600_screen(screen);
-	struct r600_texture* rtex = (struct r600_texture*)texture;
+	/* FIXME */
+	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
+}
 
-	if (!rtex) {
-		return FALSE;
-	}
+struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
+						struct pipe_resource *texture,
+						struct pipe_subresource sr,
+						unsigned usage,
+						const struct pipe_box *box)
+{
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct r600_transfer *trans;
 
-	whandle->stride = rtex->stride[0];
+	trans = CALLOC_STRUCT(r600_transfer);
+	if (trans == NULL)
+		return NULL;
+	pipe_resource_reference(&trans->transfer.resource, texture);
+	trans->transfer.sr = sr;
+	trans->transfer.usage = usage;
+	trans->transfer.box = *box;
+	trans->transfer.stride = rtex->pitch[sr.level];
+	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
+	return &trans->transfer;
+}
 
-	r600_buffer_get_handle(rscreen->rw, rtex->buffer, whandle);
+void r600_texture_transfer_destroy(struct pipe_context *ctx,
+				   struct pipe_transfer *trans)
+{
+	pipe_resource_reference(&trans->resource, NULL);
+	FREE(trans);
+}
 
-	return TRUE;
+void* r600_texture_transfer_map(struct pipe_context *ctx,
+				struct pipe_transfer* transfer)
+{
+	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+	struct r600_resource *resource;
+	enum pipe_format format = transfer->resource->format;
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	char *map;
+
+	r600_flush(ctx, 0, NULL);
+
+	resource = (struct r600_resource *)transfer->resource;
+	if (radeon_bo_map(rscreen->rw, resource->bo)) {
+		return NULL;
+	}
+	radeon_bo_wait(rscreen->rw, resource->bo);
+
+	map = resource->bo->data;
+
+	return map + rtransfer->offset +
+		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
+		transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 }
 
-static unsigned int r600_texture_is_referenced(struct pipe_context *context,
-						struct pipe_resource *texture,
-						unsigned face, unsigned level)
+void r600_texture_transfer_unmap(struct pipe_context *ctx,
+				 struct pipe_transfer* transfer)
 {
-	struct r600_texture *rtex = (struct r600_texture*)texture;
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_resource *resource;
 
-	return r600_buffer_is_referenced_by_cs(context, rtex->buffer, face, level);
+	resource = (struct r600_resource *)transfer->resource;
+	radeon_bo_unmap(rscreen->rw, resource->bo);
 }
 
 struct u_resource_vtbl r600_texture_vtbl =
 {
-	r600_texture_get_handle,	/* get_handle */
+	u_default_resource_get_handle,	/* get_handle */
 	r600_texture_destroy,		/* resource_destroy */
 	r600_texture_is_referenced,	/* is_resource_referenced */
 	r600_texture_get_transfer,	/* get_transfer */
diff --git a/src/gallium/drivers/r600/r600_texture.h b/src/gallium/drivers/r600/r600_texture.h
deleted file mode 100644
index 9bc08d6b04..0000000000
--- a/src/gallium/drivers/r600/r600_texture.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_TEXTURE_H
-#define R600_TEXTURE_H
-
-#include <pipe/p_state.h>
-
-struct r600_texture {
-	struct u_resource		b;
-	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride_override;
-	unsigned long			size;
-	struct pipe_resource		*buffer;
-};
-
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
-					  const struct pipe_resource *templ);
-unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face);
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
-					       const struct pipe_resource *base,
-					       struct winsys_handle *whandle);
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-
-/* This should be implemented by winsys. */
-boolean r600_buffer_get_handle(struct radeon *rw,
-			       struct pipe_resource *buf,
-			       struct winsys_handle *whandle);
-
-
-#endif
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 44834984c6..fb71b1e5d1 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -26,6 +26,8 @@
 #ifndef R600D_H
 #define R600D_H
 
+#define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
+
 #define PKT3_NOP                               0x10
 #define PKT3_INDIRECT_BUFFER_END               0x17
 #define PKT3_SET_PREDICATION                   0x20
@@ -207,12 +209,24 @@
 #define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
 #define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
 #define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define     V_0280A0_NUMBER_UNORM                      0x00000000
+#define     V_0280A0_NUMBER_SNORM                      0x00000001
+#define     V_0280A0_NUMBER_USCALED                    0x00000002
+#define     V_0280A0_NUMBER_SSCALED                    0x00000003
+#define     V_0280A0_NUMBER_UINT                       0x00000004
+#define     V_0280A0_NUMBER_SINT                       0x00000005
+#define     V_0280A0_NUMBER_SRGB                       0x00000006
+#define     V_0280A0_NUMBER_FLOAT                      0x00000007
 #define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
 #define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
 #define   C_0280A0_READ_SIZE                           0xFFFF7FFF
 #define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
 #define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
 #define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define     V_0280A0_SWAP_STD                          0x00000000
+#define     V_0280A0_SWAP_ALT                          0x00000001
+#define     V_0280A0_SWAP_STD_REV                      0x00000002
+#define     V_0280A0_SWAP_ALT_REV                      0x00000003
 #define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
 #define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
 #define   C_0280A0_TILE_MODE                           0xFFF3FFFF
@@ -247,6 +261,16 @@
 #define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
 #define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
 #define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
 #define R_028800_DB_DEPTH_CONTROL                    0x028800
 #define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
 #define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
@@ -266,9 +290,25 @@
 #define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
 #define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
 #define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define     V_028800_STENCILFUNC_NEVER                 0x00000000
+#define     V_028800_STENCILFUNC_LESS                  0x00000001
+#define     V_028800_STENCILFUNC_EQUAL                 0x00000002
+#define     V_028800_STENCILFUNC_LEQUAL                0x00000003
+#define     V_028800_STENCILFUNC_GREATER               0x00000004
+#define     V_028800_STENCILFUNC_NOTEQUAL              0x00000005
+#define     V_028800_STENCILFUNC_GEQUAL                0x00000006
+#define     V_028800_STENCILFUNC_ALWAYS                0x00000007
 #define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
 #define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
 #define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define     V_028800_STENCIL_KEEP                      0x00000000
+#define     V_028800_STENCIL_ZERO                      0x00000001
+#define     V_028800_STENCIL_REPLACE                   0x00000002
+#define     V_028800_STENCIL_INCR                      0x00000003
+#define     V_028800_STENCIL_DECR                      0x00000004
+#define     V_028800_STENCIL_INVERT                    0x00000005
+#define     V_028800_STENCIL_INCR_WRAP                 0x00000006
+#define     V_028800_STENCIL_DECR_WRAP                 0x00000007
 #define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
 #define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
 #define   C_028800_STENCILZPASS                        0xFFFE3FFF
@@ -287,6 +327,31 @@
 #define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
 #define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
 #define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
 #define R_028010_DB_DEPTH_INFO                       0x028010
 #define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
 #define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
@@ -314,6 +379,117 @@
 #define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
 #define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
 #define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define   S_028430_STENCILREF(x)                       (((x) & 0xFF) << 0)
+#define   G_028430_STENCILREF(x)                       (((x) >> 0) & 0xFF)
+#define   C_028430_STENCILREF                          0xFFFFFF00
+#define   S_028430_STENCILMASK(x)                      (((x) & 0xFF) << 8)
+#define   G_028430_STENCILMASK(x)                      (((x) >> 8) & 0xFF)
+#define   C_028430_STENCILMASK                         0xFFFF00FF
+#define   S_028430_STENCILWRITEMASK(x)                 (((x) & 0xFF) << 16)
+#define   G_028430_STENCILWRITEMASK(x)                 (((x) >> 16) & 0xFF)
+#define   C_028430_STENCILWRITEMASK                    0xFF00FFFF
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define   S_028434_STENCILREF_BF(x)                    (((x) & 0xFF) << 0)
+#define   G_028434_STENCILREF_BF(x)                    (((x) >> 0) & 0xFF)
+#define   C_028434_STENCILREF_BF                       0xFFFFFF00
+#define   S_028434_STENCILMASK_BF(x)                   (((x) & 0xFF) << 8)
+#define   G_028434_STENCILMASK_BF(x)                   (((x) >> 8) & 0xFF)
+#define   C_028434_STENCILMASK_BF                      0xFFFF00FF
+#define   S_028434_STENCILWRITEMASK_BF(x)              (((x) & 0xFF) << 16)
+#define   G_028434_STENCILWRITEMASK_BF(x)              (((x) >> 16) & 0xFF)
+#define   C_028434_STENCILWRITEMASK_BF                 0xFF00FFFF
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define   S_028804_COLOR_SRCBLEND(x)                   (((x) & 0x1F) << 0)
+#define   G_028804_COLOR_SRCBLEND(x)                   (((x) >> 0) & 0x1F)
+#define   C_028804_COLOR_SRCBLEND                      0xFFFFFFE0
+#define     V_028804_BLEND_ZERO                        0x00000000
+#define     V_028804_BLEND_ONE                         0x00000001
+#define     V_028804_BLEND_SRC_COLOR                   0x00000002
+#define     V_028804_BLEND_ONE_MINUS_SRC_COLOR         0x00000003
+#define     V_028804_BLEND_SRC_ALPHA                   0x00000004
+#define     V_028804_BLEND_ONE_MINUS_SRC_ALPHA         0x00000005
+#define     V_028804_BLEND_DST_ALPHA                   0x00000006
+#define     V_028804_BLEND_ONE_MINUS_DST_ALPHA         0x00000007
+#define     V_028804_BLEND_DST_COLOR                   0x00000008
+#define     V_028804_BLEND_ONE_MINUS_DST_COLOR         0x00000009
+#define     V_028804_BLEND_SRC_ALPHA_SATURATE          0x0000000A
+#define     V_028804_BLEND_BOTH_SRC_ALPHA              0x0000000B
+#define     V_028804_BLEND_BOTH_INV_SRC_ALPHA          0x0000000C
+#define     V_028804_BLEND_CONST_COLOR                 0x0000000D
+#define     V_028804_BLEND_ONE_MINUS_CONST_COLOR       0x0000000E
+#define     V_028804_BLEND_SRC1_COLOR                  0x0000000F
+#define     V_028804_BLEND_INV_SRC1_COLOR              0x00000010
+#define     V_028804_BLEND_SRC1_ALPHA                  0x00000011
+#define     V_028804_BLEND_INV_SRC1_ALPHA              0x00000012
+#define     V_028804_BLEND_CONST_ALPHA                 0x00000013
+#define     V_028804_BLEND_ONE_MINUS_CONST_ALPHA       0x00000014
+#define   S_028804_COLOR_COMB_FCN(x)                   (((x) & 0x7) << 5)
+#define   G_028804_COLOR_COMB_FCN(x)                   (((x) >> 5) & 0x7)
+#define   C_028804_COLOR_COMB_FCN                      0xFFFFFF1F
+#define     V_028804_COMB_DST_PLUS_SRC                 0x00000000
+#define     V_028804_COMB_SRC_MINUS_DST                0x00000001
+#define     V_028804_COMB_MIN_DST_SRC                  0x00000002
+#define     V_028804_COMB_MAX_DST_SRC                  0x00000003
+#define     V_028804_COMB_DST_MINUS_SRC                0x00000004
+#define   S_028804_COLOR_DESTBLEND(x)                  (((x) & 0x1F) << 8)
+#define   G_028804_COLOR_DESTBLEND(x)                  (((x) >> 8) & 0x1F)
+#define   C_028804_COLOR_DESTBLEND                     0xFFFFE0FF
+#define   S_028804_OPACITY_WEIGHT(x)                   (((x) & 0x1) << 13)
+#define   G_028804_OPACITY_WEIGHT(x)                   (((x) >> 13) & 0x1)
+#define   C_028804_OPACITY_WEIGHT                      0xFFFFDFFF
+#define   S_028804_ALPHA_SRCBLEND(x)                   (((x) & 0x1F) << 16)
+#define   G_028804_ALPHA_SRCBLEND(x)                   (((x) >> 16) & 0x1F)
+#define   C_028804_ALPHA_SRCBLEND                      0xFFE0FFFF
+#define   S_028804_ALPHA_COMB_FCN(x)                   (((x) & 0x7) << 21)
+#define   G_028804_ALPHA_COMB_FCN(x)                   (((x) >> 21) & 0x7)
+#define   C_028804_ALPHA_COMB_FCN                      0xFF1FFFFF
+#define   S_028804_ALPHA_DESTBLEND(x)                  (((x) & 0x1F) << 24)
+#define   G_028804_ALPHA_DESTBLEND(x)                  (((x) >> 24) & 0x1F)
+#define   C_028804_ALPHA_DESTBLEND                     0xE0FFFFFF
+#define   S_028804_SEPARATE_ALPHA_BLEND(x)             (((x) & 0x1) << 29)
+#define   G_028804_SEPARATE_ALPHA_BLEND(x)             (((x) >> 29) & 0x1)
+#define   C_028804_SEPARATE_ALPHA_BLEND                0xDFFFFFFF
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define   S_028814_CULL_FRONT(x)                       (((x) & 0x1) << 0)
+#define   G_028814_CULL_FRONT(x)                       (((x) >> 0) & 0x1)
+#define   C_028814_CULL_FRONT                          0xFFFFFFFE
+#define   S_028814_CULL_BACK(x)                        (((x) & 0x1) << 1)
+#define   G_028814_CULL_BACK(x)                        (((x) >> 1) & 0x1)
+#define   C_028814_CULL_BACK                           0xFFFFFFFD
+#define   S_028814_FACE(x)                             (((x) & 0x1) << 2)
+#define   G_028814_FACE(x)                             (((x) >> 2) & 0x1)
+#define   C_028814_FACE                                0xFFFFFFFB
+#define   S_028814_POLY_MODE(x)                        (((x) & 0x3) << 3)
+#define   G_028814_POLY_MODE(x)                        (((x) >> 3) & 0x3)
+#define   C_028814_POLY_MODE                           0xFFFFFFE7
+#define   S_028814_POLYMODE_FRONT_PTYPE(x)             (((x) & 0x7) << 5)
+#define   G_028814_POLYMODE_FRONT_PTYPE(x)             (((x) >> 5) & 0x7)
+#define   C_028814_POLYMODE_FRONT_PTYPE                0xFFFFFF1F
+#define   S_028814_POLYMODE_BACK_PTYPE(x)              (((x) & 0x7) << 8)
+#define   G_028814_POLYMODE_BACK_PTYPE(x)              (((x) >> 8) & 0x7)
+#define   C_028814_POLYMODE_BACK_PTYPE                 0xFFFFF8FF
+#define   S_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) & 0x1) << 11)
+#define   G_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) >> 11) & 0x1)
+#define   C_028814_POLY_OFFSET_FRONT_ENABLE            0xFFFFF7FF
+#define   S_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) & 0x1) << 12)
+#define   G_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) >> 12) & 0x1)
+#define   C_028814_POLY_OFFSET_BACK_ENABLE             0xFFFFEFFF
+#define   S_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) & 0x1) << 13)
+#define   G_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) >> 13) & 0x1)
+#define   C_028814_POLY_OFFSET_PARA_ENABLE             0xFFFFDFFF
+#define   S_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) & 0x1) << 16)
+#define   G_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) >> 16) & 0x1)
+#define   C_028814_VTX_WINDOW_OFFSET_ENABLE            0xFFFEFFFF
+#define   S_028814_PROVOKING_VTX_LAST(x)               (((x) & 0x1) << 19)
+#define   G_028814_PROVOKING_VTX_LAST(x)               (((x) >> 19) & 0x1)
+#define   C_028814_PROVOKING_VTX_LAST                  0xFFF7FFFF
+#define   S_028814_PERSP_CORR_DIS(x)                   (((x) & 0x1) << 20)
+#define   G_028814_PERSP_CORR_DIS(x)                   (((x) >> 20) & 0x1)
+#define   C_028814_PERSP_CORR_DIS                      0xFFEFFFFF
+#define   S_028814_MULTI_PRIM_IB_ENA(x)                (((x) & 0x1) << 21)
+#define   G_028814_MULTI_PRIM_IB_ENA(x)                (((x) >> 21) & 0x1)
+#define   C_028814_MULTI_PRIM_IB_ENA                   0xFFDFFFFF
 #define R_028000_DB_DEPTH_SIZE                       0x028000
 #define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
 #define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
@@ -400,6 +576,29 @@
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E00_SCALE                               0x00000000
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E04_OFFSET                              0x00000000
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E08_SCALE                               0x00000000
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E0C_OFFSET                              0x00000000
 #define R_028A40_VGT_GS_MODE                         0x028A40
 #define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
 #define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
@@ -574,6 +773,132 @@
 #define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
 #define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
 #define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define     V_038000_SQ_TEX_DIM_1D                     0x00000000
+#define     V_038000_SQ_TEX_DIM_2D                     0x00000001
+#define     V_038000_SQ_TEX_DIM_3D                     0x00000002
+#define     V_038000_SQ_TEX_DIM_CUBEMAP                0x00000003
+#define     V_038000_SQ_TEX_DIM_1D_ARRAY               0x00000004
+#define     V_038000_SQ_TEX_DIM_2D_ARRAY               0x00000005
+#define     V_038000_SQ_TEX_DIM_2D_MSAA                0x00000006
+#define     V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define     V_038010_SQ_FORMAT_COMP_UNSIGNED           0x00000000
+#define     V_038010_SQ_FORMAT_COMP_SIGNED             0x00000001
+#define     V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED    0x00000002
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define     V_038010_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_038010_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_038010_SQ_NUM_FORMAT_SCALED              0x00000002
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define     V_038010_SFR_MODE_ZERO_CLAMP_MINUS_ONE     0x00000000
+#define     V_038010_SFR_MODE_NO_ZERO                  0x00000001
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define     V_038010_SQ_SEL_X                          0x00000000
+#define     V_038010_SQ_SEL_Y                          0x00000001
+#define     V_038010_SQ_SEL_Z                          0x00000002
+#define     V_038010_SQ_SEL_W                          0x00000003
+#define     V_038010_SQ_SEL_0                          0x00000004
+#define     V_038010_SQ_SEL_1                          0x00000005
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define     V_038010_SQ_TEX_VTX_INVALID_TEXTURE        0x00000000
+#define     V_038010_SQ_TEX_VTX_INVALID_BUFFER         0x00000001
+#define     V_038010_SQ_TEX_VTX_VALID_TEXTURE          0x00000002
+#define     V_038010_SQ_TEX_VTX_VALID_BUFFER           0x00000003
 #define R_038008_SQ_VTX_CONSTANT_WORD2_0             0x038008
 #define   S_038008_BASE_ADDRESS_HI(x)                  (((x) & 0xFF) << 0)
 #define   G_038008_BASE_ADDRESS_HI(x)                  (((x) >> 0) & 0xFF)
@@ -633,6 +958,113 @@
 #define   S_038008_ENDIAN_SWAP(x)                      (((x) & 0x3) << 30)
 #define   G_038008_ENDIAN_SWAP(x)                      (((x) >> 30) & 0x3)
 #define   C_038008_ENDIAN_SWAP                         0x3FFFFFFF
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define     V_03C000_SQ_TEX_WRAP                       0x00000000
+#define     V_03C000_SQ_TEX_MIRROR                     0x00000001
+#define     V_03C000_SQ_TEX_CLAMP_LAST_TEXEL           0x00000002
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL     0x00000003
+#define     V_03C000_SQ_TEX_CLAMP_HALF_BORDER          0x00000004
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER    0x00000005
+#define     V_03C000_SQ_TEX_CLAMP_BORDER               0x00000006
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_BORDER         0x00000007
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define     V_03C000_SQ_TEX_XY_FILTER_POINT            0x00000000
+#define     V_03C000_SQ_TEX_XY_FILTER_BILINEAR         0x00000001
+#define     V_03C000_SQ_TEX_XY_FILTER_BICUBIC          0x00000002
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define     V_03C000_SQ_TEX_Z_FILTER_NONE              0x00000000
+#define     V_03C000_SQ_TEX_Z_FILTER_POINT             0x00000001
+#define     V_03C000_SQ_TEX_Z_FILTER_LINEAR            0x00000002
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define     V_03C000_SQ_TEX_BORDER_COLOR_TRANS_BLACK   0x00000000
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK  0x00000001
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE  0x00000002
+#define     V_03C000_SQ_TEX_BORDER_COLOR_REGISTER      0x00000003
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER        0x00000000
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESS         0x00000001
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL        0x00000002
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL    0x00000003
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER      0x00000004
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL     0x00000005
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x00000006
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS       0x00000007
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define     V_03C000_SQ_TEX_CHROMA_KEY_DISABLE         0x00000000
+#define     V_03C000_SQ_TEX_CHROMA_KEY_KILL            0x00000001
+#define     V_03C000_SQ_TEX_CHROMA_KEY_BLEND           0x00000002
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
 #define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
 #define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
 #define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index 3532ba5b0c..1ebe20d6ab 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -25,7 +25,6 @@
 #include "util/u_memory.h"
 #include "r700_sq.h"
 #include <stdio.h>
-#include <errno.h>
 
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {