i965/gen7: Add support for rendering to depthbuffer mipmap levels > 0.

The same as 3e43adef95ee24dd218279d2de56939b90edcb4c but for Gen7.

This doesn't quite fix GL_ARB_depth_texture/fbo-clear-formats; there's
still a 1 pixel wide black line on the right edge of the smaller squares.

The results were entirely wrong before, and are at least close now.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

2 files changed, 18 insertions, 31 deletions

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 68a222eb3f..a180b678c1 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -86,6 +86,10 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
+      uint32_t tile_x, tile_y, offset;
+
+      offset = intel_region_tile_offsets(region, &tile_x, &tile_y);
+
       assert(region->tiling == I915_TILING_Y);
 
       BEGIN_BATCH(7);
@@ -98,10 +102,10 @@ static void emit_depthbuffer(struct brw_context *brw)
 		(BRW_SURFACE_2D << 29));
       OUT_RELOC(region->buffer,
 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		0);
+		offset);
       OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
       OUT_BATCH(0);
-      OUT_BATCH(0);
+      OUT_BATCH(tile_x | (tile_y << 16));
       OUT_BATCH(0);
       ADVANCE_BATCH();
    }
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 361db2fead..d4eb550c75 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -233,6 +233,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_region *region = irb->region;
    struct gen7_surface_state *surf;
+   uint32_t tile_x, tile_y;
 
    surf = brw_state_batch(brw, sizeof(*surf), 32,
 			  &brw->wm.surf_offset[unit]);
@@ -271,37 +272,19 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    }
 
    surf->ss0.surface_type = BRW_SURFACE_2D;
-   if (region->tiling == I915_TILING_NONE) {
-      surf->ss1.base_addr = (region->draw_x +
-			    region->draw_y * region->pitch) * region->cpp;
-   } else {
-      uint32_t tile_base, tile_x, tile_y;
-      uint32_t pitch = region->pitch * region->cpp;
-
-      if (region->tiling == I915_TILING_X) {
-	 tile_x = region->draw_x % (512 / region->cpp);
-	 tile_y = region->draw_y % 8;
-	 tile_base = ((region->draw_y / 8) * (8 * pitch));
-	 tile_base += (region->draw_x - tile_x) / (512 / region->cpp) * 4096;
-      } else {
-	 /* Y */
-	 tile_x = region->draw_x % (128 / region->cpp);
-	 tile_y = region->draw_y % 32;
-	 tile_base = ((region->draw_y / 32) * (32 * pitch));
-	 tile_base += (region->draw_x - tile_x) / (128 / region->cpp) * 4096;
-      }
-      assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
-      assert(tile_x % 4 == 0);
-      assert(tile_y % 2 == 0);
-      /* Note that the low bits of these fields are missing, so
-       * there's the possibility of getting in trouble.
-       */
-      surf->ss1.base_addr = tile_base;
-      surf->ss5.x_offset = tile_x / 4;
-      surf->ss5.y_offset = tile_y / 2;
-   }
+   /* reloc */
+   surf->ss1.base_addr = intel_region_tile_offsets(region, &tile_x, &tile_y);
    surf->ss1.base_addr += region->buffer->offset; /* reloc */
 
+   assert(brw->has_surface_tile_offset);
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   assert(tile_x % 4 == 0);
+   assert(tile_y % 2 == 0);
+   surf->ss5.x_offset = tile_x / 4;
+   surf->ss5.y_offset = tile_y / 2;
+
    surf->ss2.width = rb->Width - 1;
    surf->ss2.height = rb->Height - 1;
    gen7_set_surface_tiling(surf, region->tiling);