diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2008-09-12 09:25:34 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2008-09-12 09:29:00 +0800 |
| commit | 1ffbcddb6ff14befd5de43c52b7bb0f4d631328f (patch) | |
| tree | 0197ac0a04b2edb5f480f567dba7f8231985fa31 | |
| parent | 33cf8f5c061ad7b5e44c8db9595ae8538259a815 (diff) | |
i965: Add support for G41 chipset which is another 4 series.
(cherry picked from commit b2e083eba2668517e40bc94e3a19cd15824ce93c)
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 15b9ef4312..170efd060a 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -58,6 +58,7 @@ #define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 #define PCI_CHIP_G45_G 0x2E22 +#define PCI_CHIP_G41_G 0x2E32 #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -70,7 +71,8 @@ #define IS_GM45_GM(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ - devid == PCI_CHIP_G45_G) + devid == PCI_CHIP_G45_G || \ + devid == PCI_CHIP_G41_G) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 5fa9d95e11..fd2fe596de 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -178,6 +178,9 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_Q45_G: chipset = "Intel(R) Q45/Q43"; break; + case PCI_CHIP_G41_G: + chipset = "Intel(R) G41"; + break; default: chipset = "Unknown Intel Chipset"; break; |