diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-17 12:45:01 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:58:19 +0800 |
| commit | 8c31a4c3cf6655fe4db6befb4a7b029ada62aaf6 (patch) | |
| tree | 20be0a63523db22f80185462cafb9badc61b21b0 | |
| parent | b016a78b983295c112421c01d378fbe2862412d4 (diff) | |
i965: enable accumulator update in PS kernel too on sandybridge
Accumulator update flag must be set for implicit update on sandybridge.
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_emit.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_glsl.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 9be3bfbbfe..260a04c774 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1627,9 +1627,12 @@ static void spill_values( struct brw_wm_compile *c, void brw_wm_emit( struct brw_wm_compile *c ) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; GLuint insn; brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); + if (intel->gen >= 6) + brw_set_acc_write_control(p, 1); /* Check if any of the payload regs need to be spilled: */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index f60245377e..1cbd5d2b55 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -711,6 +711,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack)); + if (intel->gen >= 6) + brw_set_acc_write_control(p, 1); + for (i = 0; i < c->nr_fp_insns; i++) { const struct prog_instruction *inst = &c->prog_instructions[i]; int dst_flags; |