i965: Fix cube map layouts on Ironlake.

We were doubling up the offsets for the mipmap levels for CPU access.
Instead of reimplementing i945_miptree_layout_2d with 6 cube images
separated by qpitch, share that function and provide the level offsets
later.

Fixes piglit cubemap and fbo-cubemap.
(cherry picked from commit 7d8f0fc28239c8023d2d44cbd4c979aa86c31873
Conflict due to mt->pitch still being here resolved -- i945 layout
should set it.)

4 files changed, 24 insertions, 70 deletions

diff --git a/src/mesa/drivers/dri/i915/i915_tex_layout.c b/src/mesa/drivers/dri/i915/i915_tex_layout.c
index fe3908f580..f4fdd5d5e2 100644
--- a/src/mesa/drivers/dri/i915/i915_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/i915_tex_layout.c
@@ -484,7 +484,7 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
    case GL_TEXTURE_1D:
    case GL_TEXTURE_2D:
    case GL_TEXTURE_RECTANGLE_ARB:
-      i945_miptree_layout_2d(intel, mt, tiling);
+      i945_miptree_layout_2d(intel, mt, tiling, 1);
       break;
    default:
       _mesa_problem(NULL, "Unexpected tex target in i945_miptree_layout()");
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index cc1ecc2030..dcae307e64 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -49,76 +49,30 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
       if (intel->gen == 5) {
-          GLuint align_h = 2, align_w = 4;
+          GLuint align_h = 2;
           GLuint level;
-          GLuint x = 0;
-          GLuint y = 0;
-          GLuint width = mt->width0;
-          GLuint height = mt->height0;
           GLuint qpitch = 0;
-          GLuint y_pitch = 0;
+	  int h0, h1, q;
 
-          mt->pitch = mt->width0;
-          intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-          y_pitch = ALIGN(height, align_h);
+	  /* On Ironlake, cube maps are finally represented as just a series
+	   * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
+	   * by a pitch of qpitch rows, where qpitch is defined by the equation
+	   * given in Volume 1 of the BSpec.
+	   */
+	  h0 = ALIGN(mt->height0, align_h);
+	  h1 = ALIGN(minify(h0), align_h);
+	  qpitch = (h0 + h1 + 11 * align_h);
+          if (mt->compressed)
+	     qpitch /= 4;
 
-          if (mt->compressed) {
-              mt->pitch = ALIGN(mt->width0, align_w);
-          }
-
-          if (mt->first_level != mt->last_level) {
-              GLuint mip1_width;
-
-              if (mt->compressed) {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + ALIGN(minify(minify(mt->width0)), align_w);
-              } else {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + minify(minify(mt->width0));
-              }
-
-              if (mip1_width > mt->pitch) {
-                  mt->pitch = mip1_width;
-              }
-          }
-
-          mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
-
-          if (mt->compressed) {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
-          } else {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h);
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
-          }
+	  i945_miptree_layout_2d(intel, mt, tiling, 6);
 
           for (level = mt->first_level; level <= mt->last_level; level++) {
-              GLuint img_height;
-              GLuint nr_images = 6;
-              GLuint q = 0;
-
-              intel_miptree_set_level_info(mt, level, nr_images, x, y, width, 
-                                           height, 1);
-
-              for (q = 0; q < nr_images; q++)
-                  intel_miptree_set_image_offset(mt, level, q,
-						 x, y + q * qpitch);
-
-              if (mt->compressed)
-                  img_height = MAX2(1, height/4);
-              else
-                  img_height = ALIGN(height, align_h);
-
-              if (level == mt->first_level + 1) {
-                  x += ALIGN(width, align_w);
-              }
-              else {
-                  y += img_height;
-              }
-
-              width  = minify(width);
-              height = minify(height);
+	     for (q = 0; q < 6; q++) {
+		intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
+	     }
           }
+	  mt->total_height = qpitch * 6;
 
           break;
       }
@@ -208,7 +162,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
    }
 
    default:
-      i945_miptree_layout_2d(intel, mt, tiling);
+      i945_miptree_layout_2d(intel, mt, tiling, 1);
       break;
    }
    DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.c b/src/mesa/drivers/dri/intel/intel_tex_layout.c
index 7d69ea4484..cdca8de00a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.c
@@ -63,9 +63,9 @@ void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *
     }
 }
 
-void i945_miptree_layout_2d( struct intel_context *intel,
-			     struct intel_mipmap_tree *mt,
-			     uint32_t tiling )
+void i945_miptree_layout_2d(struct intel_context *intel,
+			    struct intel_mipmap_tree *mt,
+			    uint32_t tiling, int nr_images)
 {
    GLuint align_h = 2, align_w = 4;
    GLuint level;
@@ -111,7 +111,7 @@ void i945_miptree_layout_2d( struct intel_context *intel,
    for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
       GLuint img_height;
 
-      intel_miptree_set_level_info(mt, level, 1, x, y, width, 
+      intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
 				   height, 1);
 
       if (mt->compressed)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_layout.h b/src/mesa/drivers/dri/intel/intel_tex_layout.h
index a9ac9e7eb4..1c8c53e545 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_layout.h
+++ b/src/mesa/drivers/dri/intel/intel_tex_layout.h
@@ -40,5 +40,5 @@ static INLINE GLuint minify( GLuint d )
 
 extern void i945_miptree_layout_2d(struct intel_context *intel,
 				   struct intel_mipmap_tree *mt,
-				   uint32_t tiling);
+				   uint32_t tiling, int nr_images);
 extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *);