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arch
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mips
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kernel
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traps.c
Age
Commit message (
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Author
Files
Lines
2010-07-05
MIPS: Return after handling coprocessor 2 exception
Jesper Nilsson
1
-1
/
+1
2010-05-21
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
Linus Torvalds
1
-1
/
+1
2010-05-21
MIPS: Use set_cpus_allowed_ptr
Julia Lawall
1
-1
/
+1
2010-05-20
mips,kgdb: kdb low level trap catch and stack trace
Jason Wessel
1
-0
/
+13
2010-04-30
MIPS: Use CKSEG1ADDR for uncached handler
Sebastian Andrzej Siewior
1
-6
/
+1
2010-04-30
MIPS: die() does not call die notifier chain
Yury Polyanskiy
1
-2
/
+7
2010-04-12
MIPS: Calculate proper ebase value for 64-bit kernels
David Daney
1
-1
/
+1
2010-02-27
MIPS: Deal with larger physical offsets
Florian Fainelli
1
-8
/
+13
2010-02-27
MIPS: Annotate set_except_vector with __init
Florian Fainelli
1
-1
/
+1
2010-02-10
MIPS: Fixup of the r4k timer
Wu Zhangjin
1
-0
/
+1
2010-01-28
MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs
David VomLehn
1
-2
/
+4
2009-12-17
MIPS: Cleanup signal code initialization
Ralf Baechle
1
-76
/
+0
2009-12-17
MIPS: Modularize COP2 handling
Ralf Baechle
1
-15
/
+45
2009-09-17
MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler
Ralf Baechle
1
-3
/
+2
2009-06-17
MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
David Daney
1
-4
/
+0
2009-06-17
MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
David Daney
1
-1
/
+1
2009-03-30
MIPS: Use BUG_ON() where possible.
Ralf Baechle
1
-2
/
+1
2009-03-23
MIPS: R2: Fix problem with code that incorrectly modifies ebase.
Chris Dearman
1
-5
/
+7
2009-01-30
MIPS: Read watch registers with interrupts disabled.
David Daney
1
-1
/
+7
2009-01-30
MIPS: R2: Fix broken installation of cache error handler.
Ralf Baechle
1
-2
/
+6
2009-01-11
MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.
David Daney
1
-0
/
+21
2008-10-30
MIPS: Switch FPU emulator trap to BREAK instruction.
Ralf Baechle
1
-0
/
+16
2008-10-30
MIPS: Consider value of c0_ebase when computing value of exception base.
David Daney
1
-4
/
+9
2008-10-11
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
David Daney
1
-5
/
+19
2008-10-03
[MIPS] SMTC: Fix holes in SMTC and FPU affinity support.
Kevin D. Kissell
1
-2
/
+4
2008-09-21
[MIPS] Fix potential latency problem due to non-atomic cpu_wait.
Atsushi Nemoto
1
-6
/
+16
2008-09-05
[MIPS] Fix WARNING: at kernel/smp.c:290
Thomas Bogendoerfer
1
-5
/
+7
2008-09-05
[MIPS] Fix data bus error recovery
Thomas Bogendoerfer
1
-2
/
+4
2008-07-30
[MIPS] kgdb: add arch support for the kernel's kgdb core
Jason Wessel
1
-0
/
+21
2008-07-15
[MIPS] Replace use of print_symbol with new %sP pointer format.
Ralf Baechle
1
-4
/
+4
2008-07-15
[MIPS] Remove board_watchpoint_handler
David Daney
1
-6
/
+0
2008-06-05
[MIPS] Fix check for valid stack pointer during backtrace
Thomas Bogendoerfer
1
-7
/
+9
2008-04-28
[MIPS] Fix handling of trap and breakpoint instructions
Ralf Baechle
1
-52
/
+37
2008-04-28
[MIPS] Add support for MIPS CMP platform.
Ralf Baechle
1
-12
/
+99
2008-04-28
[MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.
Chris Dearman
1
-1
/
+12
2008-03-12
[MIPS] Fix loads of section missmatches
Ralf Baechle
1
-3
/
+4
2008-03-12
[MIPS] Added missing cases for rdhwr emulation
Chris Dearman
1
-6
/
+25
2007-12-14
[MIPS] Ensure that ST0_FR is never set on a 32 bit kernel
Chris Dearman
1
-3
/
+3
2007-11-15
[MIPS] Fix shadow register support.
Ralf Baechle
1
-65
/
+3
2007-10-19
Use helpers to obtain task pid in printks (arch code)
Alexey Dobriyan
1
-1
/
+1
2007-10-18
[MIPS] time: Move R4000 clockevent device code to separate configurable file
Ralf Baechle
1
-0
/
+11
2007-10-17
[MIPS] SYNC emulation for MIPS I processors
Maciej W. Rozycki
1
-78
/
+86
2007-10-16
[MIPS] IP22: Fix warning.
Ralf Baechle
1
-6
/
+15
2007-10-11
[MIPS] Make facility to convert CPU types to strings generally available.
Ralf Baechle
1
-1
/
+2
2007-10-11
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Ralf Baechle
1
-13
/
+13
2007-10-11
[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
Ralf Baechle
1
-3
/
+3
2007-10-11
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
Ralf Baechle
1
-0
/
+6
2007-10-11
[MIPS] Kill useless volatile keyword
Ralf Baechle
1
-2
/
+2
2007-08-27
[MIPS] Maintain si_code field properly for FP exceptions
Thiemo Seufer
1
-3
/
+18
2007-08-27
[MIPS] SMTC: Fix duplicate status dumps on NMI
Thiemo Seufer
1
-9
/
+1
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