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2007-07-11Merge branch 'master' into cleanupdrm-ttm-cleanup-branchDave Airlie92-2425/+5491
Conflicts: libdrm/xf86drm.c linux-core/drm_bo.c linux-core/drm_fence.c
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet7-86/+215
2007-07-11Made drm_sg_alloc accessible from inside the DRM - drm_sg_alloc_ioctl is the ↵Arthur Huillet6-37/+61
ioctl wrapper
2007-07-09nouveau: Allocate mappable VRAM for notifiers..Ben Skeggs2-4/+1
2007-07-09nouveau: Don't be so strict on <NV50Ben Skeggs1-6/+6
2007-07-09nouveau: Avoid oopsBen Skeggs2-8/+21
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs23-277/+1156
Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-09nouveau: enable reporting for all PFIFO/PGRAPH irqsBen Skeggs1-23/+3
2007-07-09nouveau: rewrite gpu object codeBen Skeggs12-488/+844
Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-03Use idr_replace trick to eliminate struct drm_ctx_sarea_list.Kristian Høgsberg3-40/+8
2007-07-03Don't take dev->struct_mutex twice in drm_setsareactx.Kristian Høgsberg1-2/+0
2007-07-03One more spinlock initializer cleanup.Michel Dänzer1-1/+1
2007-07-03Simplification for previous commit.Michel Dänzer1-25/+9
Dave Airlie pointed out on IRC that idr_replace lets us know if the ID hasn't been allocated, so we don't need a special pointer value for allocated IDs that don't have valid information yet.
2007-07-03Restore pre-idr semantics for drawable information.Michel Dänzer1-18/+25
There's a difference between a drawable ID not having valid drawable information and not being allocated at all. Not making the distinction would break i915 DRM swap scheduling with older X servers that don't push drawable cliprect information to the DRM.
2007-07-02Fix must-check warnings and implement a few error paths.Kristian Høgsberg3-16/+43
2007-07-02Drop drm_drawable_list and add drm_drawable_info directly to the idr.Kristian Høgsberg2-24/+21
2007-06-29Avoid hitting BUG() for kernel-only fence objects.Thomas Hellstrom1-0/+6
2007-06-29Fence object reference / dereference cleanup.Thomas Hellstrom5-127/+134
Buffer object dereference cleanup. Add a struct drm_device member to fence objects: This can simplify code, particularly in drivers.
2007-06-29nouveau: small RAMFC cleanupsBen Skeggs2-21/+16
2007-06-28nouveau: Hack around possible Xv blit adaptor breakageBen Skeggs1-0/+13
2007-06-28nouveau/nv10: Fix earlier NV1x chipsBen Skeggs2-30/+34
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
2007-06-28nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bitBen Skeggs7-85/+106
2007-06-28nouveau: simplify PRAMIN accessBen Skeggs3-41/+27
2007-06-28nouveau: name some regsBen Skeggs3-16/+38
2007-06-28nouveau/nv50: skeletal backendBen Skeggs10-3/+264
2007-06-28nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)Ben Skeggs9-140/+315
For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaksBen Skeggs1-4/+5
2007-06-26More 64-bit padding.Thomas Hellstrom1-4/+7
2007-06-26Add support SiS based XGI chips to SiS DRM.Ian Romanick2-4/+6
2007-06-25nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303Ben Skeggs2-5/+494
2007-06-24nouveau: kill some dead codeBen Skeggs1-30/+11
2007-06-24nouveau: NV04/NV10/NV20 PGRAPH engtab functionsBen Skeggs6-46/+86
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup.
2007-06-24nouveau: NV3X PGRAPH engtab functionsBen Skeggs4-12/+74
2007-06-24nouveau: NV1X/2X/3X PFIFO engtab functionsBen Skeggs6-172/+176
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24nouveau: NV04 PFIFO engtab functionsBen Skeggs8-36/+144
2007-06-24nouveau: NV4X PGRAPH engtab functionsBen Skeggs4-70/+111
2007-06-24nouveau: NV4X PFIFO engtab functionsBen Skeggs7-76/+237
2007-06-24nouveau: split PFIFO/PGRAPH context creationBen Skeggs1-7/+31
2007-06-24nouveau: (mostly) hook up put_base againBen Skeggs2-11/+11
2007-06-24nouveau: prototype PFIFO/PGRAPH engtab APIBen Skeggs1-4/+14
2007-06-24nouveau: rename engtab functionsBen Skeggs2-70/+70
2007-06-22radeon: Acknowledge all interrupts we're interested in.Michel Dänzer1-2/+7
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-21r300: Synchronized the register defines file; documentation changes.Oliver McFadden1-3/+5
2007-06-21r300: Allow writes to R300_VAP_PVS_WAITIDLE.Oliver McFadden1-0/+1
2007-06-18r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1.Oliver McFadden1-1/+1
2007-06-18r300: Synchronized the register defines file again.Oliver McFadden1-2/+15
2007-06-18fix radeon setparam on 32/64 systems, harder.David Woodhouse1-1/+5
Commit 9b01bd5b284bbf519b726b39f1352023cb5e9e69 introduced a compat_ioctl handler for RADEON_SETPARAM, the sole purpose of which was to handle the fact that on i386, alignof(uint64_t)==4. Unfortunately, this handler was installed for _all_ 64-bit architectures, instead of only x86_64 and ia64. And thus it breaks 32-bit compatibility on every other arch, where 64-bit integers are aligned to 8 bytes in 32-bit mode just the same as in 64-bit mode. Arnd has a cunning plan to use 'compat_u64' with appropriate alignment attributes according to the 32-bit ABI, but for now let's just make the compat_radeon_cp_setparam routine entirely disappear on 64-bit machines whose 32-bit compat support isn't for i386. It would be a no-op with compat_u64 anyway. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2007-06-15i915: Fix handling of breadcrumb counter wraparounds.Michel Dänzer4-7/+12
2007-06-15Fix i915 sequence mask.Thomas Hellstrom1-1/+1
2007-06-15Indentation fixes.Thomas Hellstrom1-3/+3
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