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Diffstat (limited to 'linux/mga_state.c')
-rw-r--r--linux/mga_state.c634
1 files changed, 397 insertions, 237 deletions
diff --git a/linux/mga_state.c b/linux/mga_state.c
index 0a50aa4f..3134b785 100644
--- a/linux/mga_state.c
+++ b/linux/mga_state.c
@@ -40,15 +40,23 @@ static void mgaEmitClipRect( drm_mga_private_t *dev_priv,
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int *regs = sarea_priv->ContextState;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
/* This takes 10 dwords */
PRIMGETPTR( dev_priv );
/* Force reset of dwgctl (eliminates clip disable) */
+#if 1
PRIMOUTREG( MGAREG_DMAPAD, 0 );
- PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 );
- PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 );
+ PRIMOUTREG( MGAREG_DWGSYNC, 0 );
+ PRIMOUTREG( MGAREG_DWGSYNC, 0 );
PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
+#else
+ PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
+ PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000 );
+ PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
+ PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0x80000000 );
+#endif
PRIMOUTREG( MGAREG_DMAPAD, 0 );
PRIMOUTREG( MGAREG_CXBNDRY, ((box->x2)<<16)|(box->x1) );
@@ -63,6 +71,7 @@ static void mgaEmitContext(drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int *regs = sarea_priv->ContextState;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
/* This takes a max of 15 dwords */
PRIMGETPTR( dev_priv );
@@ -80,13 +89,13 @@ static void mgaEmitContext(drm_mga_private_t *dev_priv )
if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
PRIMOUTREG( MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG] );
PRIMOUTREG( MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0] );
- PRIMOUTREG( MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1] );
+ PRIMOUTREG( MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1] );
PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] );
} else {
PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] );
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
}
PRIMADVANCE( dev_priv );
@@ -97,27 +106,28 @@ static void mgaG200EmitTex( drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int *regs = sarea_priv->TexState[0];
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
PRIMGETPTR( dev_priv );
/* This takes 20 dwords */
- PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
- PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
- PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
- PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
+ PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
+ PRIMOUTREG( MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
+ PRIMOUTREG( MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
+ PRIMOUTREG( MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
- PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
- PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
- PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
- PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
+ PRIMOUTREG( MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
+ PRIMOUTREG( MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
+ PRIMOUTREG( MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
+ PRIMOUTREG( MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
- PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
- PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
- PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
- PRIMOUTREG(0x2d00 + 24*4, regs[MGA_TEXREG_WIDTH] );
+ PRIMOUTREG( MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
+ PRIMOUTREG( MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
+ PRIMOUTREG( MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
+ PRIMOUTREG( 0x2d00 + 24*4, regs[MGA_TEXREG_WIDTH] );
- PRIMOUTREG(0x2d00 + 34*4, regs[MGA_TEXREG_HEIGHT] );
+ PRIMOUTREG( 0x2d00 + 34*4, regs[MGA_TEXREG_HEIGHT] );
PRIMOUTREG( MGAREG_TEXTRANS, 0xffff );
PRIMOUTREG( MGAREG_TEXTRANSHIGH, 0xffff );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
@@ -131,34 +141,35 @@ static void mgaG400EmitTex0( drm_mga_private_t *dev_priv )
unsigned int *regs = sarea_priv->TexState[0];
int multitex = sarea_priv->WarpPipe & MGA_T2;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
PRIMGETPTR( dev_priv );
/* This takes a max of 30 dwords */
- PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
- PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
- PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
- PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
+ PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
+ PRIMOUTREG( MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
+ PRIMOUTREG( MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
+ PRIMOUTREG( MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
- PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
- PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
- PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
- PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
+ PRIMOUTREG( MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
+ PRIMOUTREG( MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
+ PRIMOUTREG( MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
+ PRIMOUTREG( MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
- PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
- PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
- PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
- PRIMOUTREG(0x2d00 + 49*4, 0);
+ PRIMOUTREG( MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
+ PRIMOUTREG( MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
+ PRIMOUTREG( MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
+ PRIMOUTREG( 0x2d00 + 49*4, 0 );
- PRIMOUTREG(0x2d00 + 57*4, 0);
- PRIMOUTREG(0x2d00 + 53*4, 0);
- PRIMOUTREG(0x2d00 + 61*4, 0);
+ PRIMOUTREG( 0x2d00 + 57*4, 0 );
+ PRIMOUTREG( 0x2d00 + 53*4, 0 );
+ PRIMOUTREG( 0x2d00 + 61*4, 0 );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
if (!multitex) {
- PRIMOUTREG(0x2d00 + 52*4, 0x40 );
- PRIMOUTREG(0x2d00 + 60*4, 0x40 );
+ PRIMOUTREG( 0x2d00 + 52*4, 0x40 );
+ PRIMOUTREG( 0x2d00 + 60*4, 0x40 );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
PRIMOUTREG( MGAREG_DMAPAD, 0 );
}
@@ -178,85 +189,127 @@ static void mgaG400EmitTex1( drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int *regs = sarea_priv->TexState[1];
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
- PRIMGETPTR(dev_priv);
+ PRIMGETPTR( dev_priv );
/* This takes 25 dwords */
- PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | TMC_map1_enable);
- PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
- PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
- PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
-
- PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
- PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
- PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
- PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
-
- PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
- PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
- PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
- PRIMOUTREG(0x2d00 + 49*4, 0);
-
- PRIMOUTREG(0x2d00 + 57*4, 0);
- PRIMOUTREG(0x2d00 + 53*4, 0);
- PRIMOUTREG(0x2d00 + 61*4, 0);
- PRIMOUTREG(0x2d00 + 52*4, regs[MGA_TEXREG_WIDTH] | 0x40 );
-
- PRIMOUTREG(0x2d00 + 60*4, regs[MGA_TEXREG_HEIGHT] | 0x40 );
+
+ PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | TMC_map1_enable );
+ PRIMOUTREG( MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] );
+ PRIMOUTREG( MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] );
+ PRIMOUTREG( MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] );
+
+ PRIMOUTREG( MGAREG_TEXORG, regs[MGA_TEXREG_ORG] );
+ PRIMOUTREG( MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] );
+ PRIMOUTREG( MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] );
+ PRIMOUTREG( MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] );
+
+ PRIMOUTREG( MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] );
+ PRIMOUTREG( MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] );
+ PRIMOUTREG( MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] );
+ PRIMOUTREG( 0x2d00 + 49*4, 0 );
+
+ PRIMOUTREG( 0x2d00 + 57*4, 0 );
+ PRIMOUTREG( 0x2d00 + 53*4, 0 );
+ PRIMOUTREG( 0x2d00 + 61*4, 0 );
+ PRIMOUTREG( 0x2d00 + 52*4, regs[MGA_TEXREG_WIDTH] | 0x40 );
+
+ PRIMOUTREG( 0x2d00 + 60*4, regs[MGA_TEXREG_HEIGHT] | 0x40 );
PRIMOUTREG( MGAREG_TEXTRANS, 0xffff );
PRIMOUTREG( MGAREG_TEXTRANSHIGH, 0xffff );
- PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
+ PRIMOUTREG( MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] );
+
+ PRIMADVANCE( dev_priv );
+}
+
+/* Required when switching from multitexturing to single texturing.
+ */
+static void mgaG400EmitTexFlush( drm_mga_private_t *dev_priv )
+{
+ PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
+ PRIMGETPTR( dev_priv );
+
+ /* This takes 15 dwords */
+
+ PRIMOUTREG( MGAREG_YDST, 0 );
+ PRIMOUTREG( MGAREG_FXLEFT, 0 );
+ PRIMOUTREG( MGAREG_FXRIGHT, 1 );
+ PRIMOUTREG( MGAREG_DWGCTL, MGA_FLUSH_CMD );
+
+ PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 1 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DWGSYNC, 0x7000 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+
+ PRIMOUTREG( MGAREG_TEXCTL2, 0 );
+ PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
+ PRIMOUTREG( MGAREG_TEXCTL2, 0x80 );
+ PRIMOUTREG( MGAREG_LEN + MGAREG_MGA_EXEC, 0 );
PRIMADVANCE( dev_priv );
}
-static void mgaG400EmitPipe(drm_mga_private_t *dev_priv )
+static void mgaG400EmitPipe( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->WarpPipe;
float fParam = 12800.0f;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
- PRIMGETPTR(dev_priv);
+ PRIMGETPTR( dev_priv );
+
+ /* This takes 30 dwords */
- /* This takes 25 dwords */
-
/* Establish vertex size.
*/
if (pipe & MGA_T2) {
- PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
- PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09);
- PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000);
- PRIMOUTREG(MGAREG_WFLAG, 0);
+ PRIMOUTREG( MGAREG_WIADDR2, WIA_wmode_suspend );
+ PRIMOUTREG( MGAREG_WVRTXSZ, 0x00001e09 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0x1e000000 );
} else {
- PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend);
- PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807);
- PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000);
- PRIMOUTREG(MGAREG_WFLAG, 0);
+ PRIMOUTREG( MGAREG_WIADDR2, WIA_wmode_suspend );
+ PRIMOUTREG( MGAREG_WVRTXSZ, 0x00001807 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0 );
+ PRIMOUTREG( MGAREG_WACCEPTSEQ, 0x18000000 );
}
- PRIMOUTREG(MGAREG_WFLAG1, 0);
- PRIMOUTREG(0x2d00 + 56*4, *((u32 *)(&fParam)));
- PRIMOUTREG(MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_DMAPAD, 0);
+ PRIMOUTREG( MGAREG_WFLAG, 0 );
+ PRIMOUTREG( MGAREG_WFLAG1, 0 );
+ PRIMOUTREG( 0x2d00 + 56*4, *((u32 *)(&fParam)) );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
- PRIMOUTREG(0x2d00 + 49*4, 0); /* Tex stage 0 */
- PRIMOUTREG(0x2d00 + 57*4, 0); /* Tex stage 0 */
- PRIMOUTREG(0x2d00 + 53*4, 0); /* Tex stage 1 */
- PRIMOUTREG(0x2d00 + 61*4, 0); /* Tex stage 1 */
+ PRIMOUTREG( 0x2d00 + 49*4, 0 ); /* Tex stage 0 */
+ PRIMOUTREG( 0x2d00 + 57*4, 0 ); /* Tex stage 0 */
+ PRIMOUTREG( 0x2d00 + 53*4, 0 ); /* Tex stage 1 */
+ PRIMOUTREG( 0x2d00 + 61*4, 0 ); /* Tex stage 1 */
- PRIMOUTREG(0x2d00 + 54*4, 0x40); /* Tex stage 0 : w */
- PRIMOUTREG(0x2d00 + 62*4, 0x40); /* Tex stage 0 : h */
- PRIMOUTREG(0x2d00 + 52*4, 0x40); /* Tex stage 1 : w */
- PRIMOUTREG(0x2d00 + 60*4, 0x40); /* Tex stage 1 : h */
+ PRIMOUTREG( 0x2d00 + 54*4, 0x40 ); /* Tex stage 0 : w */
+ PRIMOUTREG( 0x2d00 + 62*4, 0x40 ); /* Tex stage 0 : h */
+ PRIMOUTREG( 0x2d00 + 52*4, 0x40 ); /* Tex stage 1 : w */
+ PRIMOUTREG( 0x2d00 + 60*4, 0x40 ); /* Tex stage 1 : h */
/* Dma pading required due to hw bug */
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_WIADDR2, (__u32)(dev_priv->WarpIndex[pipe].phys_addr |
- WIA_wmode_start | WIA_wagp_agp));
- PRIMADVANCE(dev_priv);
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_WIADDR2, (u32)(dev_priv->WarpIndex[pipe].phys_addr |
+ WIA_wmode_start | WIA_wagp_agp) );
+ PRIMADVANCE( dev_priv );
}
static void mgaG200EmitPipe( drm_mga_private_t *dev_priv )
@@ -264,40 +317,45 @@ static void mgaG200EmitPipe( drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->WarpPipe;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
- PRIMGETPTR(dev_priv);
+ PRIMGETPTR( dev_priv );
/* This takes 15 dwords */
- PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend);
- PRIMOUTREG(MGAREG_WVRTXSZ, 7);
- PRIMOUTREG(MGAREG_WFLAG, 0);
- PRIMOUTREG(0x2d00 + 24*4, 0); /* tex w/h */
+ PRIMOUTREG( MGAREG_WIADDR, WIA_wmode_suspend );
+ PRIMOUTREG( MGAREG_WVRTXSZ, 7 );
+ PRIMOUTREG( MGAREG_WFLAG, 0 );
+ PRIMOUTREG( 0x2d00 + 24*4, 0 ); /* tex w/h */
- PRIMOUTREG(0x2d00 + 25*4, 0x100);
- PRIMOUTREG(0x2d00 + 34*4, 0); /* tex w/h */
- PRIMOUTREG(0x2d00 + 42*4, 0xFFFF);
- PRIMOUTREG(0x2d00 + 60*4, 0xFFFF);
+ PRIMOUTREG( 0x2d00 + 25*4, 0x100 );
+ PRIMOUTREG( 0x2d00 + 34*4, 0 ); /* tex w/h */
+ PRIMOUTREG( 0x2d00 + 42*4, 0xFFFF );
+ PRIMOUTREG( 0x2d00 + 60*4, 0xFFFF );
/* Dma pading required due to hw bug */
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff);
- PRIMOUTREG(MGAREG_WIADDR, (__u32)(dev_priv->WarpIndex[pipe].phys_addr |
- WIA_wmode_start | WIA_wagp_agp));
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_DMAPAD, 0xffffffff );
+ PRIMOUTREG( MGAREG_WIADDR, (u32)(dev_priv->WarpIndex[pipe].phys_addr |
+ WIA_wmode_start | WIA_wagp_agp) );
- PRIMADVANCE(dev_priv);
+ PRIMADVANCE( dev_priv );
}
static void mgaEmitState( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int dirty = sarea_priv->dirty;
+ DRM_DEBUG("%s\n", __FUNCTION__);
if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
int multitex = sarea_priv->WarpPipe & MGA_T2;
- if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
+ if (sarea_priv->WarpPipe != dev_priv->WarpPipe) {
+ if ((dev_priv->WarpPipe & MGA_T2) && !multitex) {
+ mgaG400EmitTexFlush( dev_priv );
+ }
mgaG400EmitPipe( dev_priv );
dev_priv->WarpPipe = sarea_priv->WarpPipe;
}
@@ -342,6 +400,8 @@ static int mgaVerifyContext(drm_mga_private_t *dev_priv )
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int *regs = sarea_priv->ContextState;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset &&
regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) {
DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n",
@@ -361,6 +421,8 @@ static int mgaVerifyTex(drm_mga_private_t *dev_priv,
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) {
DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n",
sarea_priv->TexState[unit][MGA_TEXREG_ORG],
@@ -378,6 +440,8 @@ static int mgaVerifyState( drm_mga_private_t *dev_priv )
unsigned int dirty = sarea_priv->dirty;
int rv = 0;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
@@ -408,6 +472,8 @@ static int mgaVerifyIload( drm_mga_private_t *dev_priv,
unsigned long bus_address,
unsigned int dstOrg, int length )
{
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
if(dstOrg < dev_priv->textureOffset ||
dstOrg + length >
(dev_priv->textureOffset + dev_priv->textureSize)) {
@@ -431,35 +497,34 @@ static void mga_dma_dispatch_tex_blit( drm_device_t *dev,
int use_agp = PDEA_pagpxfer_enable | 0x00000001;
u16 y2;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
y2 = length / 64;
- PRIM_OVERFLOW(dev, dev_priv, 30);
+ PRIM_OVERFLOW( dev, dev_priv, 30 );
PRIMGETPTR( dev_priv );
- dev_priv->last_sync_tag = mga_create_sync_tag(dev);
-
- PRIMOUTREG( MGAREG_DSTORG, destOrg);
- PRIMOUTREG( MGAREG_MACCESS, 0x00000000);
+ PRIMOUTREG( MGAREG_DSTORG, destOrg );
+ PRIMOUTREG( MGAREG_MACCESS, 0x00000000 );
DRM_DEBUG("srcorg : %lx\n", bus_address | use_agp);
- PRIMOUTREG( MGAREG_SRCORG, (u32) bus_address | use_agp);
- PRIMOUTREG( MGAREG_AR5, 64);
-
- PRIMOUTREG( MGAREG_PITCH, 64);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DWGCTL, MGA_COPY_CMD);
-
- PRIMOUTREG(MGAREG_AR0, 63);
- PRIMOUTREG(MGAREG_AR3, 0);
- PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16));
- PRIMOUTREG(MGAREG_YDSTLEN+MGAREG_MGA_EXEC, y2);
+ PRIMOUTREG( MGAREG_SRCORG, (u32) bus_address | use_agp );
+ PRIMOUTREG( MGAREG_AR5, 64 );
+
+ PRIMOUTREG( MGAREG_PITCH, 64 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DWGCTL, MGA_COPY_CMD );
+
+ PRIMOUTREG( MGAREG_AR0, 63 );
+ PRIMOUTREG( MGAREG_AR3, 0 );
+ PRIMOUTREG( MGAREG_FXBNDRY, (63 << 16) );
+ PRIMOUTREG( MGAREG_YDSTLEN+MGAREG_MGA_EXEC, y2 );
- PRIMOUTREG( MGAREG_SRCORG, 0);
- PRIMOUTREG( MGAREG_PITCH, dev_priv->stride / dev_priv->cpp);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag);
- PRIMADVANCE(dev_priv);
+ PRIMOUTREG( MGAREG_SRCORG, 0 );
+ PRIMOUTREG( MGAREG_PITCH, dev_priv->stride / dev_priv->cpp );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMADVANCE( dev_priv );
}
static void mga_dma_dispatch_vertex(drm_device_t *dev,
@@ -474,33 +539,100 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
int i = 0;
int primary_needed;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
DRM_DEBUG("dispatch vertex %d addr 0x%lx, "
"length 0x%x nbox %d dirty %x\n",
buf->idx, address, length,
sarea_priv->nbox, sarea_priv->dirty);
+ DRM_DEBUG("used : %d, total : %d\n", buf->used, buf->total);
+ if(sarea_priv->WarpPipe & MGA_T2) {
+ if ((buf->used/4) % 10)
+ DRM_DEBUG("Multitex Buf is not aligned properly!!!\n");
+ } else {
+ if ((buf->used/4) % 8)
+ DRM_DEBUG("Buf is not aligned properly!!!\n");
+ }
- dev_priv->last_sync_tag = mga_create_sync_tag(dev);
+ if (buf->used) {
+ /* WARNING: if you change any of the state functions verify
+ * these numbers (Overestimating this doesn't hurt).
+ */
+ buf_priv->dispatched = 1;
+ primary_needed = (30+15+15+30+25+
+ 10 +
+ 15 * MGA_NR_SAREA_CLIPRECTS);
+ PRIM_OVERFLOW(dev, dev_priv, primary_needed);
+ mgaEmitState( dev_priv );
+
+ do {
+ if (i < sarea_priv->nbox) {
+ DRM_DEBUG("idx %d Emit box %d/%d:"
+ "%d,%d - %d,%d\n",
+ buf->idx,
+ i, sarea_priv->nbox,
+ sarea_priv->boxes[i].x1,
+ sarea_priv->boxes[i].y1,
+ sarea_priv->boxes[i].x2,
+ sarea_priv->boxes[i].y2);
+
+ mgaEmitClipRect( dev_priv,
+ &sarea_priv->boxes[i] );
+ }
+
+ PRIMGETPTR( dev_priv );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_SECADDRESS,
+ ((u32)address) | TT_VERTEX );
+ PRIMOUTREG( MGAREG_SECEND,
+ (((u32)(address + length)) | use_agp) );
+ PRIMADVANCE( dev_priv );
+ } while (++i < sarea_priv->nbox);
+ }
- if (buf_priv->discard) {
- buf_priv->my_freelist->age = dev_priv->last_sync_tag;
+ if (buf_priv->discard) {
+ if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
+ buf_priv->dispatched = 0;
mga_freelist_put(dev, buf);
}
- /* WARNING: if you change any of the state functions verify
- * these numbers (Overestimating this doesn't hurt).
- */
- primary_needed = (25+15+30+25+
- 10 +
- 15 * MGA_NR_SAREA_CLIPRECTS);
+}
- PRIM_OVERFLOW(dev, dev_priv, primary_needed);
- mgaEmitState( dev_priv );
+static void mga_dma_dispatch_indices(drm_device_t *dev,
+ drm_buf_t *buf,
+ unsigned int start,
+ unsigned int end)
+{
+ drm_mga_private_t *dev_priv = dev->dev_private;
+ drm_mga_buf_priv_t *buf_priv = buf->dev_private;
+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
+ unsigned int address = (unsigned int)buf->bus_address;
+ int use_agp = PDEA_pagpxfer_enable;
+ int i = 0;
+ int primary_needed;
+ PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
+ DRM_DEBUG("dispatch indices %d addr 0x%x, "
+ "start 0x%x end 0x%x nbox %d dirty %x\n",
+ buf->idx, address, start, end,
+ sarea_priv->nbox, sarea_priv->dirty);
+
+ if (start != end) {
+ /* WARNING: if you change any of the state functions verify
+ * these numbers (Overestimating this doesn't hurt).
+ */
+ buf_priv->dispatched = 1;
+ primary_needed = (25+15+30+25+
+ 10 +
+ 15 * MGA_NR_SAREA_CLIPRECTS);
+ PRIM_OVERFLOW( dev, dev_priv, primary_needed );
+ mgaEmitState( dev_priv );
- if (buf->used) {
do {
if (i < sarea_priv->nbox) {
DRM_DEBUG("idx %d Emit box %d/%d:"
@@ -515,25 +647,23 @@ static void mga_dma_dispatch_vertex(drm_device_t *dev,
mgaEmitClipRect( dev_priv,
&sarea_priv->boxes[i] );
}
-
- PRIMGETPTR(dev_priv);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_SECADDRESS,
- ((__u32)address) | TT_VERTEX);
- PRIMOUTREG( MGAREG_SECEND,
- (((__u32)(address + length)) |
- use_agp));
+
+ PRIMGETPTR( dev_priv );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_SETUPADDRESS,
+ ((address + start) |
+ SETADD_mode_vertlist) );
+ PRIMOUTREG( MGAREG_SETUPEND,
+ ((address + end) | use_agp) );
PRIMADVANCE( dev_priv );
} while (++i < sarea_priv->nbox);
}
-
- PRIMGETPTR( dev_priv );
- PRIMOUTREG(MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_DWGSYNC, dev_priv->last_sync_tag);
- PRIMADVANCE( dev_priv );
+ if (buf_priv->discard) {
+ if (buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
+ buf_priv->dispatched = 0;
+ mga_freelist_put(dev, buf);
+ }
}
@@ -550,6 +680,7 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
int i;
int primary_needed;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
if ( dev_priv->sgram )
cmd = MGA_CLEAR_CMD | DC_atype_blk;
@@ -557,10 +688,9 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
cmd = MGA_CLEAR_CMD | DC_atype_rstr;
primary_needed = nbox * 70;
- if(primary_needed == 0) primary_needed = 70;
- PRIM_OVERFLOW(dev, dev_priv, primary_needed);
+ if (primary_needed == 0) primary_needed = 70;
+ PRIM_OVERFLOW( dev, dev_priv, primary_needed );
PRIMGETPTR( dev_priv );
- dev_priv->last_sync_tag = mga_create_sync_tag(dev);
for (i = 0 ; i < nbox ; i++) {
unsigned int height = pbox[i].y2 - pbox[i].y1;
@@ -571,55 +701,50 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int flags,
if ( flags & MGA_FRONT ) {
DRM_DEBUG("clear front\n");
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height);
- PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1);
-
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_FCOL, clear_color);
- PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
- PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height);
+ PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1);
+
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_FCOL, clear_color );
+ PRIMOUTREG( MGAREG_DSTORG, dev_priv->frontOffset );
+ PRIMOUTREG( MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
}
if ( flags & MGA_BACK ) {
DRM_DEBUG("clear back\n");
PRIMOUTREG( MGAREG_DMAPAD, 0);
PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height);
- PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1);
+ PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height );
+ PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 );
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_FCOL, clear_color);
- PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset);
- PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_FCOL, clear_color );
+ PRIMOUTREG( MGAREG_DSTORG, dev_priv->backOffset );
+ PRIMOUTREG( MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
}
if ( flags & MGA_DEPTH ) {
DRM_DEBUG("clear depth\n");
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height);
- PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1);
-
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_FCOL, clear_zval);
- PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset);
- PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_YDSTLEN, (pbox[i].y1<<16)|height );
+ PRIMOUTREG( MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1 );
+
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_FCOL, clear_zval );
+ PRIMOUTREG( MGAREG_DSTORG, dev_priv->depthOffset );
+ PRIMOUTREG( MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd );
}
}
/* Force reset of DWGCTL */
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
-
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag);
- PRIMADVANCE(dev_priv);
+ PRIMADVANCE( dev_priv );
}
static void mga_dma_dispatch_swap( drm_device_t *dev )
@@ -632,23 +757,22 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
int i;
int primary_needed;
PRIMLOCALS;
+ DRM_DEBUG("%s\n", __FUNCTION__);
primary_needed = nbox * 5;
primary_needed += 60;
PRIM_OVERFLOW(dev, dev_priv, primary_needed);
PRIMGETPTR( dev_priv );
- dev_priv->last_sync_tag = mga_create_sync_tag(dev);
+ PRIMOUTREG( MGAREG_DSTORG, dev_priv->frontOffset );
+ PRIMOUTREG( MGAREG_MACCESS, dev_priv->mAccess );
+ PRIMOUTREG( MGAREG_SRCORG, dev_priv->backOffset );
+ PRIMOUTREG( MGAREG_AR5, dev_priv->stride/2 );
- PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset);
- PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess);
- PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset);
- PRIMOUTREG(MGAREG_AR5, dev_priv->stride/2);
-
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD);
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DWGCTL, MGA_COPY_CMD );
for (i = 0 ; i < nbox; i++) {
unsigned int h = pbox[i].y2 - pbox[i].y1;
@@ -658,23 +782,19 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
pbox[i].x1, pbox[i].y1,
pbox[i].x2, pbox[i].y2);
- PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1);
- PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1);
- PRIMOUTREG(MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16));
- PRIMOUTREG(MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h);
+ PRIMOUTREG( MGAREG_AR0, start + pbox[i].x2 - 1 );
+ PRIMOUTREG( MGAREG_AR3, start + pbox[i].x1 );
+ PRIMOUTREG( MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16) );
+ PRIMOUTREG( MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h );
}
/* Force reset of DWGCTL */
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_DMAPAD, 0 );
+ PRIMOUTREG( MGAREG_SRCORG, 0 );
PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] );
- PRIMOUTREG( MGAREG_SRCORG, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DMAPAD, 0);
- PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag);
- PRIMADVANCE(dev_priv);
+ PRIMADVANCE( dev_priv );
}
int mga_clear_bufs(struct inode *inode, struct file *filp,
@@ -684,12 +804,11 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
- __volatile__ unsigned int *status =
- (__volatile__ unsigned int *)dev_priv->status_page;
drm_mga_clear_t clear;
copy_from_user_ret(&clear, (drm_mga_clear_t *)arg, sizeof(clear),
-EFAULT);
+ DRM_DEBUG("%s\n", __FUNCTION__);
if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
DRM_ERROR("mga_clear_bufs called without lock held\n");
@@ -706,8 +825,8 @@ int mga_clear_bufs(struct inode *inode, struct file *filp,
clear.clear_color,
clear.clear_depth );
PRIMUPDATE(dev_priv);
+ mga_flush_write_combine();
mga_dma_schedule(dev, 1);
- sarea_priv->last_dispatch = status[1];
return 0;
}
@@ -718,8 +837,7 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
- __volatile__ unsigned int *status =
- (__volatile__ unsigned int *)dev_priv->status_page;
+ DRM_DEBUG("%s\n", __FUNCTION__);
if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
DRM_ERROR("mga_swap_bufs called without lock held\n");
@@ -734,10 +852,9 @@ int mga_swap_bufs(struct inode *inode, struct file *filp,
dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX;
mga_dma_dispatch_swap( dev );
PRIMUPDATE(dev_priv);
- set_bit(0, &dev_priv->current_prim->swap_pending);
- dev_priv->current_prim->swap_pending = 1;
+ set_bit(MGA_BUF_SWAP_PENDING, &dev_priv->current_prim->buffer_status);
+ mga_flush_write_combine();
mga_dma_schedule(dev, 1);
- sarea_priv->last_dispatch = status[1];
return 0;
}
@@ -749,12 +866,11 @@ int mga_iload(struct inode *inode, struct file *filp,
drm_device_dma_t *dma = dev->dma;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
- __volatile__ unsigned int *status =
- (__volatile__ unsigned int *)dev_priv->status_page;
drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv;
drm_mga_iload_t iload;
unsigned long bus_address;
+ DRM_DEBUG("%s\n", __FUNCTION__);
DRM_DEBUG("Starting Iload\n");
copy_from_user_ret(&iload, (drm_mga_iload_t *)arg, sizeof(iload),
@@ -783,11 +899,11 @@ int mga_iload(struct inode *inode, struct file *filp,
mga_dma_dispatch_tex_blit(dev, bus_address, iload.length,
iload.destOrg);
- buf_priv->my_freelist->age = dev_priv->last_sync_tag;
+ AGEBUF(dev_priv, buf_priv);
buf_priv->discard = 1;
mga_freelist_put(dev, buf);
+ mga_flush_write_combine();
mga_dma_schedule(dev, 1);
- sarea_priv->last_dispatch = status[1];
return 0;
}
@@ -797,13 +913,11 @@ int mga_vertex(struct inode *inode, struct file *filp,
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
- drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
- __volatile__ unsigned int *status =
- (__volatile__ unsigned int *)dev_priv->status_page;
drm_device_dma_t *dma = dev->dma;
drm_buf_t *buf;
drm_mga_buf_priv_t *buf_priv;
drm_mga_vertex_t vertex;
+ DRM_DEBUG("%s\n", __FUNCTION__);
copy_from_user_ret(&vertex, (drm_mga_vertex_t *)arg, sizeof(vertex),
-EFAULT);
@@ -822,25 +936,75 @@ int mga_vertex(struct inode *inode, struct file *filp,
buf_priv->discard = vertex.discard;
if (!mgaVerifyState(dev_priv)) {
- if (vertex.discard) {
- buf_priv->my_freelist->age = dev_priv->last_sync_tag;
- mga_freelist_put(dev, buf);
+ if (vertex.discard) {
+ if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
+ buf_priv->dispatched = 0;
+ mga_freelist_put(dev, buf);
}
+ DRM_DEBUG("bad state\n");
return -EINVAL;
}
mga_dma_dispatch_vertex(dev, buf);
PRIMUPDATE(dev_priv);
+ mga_flush_write_combine();
mga_dma_schedule(dev, 1);
- sarea_priv->last_dispatch = status[1];
return 0;
}
+
+int mga_indices(struct inode *inode, struct file *filp,
+ unsigned int cmd, unsigned long arg)
+{
+ drm_file_t *priv = filp->private_data;
+ drm_device_t *dev = priv->dev;
+ drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
+ drm_device_dma_t *dma = dev->dma;
+ drm_buf_t *buf;
+ drm_mga_buf_priv_t *buf_priv;
+ drm_mga_indices_t indices;
+ DRM_DEBUG("%s\n", __FUNCTION__);
+
+ copy_from_user_ret(&indices, (drm_mga_indices_t *)arg, sizeof(indices),
+ -EFAULT);
+
+ if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+ DRM_ERROR("mga_indices called without lock held\n");
+ return -EINVAL;
+ }
+
+ DRM_DEBUG("mga_indices\n");
+
+ buf = dma->buflist[ indices.idx ];
+ buf_priv = buf->dev_private;
+
+ buf_priv->discard = indices.discard;
+
+ if (!mgaVerifyState(dev_priv)) {
+ if (indices.discard) {
+ if(buf_priv->dispatched == 1) AGEBUF(dev_priv, buf_priv);
+ buf_priv->dispatched = 0;
+ mga_freelist_put(dev, buf);
+ }
+ return -EINVAL;
+ }
+
+ mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
+
+ PRIMUPDATE(dev_priv);
+ mga_flush_write_combine();
+ mga_dma_schedule(dev, 1);
+ return 0;
+}
+
+
+
static int mga_dma_get_buffers(drm_device_t *dev, drm_dma_t *d)
{
int i;
drm_buf_t *buf;
+ DRM_DEBUG("%s\n", __FUNCTION__);
for (i = d->granted_count; i < d->request_count; i++) {
buf = mga_freelist_get(dev);
@@ -865,12 +1029,9 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
drm_file_t *priv = filp->private_data;
drm_device_t *dev = priv->dev;
drm_device_dma_t *dma = dev->dma;
- drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
- drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
- __volatile__ unsigned int *status =
- (__volatile__ unsigned int *)dev_priv->status_page;
int retcode = 0;
drm_dma_t d;
+ DRM_DEBUG("%s\n", __FUNCTION__);
copy_from_user_ret(&d, (drm_dma_t *)arg, sizeof(d), -EFAULT);
DRM_DEBUG("%d %d: %d send, %d req\n",
@@ -906,6 +1067,5 @@ int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd,
DRM_DEBUG("%d returning, granted = %d\n",
current->pid, d.granted_count);
copy_to_user_ret((drm_dma_t *)arg, &d, sizeof(d), -EFAULT);
- sarea_priv->last_dispatch = status[1];
return retcode;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 22:33:55 +0000