Merge trunk into r200-branchr200-0-1-20020715

author: Keith Whitwell <keith@tungstengraphics.com> 2002-07-15 20:21:18 +0000
committer: Keith Whitwell <keith@tungstengraphics.com> 2002-07-15 20:21:18 +0000
commit: eef49a73b541d69be5da9b289deff36f5bb96ab0 (patch)
tree: 0cc0fa5559d7bf87c25d277ef63d816d0090ccf4 /linux
parent: deb296f395bb16ef7cf4bfe48f6e6c2cbacea0bc (diff)
33 files changed, 161 insertions, 23858 deletions
diff --git a/linux/drm.h b/linux/drm.h
index 6ab295c4..376568e0 100644
--- a/linux/drm.h
+++ b/linux/drm.h
@@ -38,10 +38,27 @@
 #if defined(__linux__)
 #include <linux/config.h>
 #include <asm/ioctl.h>		/* For _IO* macros */
-#define DRM_IOCTL_NR(n)	     _IOC_NR(n)
-#elif defined(__FreeBSD__)
+#define DRM_IOCTL_NR(n)		_IOC_NR(n)
+#define DRM_IOC_VOID		_IOC_NONE
+#define DRM_IOC_READ		_IOC_READ
+#define DRM_IOC_WRITE		_IOC_WRITE
+#define DRM_IOC_READWRITE	_IOC_READ|_IOC_WRITE
+#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
+#elif defined(__FreeBSD__) || defined(__NetBSD__)
+#if defined(__FreeBSD__) && defined(XFree86Server)
+/* Prevent name collision when including sys/ioccom.h */
+#undef ioctl
 #include <sys/ioccom.h>
-#define DRM_IOCTL_NR(n)	     ((n) & 0xff)
+#define ioctl(a,b,c)		xf86ioctl(a,b,c)
+#else
+#include <sys/ioccom.h>
+#endif /* __FreeBSD__ && xf86ioctl */
+#define DRM_IOCTL_NR(n)		((n) & 0xff)
+#define DRM_IOC_VOID		IOC_VOID
+#define DRM_IOC_READ		IOC_OUT
+#define DRM_IOC_WRITE		IOC_IN
+#define DRM_IOC_READWRITE	IOC_INOUT
+#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
 #endif
 
 #define XFREE86_VERSION(major,minor,patch,snap) \
@@ -367,10 +384,9 @@ typedef struct drm_scatter_gather {
 
 #define DRM_IOCTL_BASE			'd'
 #define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,size)		_IOR(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOW(nr,size)		_IOW(DRM_IOCTL_BASE,nr,size)
-#define DRM_IOWR(nr,size)		_IOWR(DRM_IOCTL_BASE,nr,size)
-
+#define DRM_IOR(nr,type)		_IOR(DRM_IOCTL_BASE,nr,type)
+#define DRM_IOW(nr,type)		_IOW(DRM_IOCTL_BASE,nr,type)
+#define DRM_IOWR(nr,type)		_IOWR(DRM_IOCTL_BASE,nr,type)
 
 #define DRM_IOCTL_VERSION		DRM_IOWR(0x00, drm_version_t)
 #define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, drm_unique_t)
diff --git a/linux/drmP.h b/linux/drmP.h
index ee6c3781..c00efb4c 100644
--- a/linux/drmP.h
+++ b/linux/drmP.h
@@ -71,6 +71,8 @@
 #include <asm/pgalloc.h>
 #include "drm.h"
 
+#include "drm_os_linux.h"
+
 /* DRM template customization defaults
  */
 #ifndef __HAVE_AGP
@@ -101,7 +103,7 @@
 #define __REALLY_HAVE_AGP	(__HAVE_AGP && (defined(CONFIG_AGP) || \
 						defined(CONFIG_AGP_MODULE)))
 #define __REALLY_HAVE_MTRR	(__HAVE_MTRR && defined(CONFIG_MTRR))
-
+#define __REALLY_HAVE_SG	(__HAVE_SG)
 
 /* Begin the DRM...
  */
diff --git a/linux/drm_context.h b/linux/drm_context.h
index e155946d..39267b14 100644
--- a/linux/drm_context.h
+++ b/linux/drm_context.h
@@ -555,7 +555,7 @@ static int DRM(alloc_queue)(drm_device_t *dev)
 				/* Allocate a new queue */
 	down(&dev->struct_sem);
 
-	queue = gamma_alloc(sizeof(*queue), DRM_MEM_QUEUES);
+	queue = DRM(alloc)(sizeof(*queue), DRM_MEM_QUEUES);
 	memset(queue, 0, sizeof(*queue));
 	atomic_set(&queue->use_count, 1);
 
diff --git a/linux/drm_drv.h b/linux/drm_drv.h
index b124c422..af6858d7 100644
--- a/linux/drm_drv.h
+++ b/linux/drm_drv.h
@@ -127,6 +127,22 @@ static struct file_operations	DRM(fops) = {	\
 }
 #endif
 
+#ifndef MODULE
+/* DRM(options) is called by the kernel to parse command-line options
+ * passed via the boot-loader (e.g., LILO).  It calls the insmod option
+ * routine, drm_parse_drm.
+ */
+/* Use an additional macro to avoid preprocessor troubles */
+#define DRM_OPTIONS_FUNC DRM(options)
+static int __init DRM(options)( char *str )
+{
+	DRM(parse_options)( str );
+	return 1;
+}
+
+__setup( DRIVER_NAME "=", DRM_OPTIONS_FUNC );
+#undef DRM_OPTIONS_FUNC
+#endif
 
 /*
  * The default number of instances (minor numbers) to initialize.
diff --git a/linux/gamma.h b/linux/gamma.h
index a38c3c28..44d8d5bc 100644
--- a/linux/gamma.h
+++ b/linux/gamma.h
@@ -38,6 +38,31 @@
  */
 #define __HAVE_MTRR			1
 
+#define DRIVER_AUTHOR		"VA Linux Systems Inc."
+
+#define DRIVER_NAME		"gamma"
+#define DRIVER_DESC		"3DLabs gamma"
+#define DRIVER_DATE		"20010624"
+
+#define DRIVER_MAJOR		2
+#define DRIVER_MINOR		0
+#define DRIVER_PATCHLEVEL	0
+
+#define DRIVER_IOCTLS							  \
+	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	     = { gamma_dma,	  1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_INIT)] = { gamma_dma_init,  1, 1 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_COPY)] = { gamma_dma_copy,  1, 1 }
+
+#define IOCTL_TABLE_NAME	DRM(ioctls)
+#define IOCTL_FUNC_NAME 	DRM(ioctl)
+
+#define __HAVE_COUNTERS		5
+#define __HAVE_COUNTER6		_DRM_STAT_IRQ
+#define __HAVE_COUNTER7		_DRM_STAT_DMA
+#define __HAVE_COUNTER8		_DRM_STAT_PRIMARY
+#define __HAVE_COUNTER9		_DRM_STAT_SPECIAL
+#define __HAVE_COUNTER10	_DRM_STAT_MISSED
+
 /* DMA customization:
  */
 #define __HAVE_DMA			1
diff --git a/linux/gamma_drv.c b/linux/gamma_drv.c
index 3d37a5fc..b41526bb 100644
--- a/linux/gamma_drv.c
+++ b/linux/gamma_drv.c
@@ -36,32 +36,6 @@
 #include "gamma_drm.h"
 #include "gamma_drv.h"
 
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"gamma"
-#define DRIVER_DESC		"3DLabs gamma"
-#define DRIVER_DATE		"20010624"
-
-#define DRIVER_MAJOR		2
-#define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	0
-
-#define DRIVER_IOCTLS							  \
-	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	     = { gamma_dma,	  1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_INIT)] = { gamma_dma_init,  1, 1 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_GAMMA_COPY)] = { gamma_dma_copy,  1, 1 }
-
-#define IOCTL_TABLE_NAME	DRM(ioctls)
-#define IOCTL_FUNC_NAME 	DRM(ioctl)
-
-#define __HAVE_COUNTERS		5
-#define __HAVE_COUNTER6		_DRM_STAT_IRQ
-#define __HAVE_COUNTER7		_DRM_STAT_DMA
-#define __HAVE_COUNTER8		_DRM_STAT_PRIMARY
-#define __HAVE_COUNTER9		_DRM_STAT_SPECIAL
-#define __HAVE_COUNTER10	_DRM_STAT_MISSED
-
-
 #include "drm_auth.h"
 #include "drm_agpsupport.h"
 #include "drm_bufs.h"
@@ -70,25 +44,6 @@
 #include "drm_drawable.h"
 #include "drm_drv.h"
 
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init gamma_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", gamma_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/i810.h b/linux/i810.h
index 64309f59..ea1e7fe5 100644
--- a/linux/i810.h
+++ b/linux/i810.h
@@ -41,6 +41,47 @@
 #define __HAVE_MTRR		1
 #define __HAVE_CTX_BITMAP	1
 
+#define DRIVER_AUTHOR		"VA Linux Systems Inc."
+
+#define DRIVER_NAME		"i810"
+#define DRIVER_DESC		"Intel i810"
+#define DRIVER_DATE		"20020211"
+
+/* Interface history
+ *
+ * 1.1   - XFree86 4.1
+ * 1.2   - XvMC interfaces
+ *       - XFree86 4.2
+ * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
+ *       - Remove requirement for interrupt (leave stubs again)
+ */
+#define DRIVER_MAJOR		1
+#define DRIVER_MINOR		2
+#define DRIVER_PATCHLEVEL	1
+
+#define DRIVER_IOCTLS							    \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)]   = { i810_dma_init,    1, 1 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex,  1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)]  = { i810_clear_bufs,  1, 0 }, \
+      	[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)]  = { i810_flush_ioctl, 1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage,      1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf,      1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)]   = { i810_swap_bufs,   1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)]   = { i810_copybuf,     1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy,      1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0INFO)] = { i810_ov0_info,   1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_FSTATUS)] = { i810_fstatus,    1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0FLIP)] = { i810_ov0_flip,   1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_MC)]      = { i810_dma_mc,     1, 1 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I810_RSTATUS)] = { i810_rstatus,    1, 0 }
+
+
+#define __HAVE_COUNTERS         4
+#define __HAVE_COUNTER6         _DRM_STAT_IRQ
+#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
+#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
+#define __HAVE_COUNTER9         _DRM_STAT_DMA
+
 /* Driver customization:
  */
 #define __HAVE_RELEASE		1
diff --git a/linux/i810_drv.c b/linux/i810_drv.c
index d1a92e2a..439d7887 100644
--- a/linux/i810_drv.c
+++ b/linux/i810_drv.c
@@ -37,48 +37,6 @@
 #include "i810_drm.h"
 #include "i810_drv.h"
 
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"i810"
-#define DRIVER_DESC		"Intel i810"
-#define DRIVER_DATE		"20020211"
-
-/* Interface history
- *
- * 1.1   - XFree86 4.1
- * 1.2   - XvMC interfaces
- *       - XFree86 4.2
- * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
- *       - Remove requirement for interrupt (leave stubs again)
- */
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	1
-
-#define DRIVER_IOCTLS							    \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)]   = { i810_dma_init,    1, 1 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex,  1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)]  = { i810_clear_bufs,  1, 0 }, \
-      	[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)]  = { i810_flush_ioctl, 1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage,      1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf,      1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)]   = { i810_swap_bufs,   1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)]   = { i810_copybuf,     1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy,      1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0INFO)] = { i810_ov0_info,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_FSTATUS)] = { i810_fstatus,    1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_OV0FLIP)] = { i810_ov0_flip,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_MC)]      = { i810_dma_mc,     1, 1 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_RSTATUS)] = { i810_rstatus,    1, 0 }
-
-
-#define __HAVE_COUNTERS         4
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#define __HAVE_COUNTER9         _DRM_STAT_DMA
-
-
 #include "drm_agpsupport.h"
 #include "drm_auth.h"
 #include "drm_bufs.h"
@@ -87,25 +45,6 @@
 #include "drm_drawable.h"
 #include "drm_drv.h"
 
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init i810_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", i810_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/i830.h b/linux/i830.h
index fb7a0b32..794588b2 100644
--- a/linux/i830.h
+++ b/linux/i830.h
@@ -41,6 +41,33 @@
 #define __HAVE_MTRR		1
 #define __HAVE_CTX_BITMAP	1
 
+#define DRIVER_AUTHOR		"VA Linux Systems Inc."
+
+#define DRIVER_NAME		"i830"
+#define DRIVER_DESC		"Intel 830M"
+#define DRIVER_DATE		"20011004"
+
+#define DRIVER_MAJOR		1
+#define DRIVER_MINOR		2
+#define DRIVER_PATCHLEVEL	0
+
+#define DRIVER_IOCTLS							    \
+	[DRM_IOCTL_NR(DRM_IOCTL_I830_INIT)]   = { i830_dma_init,    1, 1 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_VERTEX)] = { i830_dma_vertex,  1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_CLEAR)]  = { i830_clear_bufs,  1, 0 }, \
+      	[DRM_IOCTL_NR(DRM_IOCTL_I830_FLUSH)]  = { i830_flush_ioctl, 1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETAGE)] = { i830_getage,      1, 0 }, \
+	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETBUF)] = { i830_getbuf,      1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_SWAP)]   = { i830_swap_bufs,   1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_COPY)]   = { i830_copybuf,     1, 0 }, \
+   	[DRM_IOCTL_NR(DRM_IOCTL_I830_DOCOPY)] = { i830_docopy,      1, 0 },
+
+#define __HAVE_COUNTERS         4
+#define __HAVE_COUNTER6         _DRM_STAT_IRQ
+#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
+#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
+#define __HAVE_COUNTER9         _DRM_STAT_DMA
+
 /* Driver customization:
  */
 #define __HAVE_RELEASE		1
diff --git a/linux/i830_drv.c b/linux/i830_drv.c
index ad31d1ef..b5efcef3 100644
--- a/linux/i830_drv.c
+++ b/linux/i830_drv.c
@@ -38,34 +38,6 @@
 #include "i830_drm.h"
 #include "i830_drv.h"
 
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"i830"
-#define DRIVER_DESC		"Intel 830M"
-#define DRIVER_DATE		"20011004"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-
-#define DRIVER_IOCTLS							    \
-	[DRM_IOCTL_NR(DRM_IOCTL_I830_INIT)]   = { i830_dma_init,    1, 1 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_VERTEX)] = { i830_dma_vertex,  1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_CLEAR)]  = { i830_clear_bufs,  1, 0 }, \
-      	[DRM_IOCTL_NR(DRM_IOCTL_I830_FLUSH)]  = { i830_flush_ioctl, 1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETAGE)] = { i830_getage,      1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETBUF)] = { i830_getbuf,      1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_SWAP)]   = { i830_swap_bufs,   1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_COPY)]   = { i830_copybuf,     1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_DOCOPY)] = { i830_docopy,      1, 0 },
-
-#define __HAVE_COUNTERS         4
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#define __HAVE_COUNTER9         _DRM_STAT_DMA
-
-
 #include "drm_agpsupport.h"
 #include "drm_auth.h"
 #include "drm_bufs.h"
@@ -74,25 +46,6 @@
 #include "drm_drawable.h"
 #include "drm_drv.h"
 
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init i830_options( char *str )
-{
-   DRM(parse_options)( str );
-   return 1;
-}
-
-__setup( DRIVER_NAME "=", i830_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/mga.h b/linux/mga.h
deleted file mode 100644
index 277aa202..00000000
--- a/linux/mga.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* mga.h -- Matrox G200/G400 DRM template customization -*- linux-c -*-
- * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __MGA_H__
-#define __MGA_H__
-
-/* This remains constant for all DRM template files.
- */
-#define DRM(x) mga_##x
-
-/* General customization:
- */
-#define __HAVE_AGP		1
-#define __MUST_HAVE_AGP		1
-#define __HAVE_MTRR		1
-#define __HAVE_CTX_BITMAP	1
-
-/* Driver customization:
- */
-#define DRIVER_PRETAKEDOWN() do {					\
-	if ( dev->dev_private ) mga_do_cleanup_dma( dev );		\
-} while (0)
-
-/* DMA customization:
- */
-#define __HAVE_DMA		1
-
-#define __HAVE_DMA_QUIESCENT	1
-#define DRIVER_DMA_QUIESCENT() do {					\
-	drm_mga_private_t *dev_priv = dev->dev_private;			\
-	return mga_do_wait_for_idle( dev_priv );			\
-} while (0)
-
-/* Buffer customization:
- */
-#define DRIVER_BUF_PRIV_T	drm_mga_buf_priv_t
-
-#define DRIVER_AGP_BUFFERS_MAP( dev )					\
-	((drm_mga_private_t *)((dev)->dev_private))->buffers
-
-#endif
diff --git a/linux/mga_dma.c b/linux/mga_dma.c
deleted file mode 100644
index 525975a8..00000000
--- a/linux/mga_dma.c
+++ /dev/null
@@ -1,815 +0,0 @@
-/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Keith Whitwell <keithw@valinux.com>
- *
- * Rewritten by:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-
-#include <linux/interrupt.h>	/* For task queue support */
-#include <linux/delay.h>
-
-#define MGA_DEFAULT_USEC_TIMEOUT	10000
-#define MGA_FREELIST_DEBUG		0
-
-
-/* ================================================================
- * Engine control
- */
-
-int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
-{
-	u32 status = 0;
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) {
-			MGA_WRITE8( MGA_CRTC_INDEX, 0 );
-			return 0;
-		}
-		udelay( 1 );
-	}
-
-#if MGA_DMA_DEBUG
-	DRM_ERROR( "failed!\n" );
-	DRM_INFO( "   status=0x%08x\n", status );
-#endif
-	return -EBUSY;
-}
-
-int mga_do_dma_idle( drm_mga_private_t *dev_priv )
-{
-	u32 status = 0;
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) return 0;
-		udelay( 1 );
-	}
-
-#if MGA_DMA_DEBUG
-	DRM_ERROR( "failed! status=0x%08x\n", status );
-#endif
-	return -EBUSY;
-}
-
-int mga_do_dma_reset( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The primary DMA stream should look like new right about now.
-	 */
-	primary->tail = 0;
-	primary->space = primary->size;
-	primary->last_flush = 0;
-
-	sarea_priv->last_wrap = 0;
-
-	/* FIXME: Reset counters, buffer ages etc...
-	 */
-
-	/* FIXME: What else do we need to reinitialize?  WARP stuff?
-	 */
-
-	return 0;
-}
-
-int mga_do_engine_reset( drm_mga_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* Okay, so we've completely screwed up and locked the engine.
-	 * How about we clean up after ourselves?
-	 */
-	MGA_WRITE( MGA_RST, MGA_SOFTRESET );
-	udelay( 15 );				/* Wait at least 10 usecs */
-	MGA_WRITE( MGA_RST, 0 );
-
-	/* Initialize the registers that get clobbered by the soft
-	 * reset.  Many of the core register values survive a reset,
-	 * but the drawing registers are basically all gone.
-	 *
-	 * 3D clients should probably die after calling this.  The X
-	 * server should reset the engine state to known values.
-	 */
-#if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status_page) |
-		   MGA_PRIMPTREN0 |
-		   MGA_PRIMPTREN1 );
-#endif
-
-	MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
-	MGA_WRITE( MGA_IEN,    MGA_SOFTRAPIEN );
-
-	/* The primary DMA stream should look like new right about now.
-	 */
-	mga_do_dma_reset( dev_priv );
-
-	/* This bad boy will never fail.
-	 */
-	return 0;
-}
-
-
-/* ================================================================
- * Primary DMA stream
- */
-
-void mga_do_dma_flush( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	u32 head, tail;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	if ( primary->tail == primary->last_flush ) {
-		DRM_DEBUG( "   bailing out...\n" );
-		return;
-	}
-
-	tail = primary->tail + dev_priv->primary->offset;
-
-	/* We need to pad the stream between flushes, as the card
-	 * actually (partially?) reads the first of these commands.
-	 * See page 4-16 in the G400 manual, middle of the page or so.
-	 */
-	BEGIN_DMA( 1 );
-
-	DMA_BLOCK( MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	ADVANCE_DMA();
-
-	primary->last_flush = primary->tail;
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-
-	if ( head <= tail ) {
-		primary->space = primary->size - primary->tail;
-	} else {
-		primary->space = head - tail;
-	}
-
-	DRM_DEBUG( "   head = 0x%06lx\n", head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06lx\n", tail - dev_priv->primary->offset );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
-
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	u32 head, tail;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	BEGIN_DMA_WRAP();
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	ADVANCE_DMA();
-
-	tail = primary->tail + dev_priv->primary->offset;
-
-	primary->tail = 0;
-	primary->last_flush = 0;
-	primary->last_wrap++;
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-
-	if ( head == dev_priv->primary->offset ) {
-		primary->space = primary->size;
-	} else {
-		primary->space = head - dev_priv->primary->offset;
-	}
-
-	DRM_DEBUG( "   head = 0x%06lx\n",
-		  head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06x\n", primary->tail );
-	DRM_DEBUG( "   wrap = %d\n", primary->last_wrap );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
-
-	set_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 head = dev_priv->primary->offset;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	sarea_priv->last_wrap++;
-	DRM_DEBUG( "   wrap = %d\n", sarea_priv->last_wrap );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
-
-	clear_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-
-/* ================================================================
- * Freelist management
- */
-
-#define MGA_BUFFER_USED		~0
-#define MGA_BUFFER_FREE		0
-
-#if MGA_FREELIST_DEBUG
-static void mga_freelist_print( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *entry;
-
-	DRM_INFO( "\n" );
-	DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
-		  dev_priv->sarea_priv->last_dispatch,
-		  (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
-				 dev_priv->primary->offset) );
-	DRM_INFO( "current freelist:\n" );
-
-	for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
-		DRM_INFO( "   %p   idx=%2d  age=0x%x 0x%06lx\n",
-			  entry, entry->buf->idx, entry->age.head,
-			  entry->age.head - dev_priv->primary->offset );
-	}
-	DRM_INFO( "\n" );
-}
-#endif
-
-static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_freelist_t *entry;
-	int i;
-	DRM_DEBUG( "%s: count=%d\n",
-		   __FUNCTION__, dma->buf_count );
-
-	dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
-		return -ENOMEM;
-
-	memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
-	SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
-
-		entry = DRM(alloc)( sizeof(drm_mga_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( entry == NULL )
-			return -ENOMEM;
-
-		memset( entry, 0, sizeof(drm_mga_freelist_t) );
-
-		entry->next = dev_priv->head->next;
-		entry->prev = dev_priv->head;
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
-		entry->buf = buf;
-
-		if ( dev_priv->head->next != NULL )
-			dev_priv->head->next->prev = entry;
-		if ( entry->next == NULL )
-			dev_priv->tail = entry;
-
-		buf_priv->list_entry = entry;
-		buf_priv->discard = 0;
-		buf_priv->dispatched = 0;
-
-		dev_priv->head->next = entry;
-	}
-
-	return 0;
-}
-
-static void mga_freelist_cleanup( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *entry;
-	drm_mga_freelist_t *next;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	entry = dev_priv->head;
-	while ( entry ) {
-		next = entry->next;
-		DRM(free)( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
-		entry = next;
-	}
-
-	dev_priv->head = dev_priv->tail = NULL;
-}
-
-#if 0
-/* FIXME: Still needed?
- */
-static void mga_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	int i;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
-		SET_AGE( &buf_priv->list_entry->age,
-			 MGA_BUFFER_FREE, 0 );
-	}
-}
-#endif
-
-static drm_buf_t *mga_freelist_get( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *next;
-	drm_mga_freelist_t *prev;
-	drm_mga_freelist_t *tail = dev_priv->tail;
-	u32 head, wrap;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-	wrap = dev_priv->sarea_priv->last_wrap;
-
-	DRM_DEBUG( "   tail=0x%06lx %d\n",
-		   tail->age.head ?
-		   tail->age.head - dev_priv->primary->offset : 0,
-		   tail->age.wrap );
-	DRM_DEBUG( "   head=0x%06lx %d\n",
-		   head - dev_priv->primary->offset, wrap );
-
-	if ( TEST_AGE( &tail->age, head, wrap ) ) {
-		prev = dev_priv->tail->prev;
-		next = dev_priv->tail;
-		prev->next = NULL;
-		next->prev = next->next = NULL;
-		dev_priv->tail = prev;
-		SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
-		return next->buf;
-	}
-
-	DRM_DEBUG( "returning NULL!\n" );
-	return NULL;
-}
-
-int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_freelist_t *head, *entry, *prev;
-
-	DRM_DEBUG( "%s: age=0x%06lx wrap=%d\n",
-		   __FUNCTION__,
-		   buf_priv->list_entry->age.head -
-		   dev_priv->primary->offset,
-		   buf_priv->list_entry->age.wrap );
-
-	entry = buf_priv->list_entry;
-	head = dev_priv->head;
-
-	if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
-		prev = dev_priv->tail;
-		prev->next = entry;
-		entry->prev = prev;
-		entry->next = NULL;
-	} else {
-		prev = head->next;
-		head->next = entry;
-		prev->prev = entry;
-		entry->prev = head;
-		entry->next = prev;
-	}
-
-	return 0;
-}
-
-
-/* ================================================================
- * DMA initialization, cleanup
- */
-
-static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
-{
-	drm_mga_private_t *dev_priv;
-	struct list_head *list;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
-	if ( !dev_priv )
-		return -ENOMEM;
-
-	memset( dev_priv, 0, sizeof(drm_mga_private_t) );
-
-	dev_priv->chipset = init->chipset;
-
-	dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
-
-	if ( init->sgram ) {
-		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
-	} else {
-		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
-	}
-	dev_priv->maccess	= init->maccess;
-
-	dev_priv->fb_cpp	= init->fb_cpp;
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	dev_priv->depth_cpp	= init->depth_cpp;
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-
-	/* FIXME: Need to support AGP textures...
-	 */
-	dev_priv->texture_offset = init->texture_offset[0];
-	dev_priv->texture_size = init->texture_size[0];
-
-	list_for_each( list, &dev->maplist->head ) {
-		drm_map_list_t *entry = (drm_map_list_t *)list;
-		if ( entry->map &&
-		     entry->map->type == _DRM_SHM &&
-		     (entry->map->flags & _DRM_CONTAINS_LOCK) ) {
-			dev_priv->sarea = entry->map;
- 			break;
- 		}
- 	}
-	if(!dev_priv->sarea) {
-		DRM_ERROR( "failed to find sarea!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR( "failed to find framebuffer!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR( "failed to find mmio region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->status, init->status_offset );
-	if(!dev_priv->status) {
-		DRM_ERROR( "failed to find status page!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-
-	DRM_FIND_MAP( dev_priv->warp, init->warp_offset );
-	if(!dev_priv->warp) {
-		DRM_ERROR( "failed to find warp microcode region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->primary, init->primary_offset );
-	if(!dev_priv->primary) {
-		DRM_ERROR( "failed to find primary dma region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR( "failed to find dma buffer region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -EINVAL;
-	}
-
-	dev_priv->sarea_priv =
-		(drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				    init->sarea_priv_offset);
-
-	DRM_IOREMAP( dev_priv->warp );
-	DRM_IOREMAP( dev_priv->primary );
-	DRM_IOREMAP( dev_priv->buffers );
-
-	if(!dev_priv->warp->handle ||
-	   !dev_priv->primary->handle ||
-	   !dev_priv->buffers->handle ) {
-		DRM_ERROR( "failed to ioremap agp regions!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -ENOMEM;
-	}
-
-	ret = mga_warp_install_microcode( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to install WARP ucode!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return ret;
-	}
-
-	ret = mga_warp_init( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to init WARP engine!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return ret;
-	}
-
-	dev_priv->prim.status = (u32 *)dev_priv->status->handle;
-
-	mga_do_wait_for_idle( dev_priv );
-
-	/* Init the primary DMA registers.
-	 */
-	MGA_WRITE( MGA_PRIMADDRESS,
-		   dev_priv->primary->offset | MGA_DMA_GENERAL );
-#if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status) |
-		   MGA_PRIMPTREN0 |	/* Soft trap, SECEND, SETUPEND */
-		   MGA_PRIMPTREN1 );	/* DWGSYNC */
-#endif
-
-	dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
-	dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
-			      + dev_priv->primary->size);
-	dev_priv->prim.size = dev_priv->primary->size;
-
-	dev_priv->prim.tail = 0;
-	dev_priv->prim.space = dev_priv->prim.size;
-	dev_priv->prim.wrapped = 0;
-
-	dev_priv->prim.last_flush = 0;
-	dev_priv->prim.last_wrap = 0;
-
-	dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
-
-	spin_lock_init( &dev_priv->prim.list_lock );
-
-	dev_priv->prim.status[0] = dev_priv->primary->offset;
-	dev_priv->prim.status[1] = 0;
-
-	dev_priv->sarea_priv->last_wrap = 0;
-	dev_priv->sarea_priv->last_frame.head = 0;
-	dev_priv->sarea_priv->last_frame.wrap = 0;
-
-	if ( mga_freelist_init( dev, dev_priv ) < 0 ) {
-		DRM_ERROR( "could not initialize freelist\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		return -ENOMEM;
-	}
-
-	/* Make dev_private visable to others. */
-	dev->dev_private = (void *)dev_priv;
-	return 0;
-}
-
-int mga_do_cleanup_dma( drm_device_t *dev )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev->dev_private ) {
-		drm_mga_private_t *dev_priv = dev->dev_private;
-
-		DRM_IOREMAPFREE( dev_priv->warp );
-		DRM_IOREMAPFREE( dev_priv->primary );
-		DRM_IOREMAPFREE( dev_priv->buffers );
-
-		if ( dev_priv->head != NULL ) {
-			mga_freelist_cleanup( dev );
-		}
-
-		DRM(free)( dev->dev_private, sizeof(drm_mga_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int mga_dma_init( struct inode *inode, struct file *filp,
-		  unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_init_t init;
-
-	if ( copy_from_user( &init, (drm_mga_init_t *)arg, sizeof(init) ) )
-		return -EFAULT;
-
-	switch ( init.func ) {
-	case MGA_INIT_DMA:
-		return mga_do_init_dma( dev, &init );
-	case MGA_CLEANUP_DMA:
-		return mga_do_cleanup_dma( dev );
-	}
-
-	return -EINVAL;
-}
-
-
-/* ================================================================
- * Primary DMA stream management
- */
-
-int mga_dma_flush( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-	drm_lock_t lock;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &lock, (drm_lock_t *)arg, sizeof(lock) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: %s%s%s\n",
-		   __FUNCTION__,
-		   (lock.flags & _DRM_LOCK_FLUSH) ?	"flush, " : "",
-		   (lock.flags & _DRM_LOCK_FLUSH_ALL) ?	"flush all, " : "",
-		   (lock.flags & _DRM_LOCK_QUIESCENT) ?	"idle, " : "" );
-
-	WRAP_WAIT_WITH_RETURN( dev_priv );
-
-	if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
-		mga_do_dma_flush( dev_priv );
-	}
-
-	if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
-#if MGA_DMA_DEBUG
-		int ret = mga_do_wait_for_idle( dev_priv );
-		if ( ret < 0 )
-			DRM_INFO( __FUNCTION__": -EBUSY\n" );
-		return ret;
-#else
-		return mga_do_wait_for_idle( dev_priv );
-#endif
-	} else {
-		return 0;
-	}
-}
-
-int mga_dma_reset( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return mga_do_dma_reset( dev_priv );
-}
-
-
-/* ================================================================
- * DMA buffer management
- */
-
-static int mga_dma_get_buffers( drm_device_t *dev, drm_dma_t *d )
-{
-	drm_buf_t *buf;
-	int i;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = mga_freelist_get( dev );
-		if ( !buf ) return -EAGAIN;
-
-		buf->pid = current->pid;
-
-		if ( copy_to_user( &d->request_indices[i],
-				   &buf->idx, sizeof(buf->idx) ) )
-			return -EFAULT;
-		if ( copy_to_user( &d->request_sizes[i],
-				   &buf->total, sizeof(buf->total) ) )
-			return -EFAULT;
-
-		d->granted_count++;
-	}
-	return 0;
-}
-
-int mga_dma_buffers( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-	drm_dma_t d;
-	int ret = 0;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
-		return -EFAULT;
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   current->pid, d.send_count );
-		return -EINVAL;
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   current->pid, d.request_count, dma->buf_count );
-		return -EINVAL;
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		ret = mga_dma_get_buffers( dev, &d );
-	}
-
-	if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
-		return -EFAULT;
-
-	return ret;
-}
diff --git a/linux/mga_drm.h b/linux/mga_drm.h
deleted file mode 100644
index 8f56beed..00000000
--- a/linux/mga_drm.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
- * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Keith Whitwell <keithw@valinux.com>
- *
- * Rewritten by:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __MGA_DRM_H__
-#define __MGA_DRM_H__
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (mga_sarea.h)
- */
-
-#ifndef __MGA_SAREA_DEFINES__
-#define __MGA_SAREA_DEFINES__
-
-/* WARP pipe flags
- */
-#define MGA_F			0x1		/* fog */
-#define MGA_A			0x2		/* alpha */
-#define MGA_S			0x4		/* specular */
-#define MGA_T2			0x8		/* multitexture */
-
-#define MGA_WARP_TGZ		0
-#define MGA_WARP_TGZF		(MGA_F)
-#define MGA_WARP_TGZA		(MGA_A)
-#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
-#define MGA_WARP_TGZS		(MGA_S)
-#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
-#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
-#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
-#define MGA_WARP_T2GZ		(MGA_T2)
-#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
-#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
-#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
-#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
-#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
-#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
-#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
-
-#define MGA_MAX_G200_PIPES	8		/* no multitex */
-#define MGA_MAX_G400_PIPES	16
-#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
-#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */
-
-#define MGA_CARD_TYPE_G200	1
-#define MGA_CARD_TYPE_G400	2
-
-
-#define MGA_FRONT		0x1
-#define MGA_BACK		0x2
-#define MGA_DEPTH		0x4
-
-/* What needs to be changed for the current vertex dma buffer?
- */
-#define MGA_UPLOAD_CONTEXT	0x1
-#define MGA_UPLOAD_TEX0		0x2
-#define MGA_UPLOAD_TEX1		0x4
-#define MGA_UPLOAD_PIPE		0x8
-#define MGA_UPLOAD_TEX0IMAGE	0x10 /* handled client-side */
-#define MGA_UPLOAD_TEX1IMAGE	0x20 /* handled client-side */
-#define MGA_UPLOAD_2D		0x40
-#define MGA_WAIT_AGE		0x80 /* handled client-side */
-#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
-#if 0
-#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
-					 quiescent */
-#endif
-
-/* 32 buffers of 64k each, total 2 meg.
- */
-#define MGA_BUFFER_SIZE		(1 << 16)
-#define MGA_NUM_BUFFERS		128
-
-/* Keep these small for testing.
- */
-#define MGA_NR_SAREA_CLIPRECTS	8
-
-/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
- * regions, subject to a minimum region size of (1<<16) == 64k.
- *
- * Clients may subdivide regions internally, but when sharing between
- * clients, the region size is the minimum granularity.
- */
-
-#define MGA_CARD_HEAP			0
-#define MGA_AGP_HEAP			1
-#define MGA_NR_TEX_HEAPS		2
-#define MGA_NR_TEX_REGIONS		16
-#define MGA_LOG_MIN_TEX_REGION_SIZE	16
-
-#endif /* __MGA_SAREA_DEFINES__ */
-
-
-/* Setup registers for 3D context
- */
-typedef struct {
-	unsigned int dstorg;
-	unsigned int maccess;
-	unsigned int plnwt;
-	unsigned int dwgctl;
-	unsigned int alphactrl;
-	unsigned int fogcolor;
-	unsigned int wflag;
-	unsigned int tdualstage0;
-	unsigned int tdualstage1;
-	unsigned int fcol;
-	unsigned int stencil;
-	unsigned int stencilctl;
-} drm_mga_context_regs_t;
-
-/* Setup registers for 2D, X server
- */
-typedef struct {
-	unsigned int pitch;
-} drm_mga_server_regs_t;
-
-/* Setup registers for each texture unit
- */
-typedef struct {
-	unsigned int texctl;
-	unsigned int texctl2;
-	unsigned int texfilter;
-	unsigned int texbordercol;
-	unsigned int texorg;
-	unsigned int texwidth;
-	unsigned int texheight;
-	unsigned int texorg1;
-	unsigned int texorg2;
-	unsigned int texorg3;
-	unsigned int texorg4;
-} drm_mga_texture_regs_t;
-
-/* General aging mechanism
- */
-typedef struct {
-	unsigned int head;		/* Position of head pointer          */
-	unsigned int wrap;		/* Primary DMA wrap count            */
-} drm_mga_age_t;
-
-typedef struct _drm_mga_sarea {
-	/* The channel for communication of state information to the kernel
-	 * on firing a vertex dma buffer.
-	 */
-   	drm_mga_context_regs_t context_state;
-   	drm_mga_server_regs_t server_state;
-   	drm_mga_texture_regs_t tex_state[2];
-   	unsigned int warp_pipe;
-   	unsigned int dirty;
-   	unsigned int vertsize;
-
-	/* The current cliprects, or a subset thereof.
-	 */
-   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
-   	unsigned int nbox;
-
-	/* Information about the most recently used 3d drawable.  The
-	 * client fills in the req_* fields, the server fills in the
-	 * exported_ fields and puts the cliprects into boxes, above.
-	 *
-	 * The client clears the exported_drawable field before
-	 * clobbering the boxes data.
-	 */
-        unsigned int req_drawable;	 /* the X drawable id */
-	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */
-
-        unsigned int exported_drawable;
-	unsigned int exported_index;
-        unsigned int exported_stamp;
-        unsigned int exported_buffers;
-        unsigned int exported_nfront;
-        unsigned int exported_nback;
-	int exported_back_x, exported_front_x, exported_w;
-	int exported_back_y, exported_front_y, exported_h;
-   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
-
-	/* Counters for aging textures and for client-side throttling.
-	 */
-	unsigned int status[4];
-	unsigned int last_wrap;
-
-	drm_mga_age_t last_frame;
-        unsigned int last_enqueue;	/* last time a buffer was enqueued */
-	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
-	unsigned int last_quiescent;     /*  */
-
-	/* LRU lists for texture memory in agp space and on the card.
-	 */
-	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
-	unsigned int texAge[MGA_NR_TEX_HEAPS];
-
-	/* Mechanism to validate card state.
-	 */
-   	int ctxOwner;
-} drm_mga_sarea_t;
-
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmMga.h)
- */
-
-/* MGA specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
-#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
-#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
-#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
-#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
-#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
-#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
-#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
-#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
-
-typedef struct _drm_mga_warp_index {
-   	int installed;
-   	unsigned long phys_addr;
-   	int size;
-} drm_mga_warp_index_t;
-
-typedef struct drm_mga_init {
-   	enum {
-	   	MGA_INIT_DMA    = 0x01,
-	       	MGA_CLEANUP_DMA = 0x02
-	} func;
-
-   	unsigned long sarea_priv_offset;
-
-	int chipset;
-   	int sgram;
-
-	unsigned int maccess;
-
-   	unsigned int fb_cpp;
-	unsigned int front_offset, front_pitch;
-   	unsigned int back_offset, back_pitch;
-
-   	unsigned int depth_cpp;
-   	unsigned int depth_offset, depth_pitch;
-
-   	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
-   	unsigned int texture_size[MGA_NR_TEX_HEAPS];
-
-	unsigned long fb_offset;
-	unsigned long mmio_offset;
-	unsigned long status_offset;
-	unsigned long warp_offset;
-	unsigned long primary_offset;
-	unsigned long buffers_offset;
-} drm_mga_init_t;
-
-typedef struct drm_mga_fullscreen {
-	enum {
-		MGA_INIT_FULLSCREEN    = 0x01,
-		MGA_CLEANUP_FULLSCREEN = 0x02
-	} func;
-} drm_mga_fullscreen_t;
-
-typedef struct drm_mga_clear {
-	unsigned int flags;
-	unsigned int clear_color;
-	unsigned int clear_depth;
-	unsigned int color_mask;
-	unsigned int depth_mask;
-} drm_mga_clear_t;
-
-typedef struct drm_mga_vertex {
-   	int idx;			/* buffer to queue */
-	int used;			/* bytes in use */
-	int discard;			/* client finished with buffer?  */
-} drm_mga_vertex_t;
-
-typedef struct drm_mga_indices {
-   	int idx;			/* buffer to queue */
-	unsigned int start;
-	unsigned int end;
-	int discard;			/* client finished with buffer?  */
-} drm_mga_indices_t;
-
-typedef struct drm_mga_iload {
-	int idx;
-	unsigned int dstorg;
-	unsigned int length;
-} drm_mga_iload_t;
-
-typedef struct _drm_mga_blit {
-	unsigned int planemask;
-	unsigned int srcorg;
-	unsigned int dstorg;
-	int src_pitch, dst_pitch;
-	int delta_sx, delta_sy;
-	int delta_dx, delta_dy;
-	int height, ydir;		/* flip image vertically */
-	int source_pitch, dest_pitch;
-} drm_mga_blit_t;
-
-#endif
diff --git a/linux/mga_drv.c b/linux/mga_drv.c
index cc8d728e..f0d4935d 100644
--- a/linux/mga_drv.c
+++ b/linux/mga_drv.c
@@ -35,36 +35,6 @@
 #include "drm.h"
 #include "mga_drm.h"
 #include "mga_drv.h"
-
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"mga"
-#define DRIVER_DESC		"Matrox G200/G400"
-#define DRIVER_DATE		"20010321"
-
-#define DRIVER_MAJOR		3
-#define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	2
-
-#define DRIVER_IOCTLS							   \
-	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	      = { mga_dma_buffers, 1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)]    = { mga_dma_init,    1, 1 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)]   = { mga_dma_flush,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)]   = { mga_dma_reset,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)]    = { mga_dma_swap,    1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)]   = { mga_dma_clear,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)]  = { mga_dma_vertex,  1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)]   = { mga_dma_iload,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)]    = { mga_dma_blit,    1, 0 },
-
-
-#define __HAVE_COUNTERS         3
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-
-
 #include "drm_agpsupport.h"
 #include "drm_auth.h"
 #include "drm_bufs.h"
@@ -72,27 +42,6 @@
 #include "drm_dma.h"
 #include "drm_drawable.h"
 #include "drm_drv.h"
-
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init mga_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", mga_options );
-#endif
-
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/mga_drv.h b/linux/mga_drv.h
deleted file mode 100644
index ba2602e7..00000000
--- a/linux/mga_drv.h
+++ /dev/null
@@ -1,643 +0,0 @@
-/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __MGA_DRV_H__
-#define __MGA_DRV_H__
-
-typedef struct drm_mga_primary_buffer {
-	u8 *start;
-	u8 *end;
-	int size;
-
-	u32 tail;
-	int space;
-	volatile int wrapped;
-
-	volatile u32 *status;
-
-	u32 last_flush;
-	u32 last_wrap;
-
-	u32 high_mark;
-
-	spinlock_t list_lock;
-} drm_mga_primary_buffer_t;
-
-typedef struct drm_mga_freelist {
-   	struct drm_mga_freelist *next;
-   	struct drm_mga_freelist *prev;
-	drm_mga_age_t age;
-   	drm_buf_t *buf;
-} drm_mga_freelist_t;
-
-typedef struct {
-   	drm_mga_freelist_t *list_entry;
-	int discard;
-	int dispatched;
-} drm_mga_buf_priv_t;
-
-typedef struct drm_mga_private {
-	drm_mga_primary_buffer_t prim;
-	drm_mga_sarea_t *sarea_priv;
-
-   	drm_mga_freelist_t *head;
-   	drm_mga_freelist_t *tail;
-
-	unsigned int warp_pipe;
-	unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
-
-	int chipset;
-	int usec_timeout;
-
-	u32 clear_cmd;
-	u32 maccess;
-
-	unsigned int fb_cpp;
-	unsigned int front_offset;
-	unsigned int front_pitch;
-	unsigned int back_offset;
-	unsigned int back_pitch;
-
-	unsigned int depth_cpp;
-	unsigned int depth_offset;
-	unsigned int depth_pitch;
-
-	unsigned int texture_offset;
-	unsigned int texture_size;
-
-	drm_map_t *sarea;
-	drm_map_t *fb;
-	drm_map_t *mmio;
-	drm_map_t *status;
-	drm_map_t *warp;
-	drm_map_t *primary;
-	drm_map_t *buffers;
-	drm_map_t *agp_textures;
-} drm_mga_private_t;
-
-				/* mga_dma.c */
-extern int mga_dma_init( struct inode *inode, struct file *filp,
-			 unsigned int cmd, unsigned long arg );
-extern int mga_dma_flush( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int mga_dma_reset( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int mga_dma_buffers( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-
-extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
-extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
-extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
-extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
-extern int mga_do_cleanup_dma( drm_device_t *dev );
-
-extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
-extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
-extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
-
-extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
-
-				/* mga_state.c */
-extern int  mga_dma_clear( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int  mga_dma_swap( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int  mga_dma_vertex( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int  mga_dma_indices( struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg );
-extern int  mga_dma_iload( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int  mga_dma_blit( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-
-				/* mga_warp.c */
-extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
-extern int mga_warp_init( drm_mga_private_t *dev_priv );
-
-#define mga_flush_write_combine()	mb()
-
-
-#define MGA_BASE( reg )		((unsigned long)(dev_priv->mmio->handle))
-#define MGA_ADDR( reg )		(MGA_BASE(reg) + reg)
-
-#define MGA_DEREF( reg )	*(volatile u32 *)MGA_ADDR( reg )
-#define MGA_DEREF8( reg )	*(volatile u8 *)MGA_ADDR( reg )
-
-#ifdef __alpha__
-#define MGA_READ( reg )		(_MGA_READ((u32 *)MGA_ADDR(reg)))
-#define MGA_WRITE( reg, val )	do { wmb(); MGA_DEREF( reg ) = val; } while (0)
-#define MGA_WRITE8( reg, val )  do { wmb(); MGA_DEREF8( reg ) = val; } while (0)
-
-static inline u32 _MGA_READ(u32 *addr)
-{
-	mb();
-	return *(volatile u32 *)addr;
-}
-
-#else
-#define MGA_READ( reg )		MGA_DEREF( reg )
-#define MGA_WRITE( reg, val )	do { MGA_DEREF( reg ) = val; } while (0)
-#define MGA_WRITE8( reg, val )  do { MGA_DEREF8( reg ) = val; } while (0)
-#endif
-
-#define DWGREG0 	0x1c00
-#define DWGREG0_END 	0x1dff
-#define DWGREG1		0x2c00
-#define DWGREG1_END	0x2dff
-
-#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
-#define DMAREG0(r)	(u8)((r - DWGREG0) >> 2)
-#define DMAREG1(r)	(u8)(((r - DWGREG1) >> 2) | 0x80)
-#define DMAREG(r)	(ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
-
-
-
-/* ================================================================
- * Helper macross...
- */
-
-#define MGA_EMIT_STATE( dev_priv, dirty )				\
-do {									\
-	if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {			\
-		if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {	\
-			mga_g400_emit_state( dev_priv );		\
-		} else {						\
-			mga_g200_emit_state( dev_priv );		\
-		}							\
-	}								\
-} while (0)
-
-#define LOCK_TEST_WITH_RETURN( dev )					\
-do {									\
-	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
-	     dev->lock.pid != current->pid ) {				\
-		DRM_ERROR( "%s called without lock held\n",		\
-			   __FUNCTION__ );				\
-		return -EINVAL;						\
-	}								\
-} while (0)
-
-#define WRAP_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
-		if ( mga_is_idle( dev_priv ) ) {			\
-			mga_do_dma_wrap_end( dev_priv );		\
-		} else if ( dev_priv->prim.space <			\
-			    dev_priv->prim.high_mark ) {		\
-			if ( MGA_DMA_DEBUG )				\
-				DRM_INFO( __FUNCTION__": wrap...\n" );	\
-			return -EBUSY;					\
-		}							\
-	}								\
-} while (0)
-
-#define WRAP_WAIT_WITH_RETURN( dev_priv )				\
-do {									\
-	if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {			\
-		if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {		\
-			if ( MGA_DMA_DEBUG )				\
-				DRM_INFO( __FUNCTION__": wrap...\n" );	\
-			return -EBUSY;					\
-		}							\
-		mga_do_dma_wrap_end( dev_priv );			\
-	}								\
-} while (0)
-
-
-/* ================================================================
- * Primary DMA command stream
- */
-
-#define MGA_VERBOSE	0
-
-#define DMA_LOCALS	unsigned int write; volatile u8 *prim;
-
-#define DMA_BLOCK_SIZE	(5 * sizeof(u32))
-
-#define BEGIN_DMA( n )							\
-do {									\
-	if ( MGA_VERBOSE ) {						\
-		DRM_INFO( "BEGIN_DMA( %d ) in %s\n",			\
-			  (n), __FUNCTION__ );				\
-		DRM_INFO( "   space=0x%x req=0x%x\n",			\
-			  dev_priv->prim.space, (n) * DMA_BLOCK_SIZE );	\
-	}								\
-	prim = dev_priv->prim.start;					\
-	write = dev_priv->prim.tail;					\
-} while (0)
-
-#define BEGIN_DMA_WRAP()						\
-do {									\
-	if ( MGA_VERBOSE ) {						\
-		DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ );	\
-		DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );	\
-	}								\
-	prim = dev_priv->prim.start;					\
-	write = dev_priv->prim.tail;					\
-} while (0)
-
-#define ADVANCE_DMA()							\
-do {									\
-	dev_priv->prim.tail = write;					\
-	if ( MGA_VERBOSE ) {						\
-		DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",	\
-			  write, dev_priv->prim.space );		\
-	}								\
-} while (0)
-
-#define FLUSH_DMA()							\
-do {									\
-	if ( 0 ) {							\
-		DRM_INFO( __FUNCTION__ ":\n" );				\
-		DRM_INFO( "   tail=0x%06x head=0x%06lx\n",		\
-			  dev_priv->prim.tail,				\
-			  MGA_READ( MGA_PRIMADDRESS ) -			\
-			  dev_priv->primary->offset );			\
-	}								\
-	if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {		\
-		if ( dev_priv->prim.space <				\
-		     dev_priv->prim.high_mark ) {			\
-			mga_do_dma_wrap_start( dev_priv );		\
-		} else {						\
-			mga_do_dma_flush( dev_priv );			\
-		}							\
-	}								\
-} while (0)
-
-/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
- */
-#define DMA_WRITE( offset, val )					\
-do {									\
-	if ( MGA_VERBOSE ) {						\
-		DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04x\n",		\
-			  (u32)(val), write + (offset) * sizeof(u32) );	\
-	}								\
-	*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val;	\
-} while (0)
-
-#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )	\
-do {									\
-	DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |				\
-		       (DMAREG( reg1 ) << 8) |				\
-		       (DMAREG( reg2 ) << 16) |				\
-		       (DMAREG( reg3 ) << 24)) );			\
-	DMA_WRITE( 1, val0 );						\
-	DMA_WRITE( 2, val1 );						\
-	DMA_WRITE( 3, val2 );						\
-	DMA_WRITE( 4, val3 );						\
-	write += DMA_BLOCK_SIZE;					\
-} while (0)
-
-
-/* Buffer aging via primary DMA stream head pointer.
- */
-
-#define SET_AGE( age, h, w )						\
-do {									\
-	(age)->head = h;						\
-	(age)->wrap = w;						\
-} while (0)
-
-#define TEST_AGE( age, h, w )		( (age)->wrap < w ||		\
-					  ( (age)->wrap == w &&		\
-					    (age)->head < h ) )
-
-#define AGE_BUFFER( buf_priv )						\
-do {									\
-	drm_mga_freelist_t *entry = (buf_priv)->list_entry;		\
-	if ( (buf_priv)->dispatched ) {					\
-		entry->age.head = (dev_priv->prim.tail +		\
-				   dev_priv->primary->offset);		\
-		entry->age.wrap = dev_priv->sarea_priv->last_wrap;	\
-	} else {							\
-		entry->age.head = 0;					\
-		entry->age.wrap = 0;					\
-	}								\
-} while (0)
-
-
-#define MGA_ENGINE_IDLE_MASK		(MGA_SOFTRAPEN |		\
-					 MGA_DWGENGSTS |		\
-					 MGA_ENDPRDMASTS)
-#define MGA_DMA_IDLE_MASK		(MGA_SOFTRAPEN |		\
-					 MGA_ENDPRDMASTS)
-
-#define MGA_DMA_DEBUG			0
-
-
-
-/* A reduced set of the mga registers.
- */
-#define MGA_CRTC_INDEX			0x1fd4
-
-#define MGA_ALPHACTRL 			0x2c7c
-#define MGA_AR0 			0x1c60
-#define MGA_AR1 			0x1c64
-#define MGA_AR2 			0x1c68
-#define MGA_AR3 			0x1c6c
-#define MGA_AR4 			0x1c70
-#define MGA_AR5 			0x1c74
-#define MGA_AR6 			0x1c78
-
-#define MGA_CXBNDRY			0x1c80
-#define MGA_CXLEFT 			0x1ca0
-#define MGA_CXRIGHT			0x1ca4
-
-#define MGA_DMAPAD 			0x1c54
-#define MGA_DSTORG 			0x2cb8
-#define MGA_DWGCTL 			0x1c00
-#	define MGA_OPCOD_MASK			(15 << 0)
-#	define MGA_OPCOD_TRAP			(4 << 0)
-#	define MGA_OPCOD_TEXTURE_TRAP		(6 << 0)
-#	define MGA_OPCOD_BITBLT			(8 << 0)
-#	define MGA_OPCOD_ILOAD			(9 << 0)
-#	define MGA_ATYPE_MASK			(7 << 4)
-#	define MGA_ATYPE_RPL			(0 << 4)
-#	define MGA_ATYPE_RSTR			(1 << 4)
-#	define MGA_ATYPE_ZI			(3 << 4)
-#	define MGA_ATYPE_BLK			(4 << 4)
-#	define MGA_ATYPE_I			(7 << 4)
-#	define MGA_LINEAR			(1 << 7)
-#	define MGA_ZMODE_MASK			(7 << 8)
-#	define MGA_ZMODE_NOZCMP			(0 << 8)
-#	define MGA_ZMODE_ZE			(2 << 8)
-#	define MGA_ZMODE_ZNE			(3 << 8)
-#	define MGA_ZMODE_ZLT			(4 << 8)
-#	define MGA_ZMODE_ZLTE			(5 << 8)
-#	define MGA_ZMODE_ZGT			(6 << 8)
-#	define MGA_ZMODE_ZGTE			(7 << 8)
-#	define MGA_SOLID			(1 << 11)
-#	define MGA_ARZERO			(1 << 12)
-#	define MGA_SGNZERO			(1 << 13)
-#	define MGA_SHIFTZERO			(1 << 14)
-#	define MGA_BOP_MASK			(15 << 16)
-#	define MGA_BOP_ZERO			(0 << 16)
-#	define MGA_BOP_DST			(10 << 16)
-#	define MGA_BOP_SRC			(12 << 16)
-#	define MGA_BOP_ONE			(15 << 16)
-#	define MGA_TRANS_SHIFT			20
-#	define MGA_TRANS_MASK			(15 << 20)
-#	define MGA_BLTMOD_MASK			(15 << 25)
-#	define MGA_BLTMOD_BMONOLEF		(0 << 25)
-#	define MGA_BLTMOD_BMONOWF		(4 << 25)
-#	define MGA_BLTMOD_PLAN			(1 << 25)
-#	define MGA_BLTMOD_BFCOL			(2 << 25)
-#	define MGA_BLTMOD_BU32BGR		(3 << 25)
-#	define MGA_BLTMOD_BU32RGB		(7 << 25)
-#	define MGA_BLTMOD_BU24BGR		(11 << 25)
-#	define MGA_BLTMOD_BU24RGB		(15 << 25)
-#	define MGA_PATTERN			(1 << 29)
-#	define MGA_TRANSC			(1 << 30)
-#	define MGA_CLIPDIS			(1 << 31)
-#define MGA_DWGSYNC			0x2c4c
-
-#define MGA_FCOL 			0x1c24
-#define MGA_FIFOSTATUS 			0x1e10
-#define MGA_FOGCOL 			0x1cf4
-#define MGA_FXBNDRY			0x1c84
-#define MGA_FXLEFT 			0x1ca8
-#define MGA_FXRIGHT			0x1cac
-
-#define MGA_ICLEAR 			0x1e18
-#	define MGA_SOFTRAPICLR			(1 << 0)
-#define MGA_IEN 			0x1e1c
-#	define MGA_SOFTRAPIEN			(1 << 0)
-
-#define MGA_LEN 			0x1c5c
-
-#define MGA_MACCESS			0x1c04
-
-#define MGA_PITCH 			0x1c8c
-#define MGA_PLNWT 			0x1c1c
-#define MGA_PRIMADDRESS 		0x1e58
-#	define MGA_DMA_GENERAL			(0 << 0)
-#	define MGA_DMA_BLIT			(1 << 0)
-#	define MGA_DMA_VECTOR			(2 << 0)
-#	define MGA_DMA_VERTEX			(3 << 0)
-#define MGA_PRIMEND			0x1e5c
-#	define MGA_PRIMNOSTART			(1 << 0)
-#	define MGA_PAGPXFER			(1 << 1)
-#define MGA_PRIMPTR			0x1e50
-#	define MGA_PRIMPTREN0			(1 << 0)
-#	define MGA_PRIMPTREN1			(1 << 1)
-
-#define MGA_RST 			0x1e40
-#	define MGA_SOFTRESET			(1 << 0)
-#	define MGA_SOFTEXTRST			(1 << 1)
-
-#define MGA_SECADDRESS 			0x2c40
-#define MGA_SECEND 			0x2c44
-#define MGA_SETUPADDRESS 		0x2cd0
-#define MGA_SETUPEND 			0x2cd4
-#define MGA_SGN				0x1c58
-#define MGA_SOFTRAP			0x2c48
-#define MGA_SRCORG 			0x2cb4
-#	define MGA_SRMMAP_MASK			(1 << 0)
-#	define MGA_SRCMAP_FB			(0 << 0)
-#	define MGA_SRCMAP_SYSMEM		(1 << 0)
-#	define MGA_SRCACC_MASK			(1 << 1)
-#	define MGA_SRCACC_PCI			(0 << 1)
-#	define MGA_SRCACC_AGP			(1 << 1)
-#define MGA_STATUS 			0x1e14
-#	define MGA_SOFTRAPEN			(1 << 0)
-#	define MGA_DWGENGSTS			(1 << 16)
-#	define MGA_ENDPRDMASTS			(1 << 17)
-#define MGA_STENCIL			0x2cc8
-#define MGA_STENCILCTL 			0x2ccc
-
-#define MGA_TDUALSTAGE0 		0x2cf8
-#define MGA_TDUALSTAGE1 		0x2cfc
-#define MGA_TEXBORDERCOL 		0x2c5c
-#define MGA_TEXCTL 			0x2c30
-#define MGA_TEXCTL2			0x2c3c
-#	define MGA_DUALTEX			(1 << 7)
-#	define MGA_G400_TC2_MAGIC		(1 << 15)
-#	define MGA_MAP1_ENABLE			(1 << 31)
-#define MGA_TEXFILTER 			0x2c58
-#define MGA_TEXHEIGHT 			0x2c2c
-#define MGA_TEXORG 			0x2c24
-#	define MGA_TEXORGMAP_MASK		(1 << 0)
-#	define MGA_TEXORGMAP_FB			(0 << 0)
-#	define MGA_TEXORGMAP_SYSMEM		(1 << 0)
-#	define MGA_TEXORGACC_MASK		(1 << 1)
-#	define MGA_TEXORGACC_PCI		(0 << 1)
-#	define MGA_TEXORGACC_AGP		(1 << 1)
-#define MGA_TEXORG1			0x2ca4
-#define MGA_TEXORG2			0x2ca8
-#define MGA_TEXORG3			0x2cac
-#define MGA_TEXORG4			0x2cb0
-#define MGA_TEXTRANS 			0x2c34
-#define MGA_TEXTRANSHIGH 		0x2c38
-#define MGA_TEXWIDTH 			0x2c28
-
-#define MGA_WACCEPTSEQ 			0x1dd4
-#define MGA_WCODEADDR 			0x1e6c
-#define MGA_WFLAG 			0x1dc4
-#define MGA_WFLAG1 			0x1de0
-#define MGA_WFLAGNB			0x1e64
-#define MGA_WFLAGNB1 			0x1e08
-#define MGA_WGETMSB			0x1dc8
-#define MGA_WIADDR 			0x1dc0
-#define MGA_WIADDR2			0x1dd8
-#	define MGA_WMODE_SUSPEND		(0 << 0)
-#	define MGA_WMODE_RESUME			(1 << 0)
-#	define MGA_WMODE_JUMP			(2 << 0)
-#	define MGA_WMODE_START			(3 << 0)
-#	define MGA_WAGP_ENABLE			(1 << 2)
-#define MGA_WMISC 			0x1e70
-#	define MGA_WUCODECACHE_ENABLE		(1 << 0)
-#	define MGA_WMASTER_ENABLE		(1 << 1)
-#	define MGA_WCACHEFLUSH_ENABLE		(1 << 3)
-#define MGA_WVRTXSZ			0x1dcc
-
-#define MGA_YBOT 			0x1c9c
-#define MGA_YDST 			0x1c90
-#define MGA_YDSTLEN			0x1c88
-#define MGA_YDSTORG			0x1c94
-#define MGA_YTOP 			0x1c98
-
-#define MGA_ZORG 			0x1c0c
-
-/* This finishes the current batch of commands
- */
-#define MGA_EXEC 			0x0100
-
-/* Warp registers
- */
-#define MGA_WR0				0x2d00
-#define MGA_WR1				0x2d04
-#define MGA_WR2				0x2d08
-#define MGA_WR3				0x2d0c
-#define MGA_WR4				0x2d10
-#define MGA_WR5				0x2d14
-#define MGA_WR6				0x2d18
-#define MGA_WR7				0x2d1c
-#define MGA_WR8				0x2d20
-#define MGA_WR9				0x2d24
-#define MGA_WR10			0x2d28
-#define MGA_WR11			0x2d2c
-#define MGA_WR12			0x2d30
-#define MGA_WR13			0x2d34
-#define MGA_WR14			0x2d38
-#define MGA_WR15			0x2d3c
-#define MGA_WR16			0x2d40
-#define MGA_WR17			0x2d44
-#define MGA_WR18			0x2d48
-#define MGA_WR19			0x2d4c
-#define MGA_WR20			0x2d50
-#define MGA_WR21			0x2d54
-#define MGA_WR22			0x2d58
-#define MGA_WR23			0x2d5c
-#define MGA_WR24			0x2d60
-#define MGA_WR25			0x2d64
-#define MGA_WR26			0x2d68
-#define MGA_WR27			0x2d6c
-#define MGA_WR28			0x2d70
-#define MGA_WR29			0x2d74
-#define MGA_WR30			0x2d78
-#define MGA_WR31			0x2d7c
-#define MGA_WR32			0x2d80
-#define MGA_WR33			0x2d84
-#define MGA_WR34			0x2d88
-#define MGA_WR35			0x2d8c
-#define MGA_WR36			0x2d90
-#define MGA_WR37			0x2d94
-#define MGA_WR38			0x2d98
-#define MGA_WR39			0x2d9c
-#define MGA_WR40			0x2da0
-#define MGA_WR41			0x2da4
-#define MGA_WR42			0x2da8
-#define MGA_WR43			0x2dac
-#define MGA_WR44			0x2db0
-#define MGA_WR45			0x2db4
-#define MGA_WR46			0x2db8
-#define MGA_WR47			0x2dbc
-#define MGA_WR48			0x2dc0
-#define MGA_WR49			0x2dc4
-#define MGA_WR50			0x2dc8
-#define MGA_WR51			0x2dcc
-#define MGA_WR52			0x2dd0
-#define MGA_WR53			0x2dd4
-#define MGA_WR54			0x2dd8
-#define MGA_WR55			0x2ddc
-#define MGA_WR56			0x2de0
-#define MGA_WR57			0x2de4
-#define MGA_WR58			0x2de8
-#define MGA_WR59			0x2dec
-#define MGA_WR60			0x2df0
-#define MGA_WR61			0x2df4
-#define MGA_WR62			0x2df8
-#define MGA_WR63			0x2dfc
-#	define MGA_G400_WR_MAGIC		(1 << 6)
-#	define MGA_G400_WR56_MAGIC		0x46480000	/* 12800.0f */
-
-
-#define MGA_ILOAD_ALIGN		64
-#define MGA_ILOAD_MASK		(MGA_ILOAD_ALIGN - 1)
-
-#define MGA_DWGCTL_FLUSH	(MGA_OPCOD_TEXTURE_TRAP |		\
-				 MGA_ATYPE_I |				\
-				 MGA_ZMODE_NOZCMP |			\
-				 MGA_ARZERO |				\
-				 MGA_SGNZERO |				\
-				 MGA_BOP_SRC |				\
-				 (15 << MGA_TRANS_SHIFT))
-
-#define MGA_DWGCTL_CLEAR	(MGA_OPCOD_TRAP |			\
-				 MGA_ZMODE_NOZCMP |			\
-				 MGA_SOLID |				\
-				 MGA_ARZERO |				\
-				 MGA_SGNZERO |				\
-				 MGA_SHIFTZERO |			\
-				 MGA_BOP_SRC |				\
-				 (0 << MGA_TRANS_SHIFT) |		\
-				 MGA_BLTMOD_BMONOLEF |			\
-				 MGA_TRANSC |				\
-				 MGA_CLIPDIS)
-
-#define MGA_DWGCTL_COPY		(MGA_OPCOD_BITBLT |			\
-				 MGA_ATYPE_RPL |			\
-				 MGA_SGNZERO |				\
-				 MGA_SHIFTZERO |			\
-				 MGA_BOP_SRC |				\
-				 (0 << MGA_TRANS_SHIFT) |		\
-				 MGA_BLTMOD_BFCOL |			\
-				 MGA_CLIPDIS)
-
-/* Simple idle test.
- */
-static inline int mga_is_idle( drm_mga_private_t *dev_priv )
-{
-	u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-	return ( status == MGA_ENDPRDMASTS );
-}
-
-#endif
diff --git a/linux/mga_state.c b/linux/mga_state.c
deleted file mode 100644
index 17cbc855..00000000
--- a/linux/mga_state.c
+++ /dev/null
@@ -1,1097 +0,0 @@
-/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
- * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Keith Whitwell <keithw@valinux.com>
- *
- * Rewritten by:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "drm.h"
-
-
-/* ================================================================
- * DMA hardware state programming functions
- */
-
-static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
-				drm_clip_rect_t *box )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	unsigned int pitch = dev_priv->front_pitch;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 2 );
-
-	/* Force reset of DWGCTL on G400 (eliminates clip disable bit).
-	 */
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		DMA_BLOCK( MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000,
-			   MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000 );
-	}
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_CXBNDRY,	(box->x2 << 16) | box->x1,
-		   MGA_YTOP,	box->y1 * pitch,
-		   MGA_YBOT,	box->y2 * pitch );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g200_emit_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 3 );
-
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
-
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
-
-	DMA_BLOCK( MGA_FCOL,		ctx->fcol,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g400_emit_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 4 );
-
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
-
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
-
-	DMA_BLOCK( MGA_WFLAG1,		ctx->wflag,
-		   MGA_TDUALSTAGE0,	ctx->tdualstage0,
-		   MGA_TDUALSTAGE1,	ctx->tdualstage1,
-		   MGA_FCOL,		ctx->fcol );
-
-	DMA_BLOCK( MGA_STENCIL,		ctx->stencil,
-		   MGA_STENCILCTL,	ctx->stencilctl,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	DMA_LOCALS;
-
-	BEGIN_DMA( 4 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR24,		tex->texwidth );
-
-	DMA_BLOCK( MGA_WR34,		tex->texheight,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
-/*  	       tex->texctl, tex->texctl2); */
-
-	BEGIN_DMA( 6 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
-
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		MGA_G400_WR_MAGIC );
-
-	DMA_BLOCK( MGA_WR60,		MGA_G400_WR_MAGIC,
-		   MGA_WR54,		tex->texwidth | MGA_G400_WR_MAGIC,
-		   MGA_WR62,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_DMAPAD,		0x00000000 );
-
-	DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
-/*  	       tex->texctl, tex->texctl2); */
-
-	BEGIN_DMA( 5 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		(tex->texctl2 |
-					 MGA_MAP1_ENABLE |
-					 MGA_G400_TC2_MAGIC),
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
-
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		tex->texwidth | MGA_G400_WR_MAGIC );
-
-	DMA_BLOCK( MGA_WR60,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int pipe = sarea_priv->warp_pipe;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 3 );
-
-	DMA_BLOCK( MGA_WIADDR,	MGA_WMODE_SUSPEND,
-		   MGA_WVRTXSZ,	0x00000007,
-		   MGA_WFLAG,	0x00000000,
-		   MGA_WR24,	0x00000000 );
-
-	DMA_BLOCK( MGA_WR25,	0x00000100,
-		   MGA_WR34,	0x00000000,
-		   MGA_WR42,	0x0000ffff,
-		   MGA_WR60,	0x0000ffff );
-
-	/* Padding required to to hardware bug.
-	 */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
-
-	ADVANCE_DMA();
-}
-
-static inline void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int pipe = sarea_priv->warp_pipe;
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_pipe %x\n", pipe); */
-
-	BEGIN_DMA( 10 );
-
-	DMA_BLOCK( MGA_WIADDR2,	MGA_WMODE_SUSPEND,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	if ( pipe & MGA_T2 ) {
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001e09,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
-
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x1e000000 );
-	} else {
-		if ( dev_priv->warp_pipe & MGA_T2 ) {
-			/* Flush the WARP pipe */
-			DMA_BLOCK( MGA_YDST,		0x00000000,
-				   MGA_FXLEFT,		0x00000000,
-				   MGA_FXRIGHT,		0x00000001,
-				   MGA_DWGCTL,		MGA_DWGCTL_FLUSH );
-
-			DMA_BLOCK( MGA_LEN + MGA_EXEC,	0x00000001,
-				   MGA_DWGSYNC,		0x00007000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_LEN + MGA_EXEC,	0x00000000 );
-
-			DMA_BLOCK( MGA_TEXCTL2,		(MGA_DUALTEX |
-							 MGA_G400_TC2_MAGIC),
-				   MGA_LEN + MGA_EXEC,	0x00000000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_DMAPAD,		0x00000000 );
-		}
-
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001807,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
-
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x18000000 );
-	}
-
-	DMA_BLOCK( MGA_WFLAG,	0x00000000,
-		   MGA_WFLAG1,	0x00000000,
-		   MGA_WR56,	MGA_G400_WR56_MAGIC,
-		   MGA_DMAPAD,	0x00000000 );
-
-	DMA_BLOCK( MGA_WR49,	0x00000000,		/* tex0              */
-		   MGA_WR57,	0x00000000,		/* tex0              */
-		   MGA_WR53,	0x00000000,		/* tex1              */
-		   MGA_WR61,	0x00000000 );		/* tex1              */
-
-	DMA_BLOCK( MGA_WR54,	MGA_G400_WR_MAGIC,	/* tex0 width        */
-		   MGA_WR62,	MGA_G400_WR_MAGIC,	/* tex0 height       */
-		   MGA_WR52,	MGA_G400_WR_MAGIC,	/* tex1 width        */
-		   MGA_WR60,	MGA_G400_WR_MAGIC );	/* tex1 height       */
-
-	/* Padding required to to hardware bug */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR2,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
-
-	ADVANCE_DMA();
-}
-
-static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g200_emit_pipe( dev_priv );
-		dev_priv->warp_pipe = sarea_priv->warp_pipe;
-	}
-
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g200_emit_context( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g200_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
-	}
-}
-
-static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-	int multitex = sarea_priv->warp_pipe & MGA_T2;
-
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g400_emit_pipe( dev_priv );
-		dev_priv->warp_pipe = sarea_priv->warp_pipe;
-	}
-
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g400_emit_context( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g400_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
-	}
-
-	if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
-		mga_g400_emit_tex1( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
-	}
-}
-
-
-/* ================================================================
- * SAREA state verification
- */
-
-/* Disallow all write destinations except the front and backbuffer.
- */
-static int mga_verify_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-
-	if ( ctx->dstorg != dev_priv->front_offset &&
-	     ctx->dstorg != dev_priv->back_offset ) {
-		DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
-			   ctx->dstorg, dev_priv->front_offset,
-			   dev_priv->back_offset );
-		ctx->dstorg = 0;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/* Disallow texture reads from PCI space.
- */
-static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
-	unsigned int org;
-
-	org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
-
-	if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
-		DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
-			   tex->texorg, unit );
-		tex->texorg = 0;
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int mga_verify_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-	int ret = 0;
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	if ( dirty & MGA_UPLOAD_CONTEXT )
-		ret |= mga_verify_context( dev_priv );
-
-	if ( dirty & MGA_UPLOAD_TEX0 )
-		ret |= mga_verify_tex( dev_priv, 0 );
-
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		if ( dirty & MGA_UPLOAD_TEX1 )
-			ret |= mga_verify_tex( dev_priv, 1 );
-
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
-	} else {
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
-	}
-
-	return ( ret == 0 );
-}
-
-static int mga_verify_iload( drm_mga_private_t *dev_priv,
-			     unsigned int dstorg, unsigned int length )
-{
-	if ( dstorg < dev_priv->texture_offset ||
-	     dstorg + length > (dev_priv->texture_offset +
-				dev_priv->texture_size) ) {
-		DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
-		return -EINVAL;
-	}
-
-	if ( length & MGA_ILOAD_MASK ) {
-		DRM_ERROR( "*** bad iload length: 0x%x\n",
-			   length & MGA_ILOAD_MASK );
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int mga_verify_blit( drm_mga_private_t *dev_priv,
-			    unsigned int srcorg, unsigned int dstorg )
-{
-	if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
-	     (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
-		DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
-			   srcorg, dstorg );
-		return -EINVAL;
-	}
-	return 0;
-}
-
-
-/* ================================================================
- *
- */
-
-static void mga_dma_dispatch_clear( drm_device_t *dev,
-				    drm_mga_clear_t *clear )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	int i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	BEGIN_DMA( 1 );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	ADVANCE_DMA();
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		drm_clip_rect_t *box = &pbox[i];
-		u32 height = box->y2 - box->y1;
-
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
-
-		if ( clear->flags & MGA_FRONT ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->front_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-
-		if ( clear->flags & MGA_BACK ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->back_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-		if ( clear->flags & MGA_DEPTH ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->depth_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_depth,
-				   MGA_DSTORG,	dev_priv->depth_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-	}
-
-	BEGIN_DMA( 1 );
-
-	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_swap( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	int i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	sarea_priv->last_frame.head = dev_priv->prim.tail;
-	sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
-
-	BEGIN_DMA( 4 + nbox );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DSTORG,	dev_priv->front_offset,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_SRCORG,	dev_priv->back_offset,
-		   MGA_AR5,	dev_priv->front_pitch );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		drm_clip_rect_t *box = &pbox[i];
-		u32 height = box->y2 - box->y1;
-		u32 start = box->y1 * dev_priv->front_pitch;
-
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
-
-		DMA_BLOCK( MGA_AR0,	start + box->x2 - 1,
-			   MGA_AR3,	start + box->x1,
-			   MGA_FXBNDRY,	((box->x2 - 1) << 16) | box->x1,
-			   MGA_YDSTLEN + MGA_EXEC,
-					(box->y1 << 16) | height );
-	}
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-
-	FLUSH_DMA();
-
-	DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
-}
-
-static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 address = (u32) buf->bus_address;
-	u32 length = (u32) buf->used;
-	int i = 0;
-	DMA_LOCALS;
-	DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
-
-	if ( buf->used ) {
-		buf_priv->dispatched = 1;
-
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
-
-		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
-			}
-
-			BEGIN_DMA( 1 );
-
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SECADDRESS,	(address |
-							 MGA_DMA_VERTEX),
-				   MGA_SECEND,		((address + length) |
-							 MGA_PAGPXFER) );
-
-			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
-		buf->pending = 0;
-		buf->used = 0;
-		buf_priv->dispatched = 0;
-
-		mga_freelist_put( dev, buf );
-	}
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
-				      unsigned int start, unsigned int end )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 address = (u32) buf->bus_address;
-	int i = 0;
-	DMA_LOCALS;
-	DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
-
-	if ( start != end ) {
-		buf_priv->dispatched = 1;
-
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
-
-		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
-			}
-
-			BEGIN_DMA( 1 );
-
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SETUPADDRESS,	address + start,
-				   MGA_SETUPEND,	((address + end) |
-							 MGA_PAGPXFER) );
-
-			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
-		buf->pending = 0;
-		buf->used = 0;
-		buf_priv->dispatched = 0;
-
-		mga_freelist_put( dev, buf );
-	}
-
-	FLUSH_DMA();
-}
-
-/* This copies a 64 byte aligned agp region to the frambuffer with a
- * standard blit, the ioctl needs to do checking.
- */
-static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
-				    unsigned int dstorg, unsigned int length )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
-	u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
-	u32 y2;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s: buf=%d used=%d\n",
-		   __FUNCTION__, buf->idx, buf->used );
-
-	y2 = length / 64;
-
-	BEGIN_DMA( 5 );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DSTORG,	dstorg,
-		   MGA_MACCESS,	0x00000000,
-		   MGA_SRCORG,	srcorg,
-		   MGA_AR5,	64 );
-
-	DMA_BLOCK( MGA_PITCH,	64,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
-
-	DMA_BLOCK( MGA_AR0,	63,
-		   MGA_AR3,	0,
-		   MGA_FXBNDRY,	(63 << 16) | 0,
-		   MGA_YDSTLEN + MGA_EXEC, y2 );
-
-	DMA_BLOCK( MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	ADVANCE_DMA();
-
-	AGE_BUFFER( buf_priv );
-
-	buf->pending = 0;
-	buf->used = 0;
-	buf_priv->dispatched = 0;
-
-	mga_freelist_put( dev, buf );
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_blit( drm_device_t *dev,
-				   drm_mga_blit_t *blit )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	u32 scandir = 0, i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	BEGIN_DMA( 4 + nbox );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DWGCTL,	MGA_DWGCTL_COPY,
-		   MGA_PLNWT,	blit->planemask,
-		   MGA_SRCORG,	blit->srcorg,
-		   MGA_DSTORG,	blit->dstorg );
-
-	DMA_BLOCK( MGA_SGN,	scandir,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_AR5,	blit->ydir * blit->src_pitch,
-		   MGA_PITCH,	blit->dst_pitch );
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int srcx = pbox[i].x1 + blit->delta_sx;
-		int srcy = pbox[i].y1 + blit->delta_sy;
-		int dstx = pbox[i].x1 + blit->delta_dx;
-		int dsty = pbox[i].y1 + blit->delta_dy;
-		int h = pbox[i].y2 - pbox[i].y1;
-		int w = pbox[i].x2 - pbox[i].x1 - 1;
-		int start;
-
-		if ( blit->ydir == -1 ) {
-			srcy = blit->height - srcy - 1;
-		}
-
-		start = srcy * blit->src_pitch + srcx;
-
-		DMA_BLOCK( MGA_AR0,	start + w,
-			   MGA_AR3,	start,
-			   MGA_FXBNDRY,	((dstx + w) << 16) | (dstx & 0xffff),
-			   MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
-	}
-
-	/* Do something to flush AGP?
-	 */
-
-	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-}
-
-
-/* ================================================================
- *
- */
-
-int mga_dma_clear( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_clear_t clear;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &clear, (drm_mga_clear_t *) arg, sizeof(clear) ) )
-		return -EFAULT;
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_clear( dev, &clear );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_swap( struct inode *inode, struct file *filp,
-		  unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_swap( dev );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_vertex( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_vertex_t vertex;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &vertex,
-			     (drm_mga_vertex_t *)arg,
-			     sizeof(vertex) ) )
-		return -EFAULT;
-
-        if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	buf->used = vertex.used;
-	buf_priv->discard = vertex.discard;
-
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( vertex.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
-			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
-		}
-		return -EINVAL;
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_vertex( dev, buf );
-
-	return 0;
-}
-
-int mga_dma_indices( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_indices_t indices;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &indices,
-			     (drm_mga_indices_t *)arg,
-			     sizeof(indices) ) )
-		return -EFAULT;
-
-        if(indices.idx < 0 || indices.idx > dma->buf_count) return -EINVAL;
-
-	buf = dma->buflist[indices.idx];
-	buf_priv = buf->dev_private;
-
-	buf_priv->discard = indices.discard;
-
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( indices.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
-			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
-		}
-		return -EINVAL;
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
-
-	return 0;
-}
-
-int mga_dma_iload( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_iload_t iload;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &iload, (drm_mga_iload_t *)arg, sizeof(iload) ) )
-		return -EFAULT;
-
-#if 0
-	if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {
-		if ( MGA_DMA_DEBUG )
-			DRM_INFO( __FUNCTION__": -EBUSY\n" );
-		return -EBUSY;
-	}
-#endif
-        if(iload.idx < 0 || iload.idx > dma->buf_count) return -EINVAL;
-
-	buf = dma->buflist[iload.idx];
-	buf_priv = buf->dev_private;
-
-	if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
-		mga_freelist_put( dev, buf );
-		return -EINVAL;
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_blit( struct inode *inode, struct file *filp,
-		  unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_blit_t blit;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &blit, (drm_mga_blit_t *)arg, sizeof(blit) ) )
-		return -EFAULT;
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
-		return -EINVAL;
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_blit( dev, &blit );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
diff --git a/linux/mga_ucode.h b/linux/mga_ucode.h
deleted file mode 100644
index fa0f82ec..00000000
--- a/linux/mga_ucode.h
+++ /dev/null
@@ -1,11645 +0,0 @@
-/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*-
- * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com
- *
- * Copyright 1999 Matrox Graphics Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
- * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Kernel-based WARP engine management:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-/*
- * WARP pipes are named according to the functions they perform, where:
- *
- *   - T stands for computation of texture stage 0
- *   - T2 stands for computation of both texture stage 0 and texture stage 1
- *   - G stands for computation of triangle intensity (Gouraud interpolation)
- *   - Z stands for computation of Z buffer interpolation
- *   - S stands for computation of specular highlight
- *   - A stands for computation of the alpha channel
- *   - F stands for computation of vertex fog interpolation
- */
-
-static unsigned char warp_g200_tgz[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x72, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x60, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x03, 0x80, 0x0A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x57, 0x39, 0x20, 0xE9,
-0x28, 0x19, 0x60, 0xEC,
-
-0x2B, 0x32, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0xB3, 0x05,
-0x00, 0xE0,
-0x16, 0x28, 0x20, 0xE9,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x2B, 0x20, 0xE9,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x85, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x84, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x82, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x7F, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgza[] = {
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x7D, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x6B, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2D, 0x44, 0x4C, 0xB6,
-0x25, 0x44, 0x54, 0xB6,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x07, 0xC0, 0x44, 0xC6,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x1F, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x3F, 0x3D, 0x5D, 0x9F,
-0x00, 0xE0,
-0x07, 0x20,
-
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
-
-0xB3, 0x05,
-0x00, 0xE0,
-0x00, 0x80, 0x00, 0xE8,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0x26, 0x1F, 0xDF,
-0x9D, 0x1F, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x9E, 0x3F, 0x4F, 0xE9,
-
-0x07, 0x07, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x9C, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x7A, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x79, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x77, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x74, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzaf[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x83, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x6F, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
-
-0x2D, 0x44, 0x4C, 0xB6,
-0x25, 0x44, 0x54, 0xB6,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x07, 0xC0, 0x44, 0xC6,
-
-0x17, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x2D, 0x20,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x1F, 0x62, 0x57, 0x9F,
-0x00, 0xE0,
-0x07, 0x20,
-
-0x3F, 0x3D, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
-
-0xB3, 0x05,
-0x00, 0xE0,
-0x17, 0x26, 0x17, 0xDF,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x35, 0x17, 0x4F, 0xE9,
-
-0x1F, 0x26, 0x1F, 0xDF,
-0x9D, 0x1F, 0x4F, 0xE9,
-
-0x9E, 0x3F, 0x4F, 0xE9,
-0x39, 0x37, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x17, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0x07, 0x07, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x9C, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x74, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x73, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x71, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6E, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzf[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x7F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x6B, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x17, 0x50, 0x56, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x00, 0x80, 0x00, 0xE8,
-0x28, 0x19, 0x60, 0xEC,
-
-0xB3, 0x05,
-0x00, 0xE0,
-0x00, 0x80, 0x00, 0xE8,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x17, 0x26, 0x17, 0xDF,
-0x35, 0x17, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x39, 0x37, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x17, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x78, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x77, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x75, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x72, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzs[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x8B, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x77, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2D, 0x21, 0x1A, 0xB0,
-0x25, 0x21, 0x31, 0xB0,
-
-0x0D, 0x21, 0x1A, 0xB2,
-0x05, 0x21, 0x31, 0xB2,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x05, 0x20,
-0x0D, 0x20,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x2F, 0xC0, 0x21, 0xC0,
-
-0x16, 0x42, 0x56, 0x9F,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x21, 0x31, 0xB4,
-0x2D, 0x21, 0x1A, 0xB4,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0x05,
-0x00, 0xE0,
-0x28, 0x19, 0x60, 0xEC,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
-
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
-
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
-
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
-
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x8F, 0x20,
-
-0xA5, 0x37, 0x4F, 0xE9,
-0x0F, 0x17, 0x0F, 0xAF,
-
-0x06, 0xC0, 0x21, 0xC4,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0xA3, 0x80, 0x4F, 0xE9,
-
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
-
-0xA1, 0x1F, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x06, 0x06, 0x1F, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x6C, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6B, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x69, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsa[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x8F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x7B, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2D, 0x21, 0x1A, 0xB0,
-0x25, 0x21, 0x31, 0xB0,
-
-0x0D, 0x21, 0x1A, 0xB2,
-0x05, 0x21, 0x31, 0xB2,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x05, 0x20,
-0x0D, 0x20,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x2F, 0xC0, 0x21, 0xC0,
-
-0x16, 0x42, 0x56, 0x9F,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x21, 0x31, 0xB4,
-0x2D, 0x21, 0x1A, 0xB4,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0x05,
-0x00, 0xE0,
-0x28, 0x19, 0x60, 0xEC,
-
-0x0D, 0x44, 0x4C, 0xB6,
-0x05, 0x44, 0x54, 0xB6,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
-
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
-
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
-
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
-
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
-
-0x0D, 0x20,
-0x05, 0x20,
-0x00, 0x80, 0x00, 0xE8,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x0F, 0x20,
-
-0x17, 0x50, 0x56, 0x9F,
-0xA5, 0x37, 0x4F, 0xE9,
-
-0x06, 0xC0, 0x21, 0xC4,
-0x0F, 0x17, 0x0F, 0xAF,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2F, 0xC0, 0x44, 0xC6,
-0xA3, 0x80, 0x4F, 0xE9,
-
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
-
-0x17, 0x26, 0x17, 0xDF,
-0x9D, 0x17, 0x4F, 0xE9,
-
-0xA1, 0x1F, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
-
-0x06, 0x06, 0x1F, 0xAF,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x9E, 0x37, 0x4F, 0xE9,
-0x2F, 0x17, 0x2F, 0xAF,
-
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x9C, 0x80, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x68, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x67, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x65, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x62, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsaf[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x94, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x80, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2D, 0x21, 0x1A, 0xB0,
-0x25, 0x21, 0x31, 0xB0,
-
-0x0D, 0x21, 0x1A, 0xB2,
-0x05, 0x21, 0x31, 0xB2,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x05, 0x20,
-0x0D, 0x20,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x2F, 0xC0, 0x21, 0xC0,
-
-0x16, 0x42, 0x56, 0x9F,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x21, 0x31, 0xB4,
-0x2D, 0x21, 0x1A, 0xB4,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0x05,
-0x00, 0xE0,
-0x28, 0x19, 0x60, 0xEC,
-
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
-
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
-
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
-
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
-
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
-
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
-
-0x2D, 0x44, 0x4C, 0xB6,
-0x25, 0x44, 0x54, 0xB6,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x0F, 0x20,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x07, 0xC0, 0x44, 0xC6,
-
-0x17, 0x50, 0x56, 0x9F,
-0xA5, 0x37, 0x4F, 0xE9,
-
-0x06, 0xC0, 0x21, 0xC4,
-0x0F, 0x17, 0x0F, 0xAF,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x3E, 0x3D, 0x5D, 0x9F,
-0x00, 0xE0,
-0x07, 0x20,
-
-0x2F, 0x20,
-0x00, 0xE0,
-0xA3, 0x0F, 0x4F, 0xE9,
-
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
-
-0x17, 0x26, 0x17, 0xDF,
-0xA1, 0x1F, 0x4F, 0xE9,
-
-0x1E, 0x26, 0x1E, 0xDF,
-0x9D, 0x1E, 0x4F, 0xE9,
-
-0x35, 0x17, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
-
-0x06, 0x06, 0x1F, 0xAF,
-0x39, 0x37, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x17, 0xAF,
-0x07, 0x07, 0x1E, 0xAF,
-
-0xA0, 0x80, 0x4F, 0xE9,
-0x9E, 0x3E, 0x4F, 0xE9,
-
-0x31, 0x80, 0x4F, 0xE9,
-0x9C, 0x80, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x63, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x62, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x60, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x5D, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g200_tgzsf[] = {
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x98, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x81, 0x04,
-0x89, 0x04,
-0x01, 0x04,
-0x09, 0x04,
-
-0xC9, 0x41, 0xC0, 0xEC,
-0x11, 0x04,
-0x00, 0xE0,
-
-0x41, 0xCC, 0x41, 0xCD,
-0x49, 0xCC, 0x49, 0xCD,
-
-0xD1, 0x41, 0xC0, 0xEC,
-0x51, 0xCC, 0x51, 0xCD,
-
-0x80, 0x04,
-0x10, 0x04,
-0x08, 0x04,
-0x00, 0xE0,
-
-0x00, 0xCC, 0xC0, 0xCD,
-0xD1, 0x49, 0xC0, 0xEC,
-
-0x8A, 0x1F, 0x20, 0xE9,
-0x8B, 0x3F, 0x20, 0xE9,
-
-0x41, 0x3C, 0x41, 0xAD,
-0x49, 0x3C, 0x49, 0xAD,
-
-0x10, 0xCC, 0x10, 0xCD,
-0x08, 0xCC, 0x08, 0xCD,
-
-0xB9, 0x41, 0x49, 0xBB,
-0x1F, 0xF0, 0x41, 0xCD,
-
-0x51, 0x3C, 0x51, 0xAD,
-0x00, 0x98, 0x80, 0xE9,
-
-0x8F, 0x80, 0x07, 0xEA,
-0x24, 0x1F, 0x20, 0xE9,
-
-0x21, 0x45, 0x80, 0xE8,
-0x1A, 0x4D, 0x80, 0xE8,
-
-0x31, 0x55, 0x80, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0x41, 0x49, 0xBD,
-0x1D, 0x41, 0x51, 0xBD,
-
-0x2E, 0x41, 0x2A, 0xB8,
-0x34, 0x53, 0xA0, 0xE8,
-
-0x15, 0x30,
-0x1D, 0x30,
-0x58, 0xE3,
-0x00, 0xE0,
-
-0xB5, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x24, 0x43, 0xA0, 0xE8,
-0x2C, 0x4B, 0xA0, 0xE8,
-
-0x15, 0x72,
-0x09, 0xE3,
-0x00, 0xE0,
-0x1D, 0x72,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0x97, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x6C, 0x64, 0xC8, 0xEC,
-0x98, 0xE1,
-0xB5, 0x05,
-
-0xBD, 0x05,
-0x2E, 0x30,
-0x32, 0xC0, 0xA0, 0xE8,
-
-0x33, 0xC0, 0xA0, 0xE8,
-0x74, 0x64, 0xC8, 0xEC,
-
-0x40, 0x3C, 0x40, 0xAD,
-0x32, 0x6A,
-0x2A, 0x30,
-
-0x20, 0x73,
-0x33, 0x6A,
-0x00, 0xE0,
-0x28, 0x73,
-
-0x1C, 0x72,
-0x83, 0xE2,
-0x7B, 0x80, 0x15, 0xEA,
-
-0xB8, 0x3D, 0x28, 0xDF,
-0x30, 0x35, 0x20, 0xDF,
-
-0x40, 0x30,
-0x00, 0xE0,
-0xCC, 0xE2,
-0x64, 0x72,
-
-0x25, 0x42, 0x52, 0xBF,
-0x2D, 0x42, 0x4A, 0xBF,
-
-0x30, 0x2E, 0x30, 0xDF,
-0x38, 0x2E, 0x38, 0xDF,
-
-0x18, 0x1D, 0x45, 0xE9,
-0x1E, 0x15, 0x45, 0xE9,
-
-0x2B, 0x49, 0x51, 0xBD,
-0x00, 0xE0,
-0x1F, 0x73,
-
-0x38, 0x38, 0x40, 0xAF,
-0x30, 0x30, 0x40, 0xAF,
-
-0x24, 0x1F, 0x24, 0xDF,
-0x1D, 0x32, 0x20, 0xE9,
-
-0x2C, 0x1F, 0x2C, 0xDF,
-0x1A, 0x33, 0x20, 0xE9,
-
-0xB0, 0x10,
-0x08, 0xE3,
-0x40, 0x10,
-0xB8, 0x10,
-
-0x26, 0xF0, 0x30, 0xCD,
-0x2F, 0xF0, 0x38, 0xCD,
-
-0x2B, 0x80, 0x20, 0xE9,
-0x2A, 0x80, 0x20, 0xE9,
-
-0xA6, 0x20,
-0x88, 0xE2,
-0x00, 0xE0,
-0xAF, 0x20,
-
-0x28, 0x2A, 0x26, 0xAF,
-0x20, 0x2A, 0xC0, 0xAF,
-
-0x34, 0x1F, 0x34, 0xDF,
-0x46, 0x24, 0x46, 0xDF,
-
-0x28, 0x30, 0x80, 0xBF,
-0x20, 0x38, 0x80, 0xBF,
-
-0x47, 0x24, 0x47, 0xDF,
-0x4E, 0x2C, 0x4E, 0xDF,
-
-0x4F, 0x2C, 0x4F, 0xDF,
-0x56, 0x34, 0x56, 0xDF,
-
-0x28, 0x15, 0x28, 0xDF,
-0x20, 0x1D, 0x20, 0xDF,
-
-0x57, 0x34, 0x57, 0xDF,
-0x00, 0xE0,
-0x1D, 0x05,
-
-0x04, 0x80, 0x10, 0xEA,
-0x89, 0xE2,
-0x2B, 0x30,
-
-0x3F, 0xC1, 0x1D, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x68,
-0xBF, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x20, 0xC0, 0x20, 0xAF,
-0x28, 0x05,
-0x97, 0x74,
-
-0x00, 0xE0,
-0x2A, 0x10,
-0x16, 0xC0, 0x20, 0xE9,
-
-0x04, 0x80, 0x10, 0xEA,
-0x8C, 0xE2,
-0x95, 0x05,
-
-0x28, 0xC1, 0x28, 0xAD,
-0x1F, 0xC1, 0x15, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA8, 0x67,
-0x9F, 0x6B,
-0x00, 0x80, 0x00, 0xE8,
-
-0x28, 0xC0, 0x28, 0xAD,
-0x1D, 0x25,
-0x20, 0x05,
-
-0x28, 0x32, 0x80, 0xAD,
-0x40, 0x2A, 0x40, 0xBD,
-
-0x1C, 0x80, 0x20, 0xE9,
-0x20, 0x33, 0x20, 0xAD,
-
-0x20, 0x73,
-0x00, 0xE0,
-0xB6, 0x49, 0x51, 0xBB,
-
-0x26, 0x2F, 0xB0, 0xE8,
-0x19, 0x20, 0x20, 0xE9,
-
-0x35, 0x20, 0x35, 0xDF,
-0x3D, 0x20, 0x3D, 0xDF,
-
-0x15, 0x20, 0x15, 0xDF,
-0x1D, 0x20, 0x1D, 0xDF,
-
-0x26, 0xD0, 0x26, 0xCD,
-0x29, 0x49, 0x2A, 0xB8,
-
-0x26, 0x40, 0x80, 0xBD,
-0x3B, 0x48, 0x50, 0xBD,
-
-0x3E, 0x54, 0x57, 0x9F,
-0x00, 0xE0,
-0x82, 0xE1,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x26, 0x30,
-0x29, 0x30,
-0x48, 0x3C, 0x48, 0xAD,
-
-0x2B, 0x72,
-0xC2, 0xE1,
-0x2C, 0xC0, 0x44, 0xC2,
-
-0x05, 0x24, 0x34, 0xBF,
-0x0D, 0x24, 0x2C, 0xBF,
-
-0x2D, 0x46, 0x4E, 0xBF,
-0x25, 0x46, 0x56, 0xBF,
-
-0x20, 0x1D, 0x6F, 0x8F,
-0x32, 0x3E, 0x5F, 0xE9,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x30,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x33, 0x1E, 0x5F, 0xE9,
-
-0x05, 0x44, 0x54, 0xB2,
-0x0D, 0x44, 0x4C, 0xB2,
-
-0x19, 0xC0, 0xB0, 0xE8,
-0x34, 0xC0, 0x44, 0xC4,
-
-0x33, 0x73,
-0x00, 0xE0,
-0x3E, 0x62, 0x57, 0x9F,
-
-0x1E, 0xAF, 0x59, 0x9F,
-0x00, 0xE0,
-0x0D, 0x20,
-
-0x84, 0x3E, 0x58, 0xE9,
-0x28, 0x1D, 0x6F, 0x8F,
-
-0x05, 0x20,
-0x00, 0xE0,
-0x85, 0x1E, 0x58, 0xE9,
-
-0x9B, 0x3B, 0x33, 0xDF,
-0x20, 0x20, 0x42, 0xAF,
-
-0x30, 0x42, 0x56, 0x9F,
-0x80, 0x3E, 0x57, 0xE9,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x30, 0x80, 0x5F, 0xE9,
-
-0x28, 0x28, 0x24, 0xAF,
-0x81, 0x1E, 0x57, 0xE9,
-
-0x05, 0x47, 0x57, 0xBF,
-0x0D, 0x47, 0x4F, 0xBF,
-
-0x88, 0x80, 0x58, 0xE9,
-0x1B, 0x29, 0x1B, 0xDF,
-
-0x30, 0x1D, 0x6F, 0x8F,
-0x3A, 0x30, 0x4F, 0xE9,
-
-0x1C, 0x30, 0x26, 0xDF,
-0x09, 0xE3,
-0x3B, 0x05,
-
-0x3E, 0x50, 0x56, 0x9F,
-0x3B, 0x3F, 0x4F, 0xE9,
-
-0x1E, 0x8F, 0x51, 0x9F,
-0x00, 0xE0,
-0xAC, 0x20,
-
-0x2D, 0x44, 0x4C, 0xB4,
-0x2C, 0x1C, 0xC0, 0xAF,
-
-0x25, 0x44, 0x54, 0xB4,
-0x00, 0xE0,
-0xC8, 0x30,
-
-0x30, 0x46, 0x30, 0xAF,
-0x1B, 0x1B, 0x48, 0xAF,
-
-0x00, 0xE0,
-0x25, 0x20,
-0x38, 0x2C, 0x4F, 0xE9,
-
-0x86, 0x80, 0x57, 0xE9,
-0x38, 0x1D, 0x6F, 0x8F,
-
-0x28, 0x74,
-0x00, 0xE0,
-0x0D, 0x44, 0x4C, 0xB0,
-
-0x05, 0x44, 0x54, 0xB0,
-0x2D, 0x20,
-0x9B, 0x10,
-
-0x82, 0x3E, 0x57, 0xE9,
-0x32, 0xF0, 0x1B, 0xCD,
-
-0x1E, 0xBD, 0x59, 0x9F,
-0x83, 0x1E, 0x57, 0xE9,
-
-0x38, 0x47, 0x38, 0xAF,
-0x34, 0x20,
-0x2A, 0x30,
-
-0x00, 0xE0,
-0x0D, 0x20,
-0x32, 0x20,
-0x05, 0x20,
-
-0x87, 0x80, 0x57, 0xE9,
-0x1F, 0x54, 0x57, 0x9F,
-
-0x17, 0x42, 0x56, 0x9F,
-0x00, 0xE0,
-0x3B, 0x6A,
-
-0x3F, 0x8F, 0x51, 0x9F,
-0x37, 0x1E, 0x4F, 0xE9,
-
-0x37, 0x32, 0x2A, 0xAF,
-0x00, 0xE0,
-0x32, 0x00,
-
-0x00, 0x80, 0x00, 0xE8,
-0x27, 0xC0, 0x44, 0xC0,
-
-0x36, 0x1F, 0x4F, 0xE9,
-0x1F, 0x1F, 0x26, 0xDF,
-
-0x37, 0x1B, 0x37, 0xBF,
-0x17, 0x26, 0x17, 0xDF,
-
-0x3E, 0x17, 0x4F, 0xE9,
-0x3F, 0x3F, 0x4F, 0xE9,
-
-0x34, 0x1F, 0x34, 0xAF,
-0x2B, 0x05,
-0xA7, 0x20,
-
-0x33, 0x2B, 0x37, 0xDF,
-0x27, 0x17, 0xC0, 0xAF,
-
-0x34, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2D, 0x21, 0x1A, 0xB0,
-0x25, 0x21, 0x31, 0xB0,
-
-0x0D, 0x21, 0x1A, 0xB2,
-0x05, 0x21, 0x31, 0xB2,
-
-0x03, 0x80, 0x2A, 0xEA,
-0x17, 0xC1, 0x2B, 0xBD,
-
-0x2D, 0x20,
-0x25, 0x20,
-0x05, 0x20,
-0x0D, 0x20,
-
-0xB3, 0x68,
-0x97, 0x25,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0xC0, 0x33, 0xAF,
-0x2F, 0xC0, 0x21, 0xC0,
-
-0x16, 0x42, 0x56, 0x9F,
-0x3C, 0x27, 0x4F, 0xE9,
-
-0x1E, 0x62, 0x57, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x21, 0x31, 0xB4,
-0x2D, 0x21, 0x1A, 0xB4,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x33, 0x05,
-0x00, 0xE0,
-0x28, 0x19, 0x60, 0xEC,
-
-0x0D, 0x21, 0x1A, 0xB6,
-0x05, 0x21, 0x31, 0xB6,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0xE0,
-0x2F, 0x20,
-
-0x23, 0x3B, 0x33, 0xAD,
-0x1E, 0x26, 0x1E, 0xDF,
-
-0xA7, 0x1E, 0x4F, 0xE9,
-0x17, 0x26, 0x16, 0xDF,
-
-0x2D, 0x20,
-0x00, 0xE0,
-0xA8, 0x3F, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x1E, 0xAF,
-0x25, 0x20,
-0x00, 0xE0,
-
-0xA4, 0x16, 0x4F, 0xE9,
-0x0F, 0xC0, 0x21, 0xC2,
-
-0xA6, 0x80, 0x4F, 0xE9,
-0x1F, 0x62, 0x57, 0x9F,
-
-0x0D, 0x20,
-0x05, 0x20,
-0x2F, 0xC0, 0x21, 0xC6,
-
-0x3F, 0x2F, 0x5D, 0x9F,
-0x00, 0xE0,
-0x0F, 0x20,
-
-0x17, 0x50, 0x56, 0x9F,
-0xA5, 0x37, 0x4F, 0xE9,
-
-0x06, 0xC0, 0x21, 0xC4,
-0x0F, 0x17, 0x0F, 0xAF,
-
-0x37, 0x0F, 0x5C, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2F, 0x20,
-0x00, 0xE0,
-0xA3, 0x80, 0x4F, 0xE9,
-
-0x06, 0x20,
-0x00, 0xE0,
-0x1F, 0x26, 0x1F, 0xDF,
-
-0x17, 0x26, 0x17, 0xDF,
-0x35, 0x17, 0x4F, 0xE9,
-
-0xA1, 0x1F, 0x4F, 0xE9,
-0xA2, 0x3F, 0x4F, 0xE9,
-
-0x06, 0x06, 0x1F, 0xAF,
-0x39, 0x37, 0x4F, 0xE9,
-
-0x2F, 0x2F, 0x17, 0xAF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xA0, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x31, 0x80, 0x4F, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x57, 0x39, 0x20, 0xE9,
-
-0x16, 0x28, 0x20, 0xE9,
-0x1D, 0x3B, 0x20, 0xE9,
-
-0x1E, 0x2B, 0x20, 0xE9,
-0x2B, 0x32, 0x20, 0xE9,
-
-0x1C, 0x23, 0x20, 0xE9,
-0x57, 0x36, 0x20, 0xE9,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x40, 0x40, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x90, 0xE2,
-0x00, 0xE0,
-
-0x68, 0xFF, 0x20, 0xEA,
-0x19, 0xC8, 0xC1, 0xCD,
-
-0x1F, 0xD7, 0x18, 0xBD,
-0x3F, 0xD7, 0x22, 0xBD,
-
-0x9F, 0x41, 0x49, 0xBD,
-0x00, 0x80, 0x00, 0xE8,
-
-0x25, 0x41, 0x49, 0xBD,
-0x2D, 0x41, 0x51, 0xBD,
-
-0x0D, 0x80, 0x07, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x35, 0x40, 0x48, 0xBD,
-0x3D, 0x40, 0x50, 0xBD,
-
-0x00, 0x80, 0x00, 0xE8,
-0x25, 0x30,
-0x2D, 0x30,
-
-0x35, 0x30,
-0xB5, 0x30,
-0xBD, 0x30,
-0x3D, 0x30,
-
-0x9C, 0xA7, 0x5B, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x67, 0xFF, 0x0A, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC9, 0x41, 0xC8, 0xEC,
-0x42, 0xE1,
-0x00, 0xE0,
-
-0x65, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0xC8, 0x40, 0xC0, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x62, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-};
-
-static unsigned char warp_g400_t2gz[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x78, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x69, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x25, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x9F, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xBE, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x7D, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gza[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x7C, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x6D, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x29, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0F, 0xCF, 0x74, 0xC6,
-0x3D, 0xCF, 0x74, 0xC2,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB4,
-0x02, 0x44, 0x64, 0xB4,
-
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x9B, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xBA, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x79, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzaf[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x81, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x72, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x37, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x2E, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x0F, 0xCF, 0x74, 0xC6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB4,
-0x02, 0x44, 0x64, 0xB4,
-
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x3D, 0xCF, 0x75, 0xC6,
-0x00, 0x80, 0x00, 0xE8,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x45, 0x55, 0xB6,
-0x02, 0x45, 0x65, 0xB6,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x96, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xB5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x74, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzf[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x7D, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x6E, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0F, 0xCF, 0x75, 0xC6,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x28, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x0F, 0x20, 0xE9,
-
-0x0A, 0x44, 0x54, 0xB4,
-0x02, 0x44, 0x64, 0xB4,
-
-0x2A, 0x45, 0x55, 0xB6,
-0x1A, 0x45, 0x65, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x9A, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xBB, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x78, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzs[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x85, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x76, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x31, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
-
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
-
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x20,
-0x1A, 0x20,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA7, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x92, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xB2, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x70, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsa[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x8A, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x7B, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x36, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
-
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
-
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
-
-0x0F, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x8D, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xAD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x6B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsaf[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x8E, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x7F, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x3A, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
-
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
-
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
-
-0x0F, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB6,
-0x1A, 0x44, 0x64, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x45, 0x55, 0xB6,
-0x02, 0x45, 0x65, 0xB6,
-
-0x3D, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x89, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xA9, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x67, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_t2gzsf[] = {
-
-0x00, 0x8A, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x0A, 0x40, 0x50, 0xBF,
-0x2A, 0x40, 0x60, 0xBF,
-
-0x32, 0x41, 0x51, 0xBF,
-0x3A, 0x41, 0x61, 0xBF,
-
-0xC3, 0x6B,
-0xD3, 0x6B,
-0x00, 0x8A, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x53, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x23, 0x9F,
-0x00, 0xE0,
-0x51, 0x04,
-
-0x90, 0xE2,
-0x61, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x51, 0x41, 0xE0, 0xEC,
-0x39, 0x67, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x63, 0xA0, 0xE8,
-
-0x61, 0x41, 0xE0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x8A, 0x80, 0x15, 0xEA,
-0x10, 0x04,
-0x20, 0x04,
-
-0x61, 0x51, 0xE0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x52, 0xBF,
-0x0F, 0x52, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x62, 0xBF,
-0x1E, 0x51, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x0E, 0x61, 0x60, 0xEA,
-
-0x32, 0x40, 0x50, 0xBD,
-0x22, 0x40, 0x60, 0xBD,
-
-0x12, 0x41, 0x51, 0xBD,
-0x3A, 0x41, 0x61, 0xBD,
-
-0xBF, 0x2F, 0x0E, 0xBD,
-0x97, 0xE2,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x35, 0x48, 0xB1, 0xE8,
-0x3D, 0x59, 0xB1, 0xE8,
-
-0x46, 0x31, 0x46, 0xBF,
-0x56, 0x31, 0x56, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x66, 0x31, 0x66, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x57, 0x39, 0x57, 0xBF,
-0x67, 0x39, 0x67, 0xBF,
-
-0x7B, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x35, 0x00,
-0x3D, 0x00,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0x8D, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x75, 0xF8, 0xEC,
-0x35, 0x20,
-0x3D, 0x20,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x53, 0x53, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x0E, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x48, 0x35, 0x48, 0xBF,
-0x58, 0x35, 0x58, 0xBF,
-
-0x68, 0x35, 0x68, 0xBF,
-0x49, 0x3D, 0x49, 0xBF,
-
-0x59, 0x3D, 0x59, 0xBF,
-0x69, 0x3D, 0x69, 0xBF,
-
-0x63, 0x63, 0x2D, 0xDF,
-0x4D, 0x7D, 0xF8, 0xEC,
-
-0x59, 0xE3,
-0x00, 0xE0,
-0xB8, 0x38, 0x33, 0xBF,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x18, 0x3A, 0x41, 0xE9,
-
-0x3F, 0x53, 0xA0, 0xE8,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x63, 0xA0, 0xE8,
-
-0x50, 0x70, 0xF8, 0xEC,
-0x2B, 0x50, 0x3C, 0xE9,
-
-0x1F, 0x0F, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x59, 0x78, 0xF8, 0xEC,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x46, 0x37, 0x46, 0xDF,
-0x56, 0x3F, 0x56, 0xDF,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x66, 0x3D, 0x66, 0xDF,
-
-0x1D, 0x32, 0x41, 0xE9,
-0x67, 0x3D, 0x67, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3F, 0x57, 0xDF,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x59, 0x3F, 0x59, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x69, 0x3D, 0x69, 0xDF,
-
-0x48, 0x37, 0x48, 0xDF,
-0x58, 0x3F, 0x58, 0xDF,
-
-0x68, 0x3D, 0x68, 0xDF,
-0x49, 0x37, 0x49, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x0F, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x54, 0xB0,
-0x02, 0x44, 0x64, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB2,
-0x1A, 0x44, 0x64, 0xB2,
-
-0x36, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0F, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x54, 0xB4,
-0x1A, 0x44, 0x64, 0xB4,
-
-0x0A, 0x45, 0x55, 0xB0,
-0x02, 0x45, 0x65, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x55, 0xB2,
-0x1A, 0x45, 0x65, 0xB2,
-
-0x0A, 0x45, 0x55, 0xB4,
-0x02, 0x45, 0x65, 0xB4,
-
-0x0F, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x0F, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x55, 0xB6,
-0x1A, 0x45, 0x65, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x56, 0xBF,
-0x1A, 0x46, 0x66, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x57, 0xBF,
-0x02, 0x47, 0x67, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x53, 0xBF,
-0x1A, 0x43, 0x63, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x48, 0x58, 0xBF,
-0x02, 0x48, 0x68, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x2A, 0x49, 0x59, 0xBF,
-0x1A, 0x49, 0x69, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x82, 0x30, 0x57, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x83, 0x38, 0x57, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x84, 0x31, 0x5E, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x85, 0x39, 0x5E, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x87, 0x77, 0x57, 0xE9,
-0x8B, 0x3E, 0xBF, 0xEA,
-
-0x80, 0x30, 0x57, 0xE9,
-0x81, 0x38, 0x57, 0xE9,
-
-0x82, 0x31, 0x57, 0xE9,
-0x86, 0x78, 0x57, 0xE9,
-
-0x83, 0x39, 0x57, 0xE9,
-0x87, 0x79, 0x57, 0xE9,
-
-0x30, 0x1F, 0x5F, 0xE9,
-0x8A, 0x34, 0x20, 0xE9,
-
-0x8B, 0x3C, 0x20, 0xE9,
-0x37, 0x50, 0x60, 0xBD,
-
-0x57, 0x0D, 0x20, 0xE9,
-0x35, 0x51, 0x61, 0xBD,
-
-0x2B, 0x50, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x0E, 0x77,
-
-0x24, 0x51, 0x20, 0xE9,
-0x8D, 0xFF, 0x20, 0xEA,
-
-0x16, 0x0E, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x0B, 0x46, 0xA0, 0xE8,
-0x1B, 0x56, 0xA0, 0xE8,
-
-0x2B, 0x66, 0xA0, 0xE8,
-0x0C, 0x47, 0xA0, 0xE8,
-
-0x1C, 0x57, 0xA0, 0xE8,
-0x2C, 0x67, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x57, 0x80, 0x57, 0xCF,
-
-0x66, 0x33, 0x66, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x67, 0x3B, 0x67, 0xCF,
-
-0x0B, 0x48, 0xA0, 0xE8,
-0x1B, 0x58, 0xA0, 0xE8,
-
-0x2B, 0x68, 0xA0, 0xE8,
-0x0C, 0x49, 0xA0, 0xE8,
-
-0x1C, 0x59, 0xA0, 0xE8,
-0x2C, 0x69, 0xA0, 0xE8,
-
-0x0B, 0x00,
-0x1B, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x0C, 0x00,
-0x1C, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x0B, 0x65,
-0x1B, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x0C, 0x65,
-0x1C, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x0B, 0x1B, 0x60, 0xEC,
-0x34, 0xD7, 0x34, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x0C, 0x1C, 0x60, 0xEC,
-
-0x3C, 0xD7, 0x3C, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x0B, 0x2B, 0xDE, 0xE8,
-0x1B, 0x80, 0xDE, 0xE8,
-
-0x34, 0x80, 0x34, 0xBD,
-0x3C, 0x80, 0x3C, 0xBD,
-
-0x33, 0xD7, 0x0B, 0xBD,
-0x3B, 0xD7, 0x1B, 0xBD,
-
-0x48, 0x80, 0x48, 0xCF,
-0x59, 0x80, 0x59, 0xCF,
-
-0x68, 0x33, 0x68, 0xCF,
-0x49, 0x3B, 0x49, 0xCF,
-
-0xAD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x58, 0x33, 0x58, 0xCF,
-0x69, 0x3B, 0x69, 0xCF,
-
-0x6B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgz[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x58, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x4A, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x1D, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0xAF, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xD6, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x9D, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgza[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x5C, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x4E, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x27, 0xCF, 0x74, 0xC6,
-0x3D, 0xCF, 0x74, 0xC2,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x20, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
-
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
-
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0xAB, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xD3, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x99, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzaf[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x61, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x53, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x34, 0x37, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x26, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x27, 0xCF, 0x74, 0xC6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
-
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
-
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x3D, 0xCF, 0x75, 0xC6,
-0x00, 0x80, 0x00, 0xE8,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x45, 0x4D, 0xB6,
-0x02, 0x45, 0x55, 0xB6,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0xA6, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xCD, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x94, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzf[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x5D, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x4F, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x34, 0x80, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x27, 0xCF, 0x75, 0xC6,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x20, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x3D, 0xCF, 0x74, 0xC2,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x27, 0x20, 0xE9,
-
-0x0A, 0x44, 0x4C, 0xB4,
-0x02, 0x44, 0x54, 0xB4,
-
-0x2A, 0x45, 0x4D, 0xB6,
-0x1A, 0x45, 0x55, 0xB6,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x38, 0x3D, 0x20, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0xAA, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xD3, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x98, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzs[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x65, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x57, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x29, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
-
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
-
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x20,
-0x02, 0x20,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA7, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0xA2, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xCA, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x90, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsa[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x6A, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x5C, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x2E, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
-
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
-
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
-
-0x27, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0x9D, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xC5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x8B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsaf[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x6E, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x60, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x32, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
-
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
-
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
-
-0x27, 0xCF, 0x74, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9C, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB6,
-0x1A, 0x44, 0x54, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x45, 0x4D, 0xB6,
-0x02, 0x45, 0x55, 0xB6,
-
-0x3D, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x31, 0x3D, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x9D, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x9E, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x30, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x38, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0x99, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xC1, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x87, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
-
-static unsigned char warp_g400_tgzsf[] = {
-
-0x00, 0x88, 0x98, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-0xFF, 0x80, 0xC0, 0xE9,
-0x00, 0x80, 0x00, 0xE8,
-
-0x22, 0x40, 0x48, 0xBF,
-0x2A, 0x40, 0x50, 0xBF,
-
-0x32, 0x41, 0x49, 0xBF,
-0x3A, 0x41, 0x51, 0xBF,
-
-0xC3, 0x6B,
-0xCB, 0x6B,
-0x00, 0x88, 0x98, 0xE9,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x96, 0xE2,
-0x41, 0x04,
-
-0x7B, 0x43, 0xA0, 0xE8,
-0x73, 0x4B, 0xA0, 0xE8,
-
-0xAD, 0xEE, 0x29, 0x9F,
-0x00, 0xE0,
-0x49, 0x04,
-
-0x90, 0xE2,
-0x51, 0x04,
-0x31, 0x46, 0xB1, 0xE8,
-
-0x49, 0x41, 0xC0, 0xEC,
-0x39, 0x57, 0xB1, 0xE8,
-
-0x00, 0x04,
-0x46, 0xE2,
-0x73, 0x53, 0xA0, 0xE8,
-
-0x51, 0x41, 0xC0, 0xEC,
-0x31, 0x00,
-0x39, 0x00,
-
-0x6A, 0x80, 0x15, 0xEA,
-0x08, 0x04,
-0x10, 0x04,
-
-0x51, 0x49, 0xC0, 0xEC,
-0x2F, 0x41, 0x60, 0xEA,
-
-0x31, 0x20,
-0x39, 0x20,
-0x1F, 0x42, 0xA0, 0xE8,
-
-0x2A, 0x42, 0x4A, 0xBF,
-0x27, 0x4A, 0xA0, 0xE8,
-
-0x1A, 0x42, 0x52, 0xBF,
-0x1E, 0x49, 0x60, 0xEA,
-
-0x73, 0x7B, 0xC8, 0xEC,
-0x26, 0x51, 0x60, 0xEA,
-
-0x32, 0x40, 0x48, 0xBD,
-0x22, 0x40, 0x50, 0xBD,
-
-0x12, 0x41, 0x49, 0xBD,
-0x3A, 0x41, 0x51, 0xBD,
-
-0xBF, 0x2F, 0x26, 0xBD,
-0x00, 0xE0,
-0x7B, 0x72,
-
-0x32, 0x20,
-0x22, 0x20,
-0x12, 0x20,
-0x3A, 0x20,
-
-0x46, 0x31, 0x46, 0xBF,
-0x4E, 0x31, 0x4E, 0xBF,
-
-0xB3, 0xE2, 0x2D, 0x9F,
-0x00, 0x80, 0x00, 0xE8,
-
-0x56, 0x31, 0x56, 0xBF,
-0x47, 0x39, 0x47, 0xBF,
-
-0x4F, 0x39, 0x4F, 0xBF,
-0x57, 0x39, 0x57, 0xBF,
-
-0x5C, 0x80, 0x07, 0xEA,
-0x24, 0x41, 0x20, 0xE9,
-
-0x42, 0x73, 0xF8, 0xEC,
-0x00, 0xE0,
-0x2D, 0x73,
-
-0x33, 0x72,
-0x0C, 0xE3,
-0xA5, 0x2F, 0x1E, 0xBD,
-
-0x43, 0x43, 0x2D, 0xDF,
-0x4B, 0x4B, 0x2D, 0xDF,
-
-0xAE, 0x1E, 0x26, 0xBD,
-0x58, 0xE3,
-0x33, 0x66,
-
-0x53, 0x53, 0x2D, 0xDF,
-0x00, 0x80, 0x00, 0xE8,
-
-0xB8, 0x38, 0x33, 0xBF,
-0x00, 0xE0,
-0x59, 0xE3,
-
-0x1E, 0x12, 0x41, 0xE9,
-0x1A, 0x22, 0x41, 0xE9,
-
-0x2B, 0x40, 0x3D, 0xE9,
-0x3F, 0x4B, 0xA0, 0xE8,
-
-0x2D, 0x73,
-0x30, 0x76,
-0x05, 0x80, 0x3D, 0xEA,
-
-0x37, 0x43, 0xA0, 0xE8,
-0x3D, 0x53, 0xA0, 0xE8,
-
-0x48, 0x70, 0xF8, 0xEC,
-0x2B, 0x48, 0x3C, 0xE9,
-
-0x1F, 0x27, 0xBC, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x00, 0x80, 0x00, 0xE8,
-0x00, 0x80, 0x00, 0xE8,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x15, 0xC0, 0x20, 0xE9,
-0x15, 0xC0, 0x20, 0xE9,
-
-0x18, 0x3A, 0x41, 0xE9,
-0x1D, 0x32, 0x41, 0xE9,
-
-0x2A, 0x40, 0x20, 0xE9,
-0x56, 0x3D, 0x56, 0xDF,
-
-0x46, 0x37, 0x46, 0xDF,
-0x4E, 0x3F, 0x4E, 0xDF,
-
-0x16, 0x30, 0x20, 0xE9,
-0x4F, 0x3F, 0x4F, 0xDF,
-
-0x47, 0x37, 0x47, 0xDF,
-0x57, 0x3D, 0x57, 0xDF,
-
-0x32, 0x32, 0x2D, 0xDF,
-0x22, 0x22, 0x2D, 0xDF,
-
-0x12, 0x12, 0x2D, 0xDF,
-0x3A, 0x3A, 0x2D, 0xDF,
-
-0x27, 0xCF, 0x74, 0xC2,
-0x37, 0xCF, 0x74, 0xC4,
-
-0x0A, 0x44, 0x4C, 0xB0,
-0x02, 0x44, 0x54, 0xB0,
-
-0x3D, 0xCF, 0x74, 0xC0,
-0x34, 0x37, 0x20, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x38, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3C, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB2,
-0x1A, 0x44, 0x54, 0xB2,
-
-0x2E, 0x80, 0x3A, 0xEA,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x27, 0xCF, 0x75, 0xC0,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x32, 0x31, 0x5F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x33, 0x39, 0x5F, 0xE9,
-
-0x3D, 0xCF, 0x75, 0xC2,
-0x37, 0xCF, 0x75, 0xC4,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA6, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA3, 0x3D, 0x20, 0xE9,
-
-0x2A, 0x44, 0x4C, 0xB4,
-0x1A, 0x44, 0x54, 0xB4,
-
-0x0A, 0x45, 0x4D, 0xB0,
-0x02, 0x45, 0x55, 0xB0,
-
-0x88, 0x73, 0x5E, 0xE9,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA0, 0x37, 0x20, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x3E, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x3F, 0x38, 0x4F, 0xE9,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x3A, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x3B, 0x39, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x4D, 0xB2,
-0x1A, 0x45, 0x55, 0xB2,
-
-0x0A, 0x45, 0x4D, 0xB4,
-0x02, 0x45, 0x55, 0xB4,
-
-0x27, 0xCF, 0x75, 0xC6,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0xA7, 0x30, 0x4F, 0xE9,
-0x0A, 0x20,
-0x02, 0x20,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x31, 0x27, 0x20, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA8, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x45, 0x4D, 0xB6,
-0x1A, 0x45, 0x55, 0xB6,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x36, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x37, 0x39, 0x4F, 0xE9,
-
-0x00, 0x80, 0x00, 0xE8,
-0x2A, 0x20,
-0x1A, 0x20,
-
-0x2A, 0x46, 0x4E, 0xBF,
-0x1A, 0x46, 0x56, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA4, 0x31, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA5, 0x39, 0x4F, 0xE9,
-
-0x0A, 0x47, 0x4F, 0xBF,
-0x02, 0x47, 0x57, 0xBF,
-
-0x31, 0x53, 0x2F, 0x9F,
-0xA1, 0x30, 0x4F, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0xA2, 0x38, 0x4F, 0xE9,
-
-0x2A, 0x43, 0x4B, 0xBF,
-0x1A, 0x43, 0x53, 0xBF,
-
-0x30, 0x50, 0x2E, 0x9F,
-0x35, 0x31, 0x4F, 0xE9,
-
-0x38, 0x21, 0x2C, 0x9F,
-0x39, 0x39, 0x4F, 0xE9,
-
-0x31, 0x53, 0x2F, 0x9F,
-0x80, 0x31, 0x57, 0xE9,
-
-0x39, 0xE5, 0x2C, 0x9F,
-0x81, 0x39, 0x57, 0xE9,
-
-0x37, 0x48, 0x50, 0xBD,
-0x8A, 0x36, 0x20, 0xE9,
-
-0x86, 0x76, 0x57, 0xE9,
-0x8B, 0x3E, 0x20, 0xE9,
-
-0x82, 0x30, 0x57, 0xE9,
-0x87, 0x77, 0x57, 0xE9,
-
-0x83, 0x38, 0x57, 0xE9,
-0x35, 0x49, 0x51, 0xBD,
-
-0x84, 0x31, 0x5E, 0xE9,
-0x30, 0x1F, 0x5F, 0xE9,
-
-0x85, 0x39, 0x5E, 0xE9,
-0x57, 0x25, 0x20, 0xE9,
-
-0x2B, 0x48, 0x20, 0xE9,
-0x1D, 0x37, 0xE1, 0xEA,
-
-0x1E, 0x35, 0xE1, 0xEA,
-0x00, 0xE0,
-0x26, 0x77,
-
-0x24, 0x49, 0x20, 0xE9,
-0x9D, 0xFF, 0x20, 0xEA,
-
-0x16, 0x26, 0x20, 0xE9,
-0x57, 0x2E, 0xBF, 0xEA,
-
-0x1C, 0x46, 0xA0, 0xE8,
-0x23, 0x4E, 0xA0, 0xE8,
-
-0x2B, 0x56, 0xA0, 0xE8,
-0x1D, 0x47, 0xA0, 0xE8,
-
-0x24, 0x4F, 0xA0, 0xE8,
-0x2C, 0x57, 0xA0, 0xE8,
-
-0x1C, 0x00,
-0x23, 0x00,
-0x2B, 0x00,
-0x00, 0xE0,
-
-0x1D, 0x00,
-0x24, 0x00,
-0x2C, 0x00,
-0x00, 0xE0,
-
-0x1C, 0x65,
-0x23, 0x65,
-0x2B, 0x65,
-0x00, 0xE0,
-
-0x1D, 0x65,
-0x24, 0x65,
-0x2C, 0x65,
-0x00, 0xE0,
-
-0x1C, 0x23, 0x60, 0xEC,
-0x36, 0xD7, 0x36, 0xAD,
-
-0x2B, 0x80, 0x60, 0xEC,
-0x1D, 0x24, 0x60, 0xEC,
-
-0x3E, 0xD7, 0x3E, 0xAD,
-0x2C, 0x80, 0x60, 0xEC,
-
-0x1C, 0x2B, 0xDE, 0xE8,
-0x23, 0x80, 0xDE, 0xE8,
-
-0x36, 0x80, 0x36, 0xBD,
-0x3E, 0x80, 0x3E, 0xBD,
-
-0x33, 0xD7, 0x1C, 0xBD,
-0x3B, 0xD7, 0x23, 0xBD,
-
-0x46, 0x80, 0x46, 0xCF,
-0x4F, 0x80, 0x4F, 0xCF,
-
-0x56, 0x33, 0x56, 0xCF,
-0x47, 0x3B, 0x47, 0xCF,
-
-0xC5, 0xFF, 0x20, 0xEA,
-0x00, 0x80, 0x00, 0xE8,
-
-0x4E, 0x33, 0x4E, 0xCF,
-0x57, 0x3B, 0x57, 0xCF,
-
-0x8B, 0xFF, 0x20, 0xEA,
-0x57, 0xC0, 0xBF, 0xEA,
-
-0x00, 0x80, 0xA0, 0xE9,
-0x00, 0x00, 0xD8, 0xEC,
-
-};
diff --git a/linux/mga_warp.c b/linux/mga_warp.c
deleted file mode 100644
index 4dd998b3..00000000
--- a/linux/mga_warp.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
- * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "mga_ucode.h"
-
-
-#define MGA_WARP_CODE_ALIGN		256		/* in bytes */
-
-#define WARP_UCODE_SIZE( which )					\
-	((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
-
-#define WARP_UCODE_INSTALL( which, where )				\
-do {									\
-	DRM_DEBUG( " pcbase = 0x%08lx  vcbase = %p\n", pcbase, vcbase );\
-	dev_priv->warp_pipe_phys[where] = pcbase;			\
-	memcpy( vcbase, which, sizeof(which) );				\
-	pcbase += WARP_UCODE_SIZE( which );				\
-	vcbase += WARP_UCODE_SIZE( which );				\
-} while (0)
-
-
-static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv )
-{
-	unsigned int size;
-
-	size = ( WARP_UCODE_SIZE( warp_g400_tgz ) +
-		 WARP_UCODE_SIZE( warp_g400_tgza ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gz ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gza ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzs ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsf ) );
-
-	size = PAGE_ALIGN( size );
-
-	DRM_DEBUG( "G400 ucode size = %d bytes\n", size );
-	return size;
-}
-
-static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv )
-{
-	unsigned int size;
-
-	size = ( WARP_UCODE_SIZE( warp_g200_tgz ) +
-		 WARP_UCODE_SIZE( warp_g200_tgza ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsf ) );
-
-	size = PAGE_ALIGN( size );
-
-	DRM_DEBUG( "G200 ucode size = %d bytes\n", size );
-	return size;
-}
-
-static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv )
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-	unsigned int size;
-
-	size = mga_warp_g400_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
-		return -ENOMEM;
-	}
-
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
-
-	WARP_UCODE_INSTALL( warp_g400_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g400_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g400_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g400_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g400_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g400_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g400_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g400_tgzsaf,	MGA_WARP_TGZSAF );
-
-	WARP_UCODE_INSTALL( warp_g400_t2gz,	MGA_WARP_T2GZ );
-	WARP_UCODE_INSTALL( warp_g400_t2gzf,	MGA_WARP_T2GZF );
-	WARP_UCODE_INSTALL( warp_g400_t2gza,	MGA_WARP_T2GZA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzaf,	MGA_WARP_T2GZAF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzs,	MGA_WARP_T2GZS );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsf,	MGA_WARP_T2GZSF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsa,	MGA_WARP_T2GZSA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsaf,	MGA_WARP_T2GZSAF );
-
-	return 0;
-}
-
-static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv )
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-	unsigned int size;
-
-	size = mga_warp_g200_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
-		return -ENOMEM;
-	}
-
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
-
-	WARP_UCODE_INSTALL( warp_g200_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g200_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g200_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g200_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g200_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g200_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g200_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g200_tgzsaf,	MGA_WARP_TGZSAF );
-
-	return 0;
-}
-
-int mga_warp_install_microcode(	drm_mga_private_t *dev_priv )
-{
-	switch ( dev_priv->chipset ) {
-	case MGA_CARD_TYPE_G400:
-		return mga_warp_install_g400_microcode( dev_priv );
-	case MGA_CARD_TYPE_G200:
-		return mga_warp_install_g200_microcode( dev_priv );
-	default:
-		return -EINVAL;
-	}
-}
-
-#define WMISC_EXPECTED		(MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
-
-int mga_warp_init( drm_mga_private_t *dev_priv )
-{
-	u32 wmisc;
-
-	/* FIXME: Get rid of these damned magic numbers...
-	 */
-	switch ( dev_priv->chipset ) {
-	case MGA_CARD_TYPE_G400:
-		MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x00000E00 );
-		MGA_WRITE( MGA_WVRTXSZ, 0x00001807 );
-		MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 );
-		break;
-	case MGA_CARD_TYPE_G200:
-		MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x1606 );
-		MGA_WRITE( MGA_WVRTXSZ, 7 );
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
-			       MGA_WMASTER_ENABLE |
-			       MGA_WCACHEFLUSH_ENABLE) );
-	wmisc = MGA_READ( MGA_WMISC );
-	if ( wmisc != WMISC_EXPECTED ) {
-		DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n",
-			   wmisc, WMISC_EXPECTED );
-		return -EINVAL;
-	}
-
-	return 0;
-}
diff --git a/linux/r128.h b/linux/r128.h
deleted file mode 100644
index 926b4bfd..00000000
--- a/linux/r128.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* r128.h -- ATI Rage 128 DRM template customization -*- linux-c -*-
- * Created: Wed Feb 14 16:07:10 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __R128_H__
-#define __R128_H__
-
-/* This remains constant for all DRM template files.
- */
-#define DRM(x) r128_##x
-
-/* General customization:
- */
-#define __HAVE_AGP		1
-#define __MUST_HAVE_AGP		0
-#define __HAVE_MTRR		1
-#define __HAVE_CTX_BITMAP	1
-#define __HAVE_SG		1
-#define __HAVE_PCI_DMA		1
-
-/* Driver customization:
- */
-#define DRIVER_PRERELEASE() do {					\
-	if ( dev->dev_private ) {					\
-		drm_r128_private_t *dev_priv = dev->dev_private;	\
-		if ( dev_priv->page_flipping ) {			\
-			r128_do_cleanup_pageflip( dev );		\
-		}							\
-	}								\
-} while (0)
-
-#define DRIVER_PRETAKEDOWN() do {					\
-	if ( dev->dev_private ) r128_do_cleanup_cce( dev );		\
-} while (0)
-
-/* DMA customization:
- */
-#define __HAVE_DMA		1
-
-#if 0
-/* GH: Remove this for now... */
-#define __HAVE_DMA_QUIESCENT	1
-#define DRIVER_DMA_QUIESCENT() do {					\
-	drm_r128_private_t *dev_priv = dev->dev_private;		\
-	return r128_do_cce_idle( dev_priv );				\
-} while (0)
-#endif
-
-/* Buffer customization:
- */
-#define DRIVER_BUF_PRIV_T	drm_r128_buf_priv_t
-
-#define DRIVER_AGP_BUFFERS_MAP( dev )					\
-	((drm_r128_private_t *)((dev)->dev_private))->buffers
-
-#endif
diff --git a/linux/r128_cce.c b/linux/r128_cce.c
deleted file mode 100644
index 72b8d767..00000000
--- a/linux/r128_cce.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
- * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "r128.h"
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-
-#include <linux/interrupt.h>	/* For task queue support */
-#include <linux/delay.h>
-
-#define R128_FIFO_DEBUG		0
-
-
-/* CCE microcode (from ATI) */
-static u32 r128_cce_microcode[] = {
-	0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
-	1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
-	599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
-	11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
-	262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
-	1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
-	30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
-	1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
-	15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
-	12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
-	46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
-	459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
-	18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
-	15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
-	268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
-	15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
-	1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
-	3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
-	1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
-	15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
-	180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
-	114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
-	33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
-	1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
-	14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
-	1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
-	198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
-	114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
-	1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
-	1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
-	16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
-	174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
-	33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
-	33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
-	409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-
-int R128_READ_PLL(drm_device_t *dev, int addr)
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-
-	R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
-	return R128_READ(R128_CLOCK_CNTL_DATA);
-}
-
-#if R128_FIFO_DEBUG
-static void r128_status( drm_r128_private_t *dev_priv )
-{
-	printk( "GUI_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_GUI_STAT ) );
-	printk( "PM4_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_STAT ) );
-	printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
-	printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
-	printk( "PM4_MICRO_CNTL     = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
-	printk( "PM4_BUFFER_CNTL    = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
-}
-#endif
-
-
-/* ================================================================
- * Engine, FIFO control
- */
-
-static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
-{
-	u32 tmp;
-	int i;
-
-	tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
-	R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
-			return 0;
-		}
-		udelay( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	return -EBUSY;
-}
-
-static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
-		if ( slots >= entries ) return 0;
-		udelay( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	return -EBUSY;
-}
-
-int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
-{
-	int i, ret;
-
-	ret = r128_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret < 0 ) return ret;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
-			r128_do_pixcache_flush( dev_priv );
-			return 0;
-		}
-		udelay( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	return -EBUSY;
-}
-
-
-/* ================================================================
- * CCE control, initialization
- */
-
-/* Load the microcode for the CCE */
-static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
-{
-	int i;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	r128_do_wait_for_idle( dev_priv );
-
-	R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
-	for ( i = 0 ; i < 256 ; i++ ) {
-		R128_WRITE( R128_PM4_MICROCODE_DATAH,
-			    r128_cce_microcode[i * 2] );
-		R128_WRITE( R128_PM4_MICROCODE_DATAL,
-			    r128_cce_microcode[i * 2 + 1] );
-	}
-}
-
-/* Flush any pending commands to the CCE.  This should only be used just
- * prior to a wait for idle, as it informs the engine that the command
- * stream is ending.
- */
-static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
-{
-	u32 tmp;
-
-	tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
-}
-
-/* Wait for the CCE to go idle.
- */
-int r128_do_cce_idle( drm_r128_private_t *dev_priv )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
-			int pm4stat = R128_READ( R128_PM4_STAT );
-			if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
-			       dev_priv->cce_fifo_size ) &&
-			     !(pm4stat & (R128_PM4_BUSY |
-					  R128_PM4_GUI_ACTIVE)) ) {
-				return r128_do_pixcache_flush( dev_priv );
-			}
-		}
-		udelay( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	r128_status( dev_priv );
-#endif
-	return -EBUSY;
-}
-
-/* Start the Concurrent Command Engine.
- */
-static void r128_do_cce_start( drm_r128_private_t *dev_priv )
-{
-	r128_do_wait_for_idle( dev_priv );
-
-	R128_WRITE( R128_PM4_BUFFER_CNTL,
-		    dev_priv->cce_mode | dev_priv->ring.size_l2qw );
-	R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
-	R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
-
-	dev_priv->cce_running = 1;
-}
-
-/* Reset the Concurrent Command Engine.  This will not flush any pending
- * commands, so you must wait for the CCE command stream to complete
- * before calling this routine.
- */
-static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
-{
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
-	SET_RING_HEAD( &dev_priv->ring, 0 );
-	dev_priv->ring.tail = 0;
-}
-
-/* Stop the Concurrent Command Engine.  This will not flush any pending
- * commands, so you must flush the command stream and wait for the CCE
- * to go idle before calling this routine.
- */
-static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
-{
-	R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
-	R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
-
-	dev_priv->cce_running = 0;
-}
-
-/* Reset the engine.  This will stop the CCE if it is running.
- */
-static int r128_do_engine_reset( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
-
-	r128_do_pixcache_flush( dev_priv );
-
-	clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
-	mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
-
-	R128_WRITE_PLL( R128_MCLK_CNTL,
-			mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
-
-	gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
-
-	/* Taken from the sample code - do not change */
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl | R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl & ~R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
-
-	R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
-	R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
-	R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
-
-	/* Reset the CCE ring */
-	r128_do_cce_reset( dev_priv );
-
-	/* The CCE is no longer running after an engine reset */
-	dev_priv->cce_running = 0;
-
-	/* Reset any pending vertex, indirect buffers */
-	r128_freelist_reset( dev );
-
-	return 0;
-}
-
-static void r128_cce_init_ring_buffer( drm_device_t *dev,
-				       drm_r128_private_t *dev_priv )
-{
-	u32 ring_start;
-	u32 tmp;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The manual (p. 2) says this address is in "VM space".  This
-	 * means it's an offset from the start of AGP space.
-	 */
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		ring_start = dev_priv->cce_ring->offset - dev->agp->base;
-	else
-#endif
-		ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
-
-	R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
-
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
-
-	/* DL_RPTR_ADDR is a physical address in AGP space. */
-	SET_RING_HEAD( &dev_priv->ring, 0 );
-
-	if ( !dev_priv->is_pci ) {
-		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
-			    dev_priv->ring_rptr->offset );
-	} else {
-		drm_sg_mem_t *entry = dev->sg;
-		unsigned long tmp_ofs, page_ofs;
-
-		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
-		page_ofs = tmp_ofs >> PAGE_SHIFT;
-
-		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
-     			    entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
-			   entry->busaddr[page_ofs],
-     			   entry->handle + tmp_ofs );
-	}
-
-	/* Set watermark control */
-	R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
-		    ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
-		    | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
-		    | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
-		    | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
-
-	/* Force read.  Why?  Because it's in the examples... */
-	R128_READ( R128_PM4_BUFFER_ADDR );
-
-	/* Turn on bus mastering */
-	tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
-	R128_WRITE( R128_BUS_CNTL, tmp );
-}
-
-static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
-{
-	drm_r128_private_t *dev_priv;
-	struct list_head *list;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
-		return -ENOMEM;
-
-	memset( dev_priv, 0, sizeof(drm_r128_private_t) );
-
-	dev_priv->is_pci = init->is_pci;
-
-	if ( dev_priv->is_pci && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-
-	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-
-	dev_priv->cce_mode = init->cce_mode;
-
-	/* GH: Simple idle check.
-	 */
-	atomic_set( &dev_priv->idle_count, 0 );
-
-	/* We don't support anything other than bus-mastering ring mode,
-	 * but the ring can be in either AGP or PCI space for the ring
-	 * read pointer.
-	 */
-	if ( ( init->cce_mode != R128_PM4_192BM ) &&
-	     ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
-		DRM_DEBUG( "Bad cce_mode!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-
-	switch ( init->cce_mode ) {
-	case R128_PM4_NONPM4:
-		dev_priv->cce_fifo_size = 0;
-		break;
-	case R128_PM4_192PIO:
-	case R128_PM4_192BM:
-		dev_priv->cce_fifo_size = 192;
-		break;
-	case R128_PM4_128PIO_64INDBM:
-	case R128_PM4_128BM_64INDBM:
-		dev_priv->cce_fifo_size = 128;
-		break;
-	case R128_PM4_64PIO_128INDBM:
-	case R128_PM4_64BM_128INDBM:
-	case R128_PM4_64PIO_64VCBM_64INDBM:
-	case R128_PM4_64BM_64VCBM_64INDBM:
-	case R128_PM4_64PIO_64VCPIO_64INDPIO:
-		dev_priv->cce_fifo_size = 64;
-		break;
-	}
-
-	switch ( init->fb_bpp ) {
-	case 16:
-		dev_priv->color_fmt = R128_DATATYPE_RGB565;
-		break;
-	case 32:
-	default:
-		dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
-		break;
-	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	switch ( init->depth_bpp ) {
-	case 16:
-		dev_priv->depth_fmt = R128_DATATYPE_RGB565;
-		break;
-	case 24:
-	case 32:
-	default:
-		dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
-		break;
-	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-	dev_priv->span_offset	= init->span_offset;
-
-	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
-					  (dev_priv->front_offset >> 5));
-	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
-					 (dev_priv->back_offset >> 5));
-	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
-					  (dev_priv->depth_offset >> 5) |
-					  R128_DST_TILE);
-	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
-					 (dev_priv->span_offset >> 5));
-
-	list_for_each(list, &dev->maplist->head) {
-		drm_map_list_t *r_list = (drm_map_list_t *)list;
-		if( r_list->map &&
-		    r_list->map->type == _DRM_SHM &&
-		    r_list->map->flags & _DRM_CONTAINS_LOCK ) {
-			dev_priv->sarea = r_list->map;
- 			break;
- 		}
- 	}
-	if(!dev_priv->sarea) {
-		DRM_ERROR("could not find sarea!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR("could not find framebuffer!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR("could not find mmio region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
-	if(!dev_priv->cce_ring) {
-		DRM_ERROR("could not find cce ring region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
-	if(!dev_priv->ring_rptr) {
-		DRM_ERROR("could not find ring read pointer!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR("could not find dma buffer region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		return -EINVAL;
-	}
-
-	if ( !dev_priv->is_pci ) {
-		DRM_FIND_MAP( dev_priv->agp_textures,
-			      init->agp_textures_offset );
-		if(!dev_priv->agp_textures) {
-			DRM_ERROR("could not find agp texture region!\n");
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			return -EINVAL;
-		}
-	}
-
-	dev_priv->sarea_priv =
-		(drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				     init->sarea_priv_offset);
-
-	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cce_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
-		if(!dev_priv->cce_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev_priv->buffers->handle) {
-			DRM_ERROR("Could not ioremap agp regions!\n");
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			return -ENOMEM;
-		}
-	} else {
-		dev_priv->cce_ring->handle =
-			(void *)dev_priv->cce_ring->offset;
-		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
-	}
-
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		dev_priv->cce_buffers_offset = dev->agp->base;
-	else
-#endif
-		dev_priv->cce_buffers_offset = dev->sg->handle;
-
-	dev_priv->ring.head = ((__volatile__ u32 *)
-			       dev_priv->ring_rptr->handle);
-
-	dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
-			      + init->ring_size / sizeof(u32));
-	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
-
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
-
-	dev_priv->ring.high_mark = 128;
-
-	dev_priv->sarea_priv->last_frame = 0;
-	R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
-
-	dev_priv->sarea_priv->last_dispatch = 0;
-	R128_WRITE( R128_LAST_DISPATCH_REG,
-		    dev_priv->sarea_priv->last_dispatch );
-
-	if ( dev_priv->is_pci ) {
-		if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
-     					    &dev_priv->bus_pci_gart) ) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			return -ENOMEM;
-		}
-		R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
-	}
-
-	r128_cce_init_ring_buffer( dev, dev_priv );
-	r128_cce_load_microcode( dev_priv );
-
-	dev->dev_private = (void *)dev_priv;
-
-	r128_do_engine_reset( dev );
-
-	return 0;
-}
-
-int r128_do_cleanup_cce( drm_device_t *dev )
-{
-	if ( dev->dev_private ) {
-		drm_r128_private_t *dev_priv = dev->dev_private;
-
-		if ( !dev_priv->is_pci ) {
-			DRM_IOREMAPFREE( dev_priv->cce_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
-		} else {
-			if (!DRM(ati_pcigart_cleanup)( dev,
-						dev_priv->phys_pci_gart,
-						dev_priv->bus_pci_gart ))
-				DRM_ERROR( "failed to cleanup PCI GART!\n" );
-		}
-
-		DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int r128_cce_init( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_init_t init;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) )
-		return -EFAULT;
-
-	switch ( init.func ) {
-	case R128_INIT_CCE:
-		return r128_do_init_cce( dev, &init );
-	case R128_CLEANUP_CCE:
-		return r128_do_cleanup_cce( dev );
-	}
-
-	return -EINVAL;
-}
-
-int r128_cce_start( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
-		DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
-		return 0;
-	}
-
-	r128_do_cce_start( dev_priv );
-
-	return 0;
-}
-
-/* Stop the CCE.  The engine must have been idled before calling this
- * routine.
- */
-int r128_cce_stop( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_cce_stop_t stop;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) )
-		return -EFAULT;
-
-	/* Flush any pending CCE commands.  This ensures any outstanding
-	 * commands are exectuted by the engine before we turn it off.
-	 */
-	if ( stop.flush ) {
-		r128_do_cce_flush( dev_priv );
-	}
-
-	/* If we fail to make the engine go idle, we return an error
-	 * code so that the DRM ioctl wrapper can try again.
-	 */
-	if ( stop.idle ) {
-		ret = r128_do_cce_idle( dev_priv );
-		if ( ret < 0 ) return ret;
-	}
-
-	/* Finally, we can turn off the CCE.  If the engine isn't idle,
-	 * we will get some dropped triangles as they won't be fully
-	 * rendered before the CCE is shut down.
-	 */
-	r128_do_cce_stop( dev_priv );
-
-	/* Reset the engine */
-	r128_do_engine_reset( dev );
-
-	return 0;
-}
-
-/* Just reset the CCE ring.  Called as part of an X Server engine reset.
- */
-int r128_cce_reset( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	r128_do_cce_reset( dev_priv );
-
-	/* The CCE is no longer running after an engine reset */
-	dev_priv->cce_running = 0;
-
-	return 0;
-}
-
-int r128_cce_idle( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cce_running ) {
-		r128_do_cce_flush( dev_priv );
-	}
-
-	return r128_do_cce_idle( dev_priv );
-}
-
-int r128_engine_reset( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return r128_do_engine_reset( dev );
-}
-
-
-/* ================================================================
- * Fullscreen mode
- */
-
-static int r128_do_init_pageflip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv->crtc_offset =      R128_READ( R128_CRTC_OFFSET );
-	dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
-
-	R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL,
-		    dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
-
-	dev_priv->page_flipping = 1;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int r128_do_cleanup_pageflip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	R128_WRITE( R128_CRTC_OFFSET,      dev_priv->crtc_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
-
-	dev_priv->page_flipping = 0;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int r128_fullscreen( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_r128_fullscreen_t fs;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &fs, (drm_r128_fullscreen_t *)arg, sizeof(fs) ) )
-		return -EFAULT;
-
-	switch ( fs.func ) {
-	case R128_INIT_FULLSCREEN:
-		return r128_do_init_pageflip( dev );
-	case R128_CLEANUP_FULLSCREEN:
-		return r128_do_cleanup_pageflip( dev );
-	}
-
-	return -EINVAL;
-}
-
-
-/* ================================================================
- * Freelist management
- */
-#define R128_BUFFER_USED	0xffffffff
-#define R128_BUFFER_FREE	0
-
-#if 0
-static int r128_freelist_init( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_freelist_t *entry;
-	int i;
-
-	dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
-		return -ENOMEM;
-
-	memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
-	dev_priv->head->age = R128_BUFFER_USED;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-
-		entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( !entry ) return -ENOMEM;
-
-		entry->age = R128_BUFFER_FREE;
-		entry->buf = buf;
-		entry->prev = dev_priv->head;
-		entry->next = dev_priv->head->next;
-		if ( !entry->next )
-			dev_priv->tail = entry;
-
-		buf_priv->discard = 0;
-		buf_priv->dispatched = 0;
-		buf_priv->list_entry = entry;
-
-		dev_priv->head->next = entry;
-
-		if ( dev_priv->head->next )
-			dev_priv->head->next->prev = entry;
-	}
-
-	return 0;
-
-}
-#endif
-
-drm_buf_t *r128_freelist_get( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_buf_t *buf;
-	int i, t;
-
-	/* FIXME: Optimize -- use freelist code */
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-		if ( buf->pid == 0 )
-			return buf;
-	}
-
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-		u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
-
-		for ( i = 0 ; i < dma->buf_count ; i++ ) {
-			buf = dma->buflist[i];
-			buf_priv = buf->dev_private;
-			if ( buf->pending && buf_priv->age <= done_age ) {
-				/* The buffer has been processed, so it
-				 * can now be used.
-				 */
-				buf->pending = 0;
-				return buf;
-			}
-		}
-		udelay( 1 );
-	}
-
-	DRM_ERROR( "returning NULL!\n" );
-	return NULL;
-}
-
-void r128_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	int i;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		drm_buf_t *buf = dma->buflist[i];
-		drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-		buf_priv->age = 0;
-	}
-}
-
-
-/* ================================================================
- * CCE command submission
- */
-
-int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
-{
-	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		r128_update_ring_snapshot( ring );
-		if ( ring->space >= n )
-			return 0;
-		udelay( 1 );
-	}
-
-	/* FIXME: This is being ignored... */
-	DRM_ERROR( "failed!\n" );
-	return -EBUSY;
-}
-
-static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
-{
-	int i;
-	drm_buf_t *buf;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = r128_freelist_get( dev );
-		if ( !buf ) return -EAGAIN;
-
-		buf->pid = current->pid;
-
-		if ( copy_to_user( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
-			return -EFAULT;
-		if ( copy_to_user( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
-			return -EFAULT;
-
-		d->granted_count++;
-	}
-	return 0;
-}
-
-int r128_cce_buffers( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-	int ret = 0;
-	drm_dma_t d;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
-		return -EFAULT;
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   current->pid, d.send_count );
-		return -EINVAL;
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   current->pid, d.request_count, dma->buf_count );
-		return -EINVAL;
-	}
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		ret = r128_cce_get_buffers( dev, &d );
-	}
-
-	if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
-		return -EFAULT;
-
-	return ret;
-}
diff --git a/linux/r128_drm.h b/linux/r128_drm.h
deleted file mode 100644
index a8d23008..00000000
--- a/linux/r128_drm.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
- * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- *    Kevin E. Martin <martin@valinux.com>
- */
-
-#ifndef __R128_DRM_H__
-#define __R128_DRM_H__
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the X server file (r128_sarea.h)
- */
-#ifndef __R128_SAREA_DEFINES__
-#define __R128_SAREA_DEFINES__
-
-/* What needs to be changed for the current vertex buffer?
- */
-#define R128_UPLOAD_CONTEXT		0x001
-#define R128_UPLOAD_SETUP		0x002
-#define R128_UPLOAD_TEX0		0x004
-#define R128_UPLOAD_TEX1		0x008
-#define R128_UPLOAD_TEX0IMAGES		0x010
-#define R128_UPLOAD_TEX1IMAGES		0x020
-#define R128_UPLOAD_CORE		0x040
-#define R128_UPLOAD_MASKS		0x080
-#define R128_UPLOAD_WINDOW		0x100
-#define R128_UPLOAD_CLIPRECTS		0x200	/* handled client-side */
-#define R128_REQUIRE_QUIESCENCE		0x400
-#define R128_UPLOAD_ALL			0x7ff
-
-#define R128_FRONT			0x1
-#define R128_BACK			0x2
-#define R128_DEPTH			0x4
-
-/* Primitive types
- */
-#define R128_POINTS			0x1
-#define R128_LINES			0x2
-#define R128_LINE_STRIP			0x3
-#define R128_TRIANGLES			0x4
-#define R128_TRIANGLE_FAN		0x5
-#define R128_TRIANGLE_STRIP		0x6
-
-/* Vertex/indirect buffer size
- */
-#define R128_BUFFER_SIZE		16384
-
-/* Byte offsets for indirect buffer data
- */
-#define R128_INDEX_PRIM_OFFSET		20
-#define R128_HOSTDATA_BLIT_OFFSET	32
-
-/* Keep these small for testing.
- */
-#define R128_NR_SAREA_CLIPRECTS		12
-
-/* There are 2 heaps (local/AGP).  Each region within a heap is a
- *  minimum of 64k, and there are at most 64 of them per heap.
- */
-#define R128_LOCAL_TEX_HEAP		0
-#define R128_AGP_TEX_HEAP		1
-#define R128_NR_TEX_HEAPS		2
-#define R128_NR_TEX_REGIONS		64
-#define R128_LOG_TEX_GRANULARITY	16
-
-#define R128_NR_CONTEXT_REGS		12
-
-#define R128_MAX_TEXTURE_LEVELS		11
-#define R128_MAX_TEXTURE_UNITS		2
-
-#endif /* __R128_SAREA_DEFINES__ */
-
-typedef struct {
-	/* Context state - can be written in one large chunk */
-	unsigned int dst_pitch_offset_c;
-	unsigned int dp_gui_master_cntl_c;
-	unsigned int sc_top_left_c;
-	unsigned int sc_bottom_right_c;
-	unsigned int z_offset_c;
-	unsigned int z_pitch_c;
-	unsigned int z_sten_cntl_c;
-	unsigned int tex_cntl_c;
-	unsigned int misc_3d_state_cntl_reg;
-	unsigned int texture_clr_cmp_clr_c;
-	unsigned int texture_clr_cmp_msk_c;
-	unsigned int fog_color_c;
-
-	/* Texture state */
-	unsigned int tex_size_pitch_c;
-	unsigned int constant_color_c;
-
-	/* Setup state */
-	unsigned int pm4_vc_fpu_setup;
-	unsigned int setup_cntl;
-
-	/* Mask state */
-	unsigned int dp_write_mask;
-	unsigned int sten_ref_mask_c;
-	unsigned int plane_3d_mask_c;
-
-	/* Window state */
-	unsigned int window_xy_offset;
-
-	/* Core state */
-	unsigned int scale_3d_cntl;
-} drm_r128_context_regs_t;
-
-/* Setup registers for each texture unit
- */
-typedef struct {
-	unsigned int tex_cntl;
-	unsigned int tex_combine_cntl;
-	unsigned int tex_size_pitch;
-	unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
-	unsigned int tex_border_color;
-} drm_r128_texture_regs_t;
-
-
-typedef struct drm_r128_sarea {
-	/* The channel for communication of state information to the kernel
-	 * on firing a vertex buffer.
-	 */
-	drm_r128_context_regs_t context_state;
-	drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
-	unsigned int dirty;
-	unsigned int vertsize;
-	unsigned int vc_format;
-
-	/* The current cliprects, or a subset thereof.
-	 */
-	drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
-	unsigned int nbox;
-
-	/* Counters for client-side throttling of rendering clients.
-	 */
-	unsigned int last_frame;
-	unsigned int last_dispatch;
-
-	drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1];
-	int tex_age[R128_NR_TEX_HEAPS];
-	int ctx_owner;
-} drm_r128_sarea_t;
-
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmR128.h)
- */
-
-/* Rage 128 specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)
-#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)
-#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)
-#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)
-#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)
-#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)
-#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)
-#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)
-#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)
-#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)
-#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)
-#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)
-#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)
-#define DRM_IOCTL_R128_INDIRECT		DRM_IOWR(0x4f, drm_r128_indirect_t)
-#define DRM_IOCTL_R128_FULLSCREEN	DRM_IOW( 0x50, drm_r128_fullscreen_t)
-#define DRM_IOCTL_R128_CLEAR2		DRM_IOW( 0x51, drm_r128_clear2_t)
-
-typedef struct drm_r128_init {
-	enum {
-		R128_INIT_CCE    = 0x01,
-		R128_CLEANUP_CCE = 0x02
-	} func;
-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
-	int sarea_priv_offset;
-#else
-	unsigned long sarea_priv_offset;
-#endif
-	int is_pci;
-	int cce_mode;
-	int cce_secure;
-	int ring_size;
-	int usec_timeout;
-
-	unsigned int fb_bpp;
-	unsigned int front_offset, front_pitch;
-	unsigned int back_offset, back_pitch;
-	unsigned int depth_bpp;
-	unsigned int depth_offset, depth_pitch;
-	unsigned int span_offset;
-
-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
-	unsigned int fb_offset;
-	unsigned int mmio_offset;
-	unsigned int ring_offset;
-	unsigned int ring_rptr_offset;
-	unsigned int buffers_offset;
-	unsigned int agp_textures_offset;
-#else
-	unsigned long fb_offset;
-	unsigned long mmio_offset;
-	unsigned long ring_offset;
-	unsigned long ring_rptr_offset;
-	unsigned long buffers_offset;
-	unsigned long agp_textures_offset;
-#endif
-} drm_r128_init_t;
-
-typedef struct drm_r128_cce_stop {
-	int flush;
-	int idle;
-} drm_r128_cce_stop_t;
-
-typedef struct drm_r128_clear {
-	unsigned int flags;
-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
-	int x, y, w, h;
-#endif
-	unsigned int clear_color;
-	unsigned int clear_depth;
-#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
-	unsigned int color_mask;
-	unsigned int depth_mask;
-#endif
-} drm_r128_clear_t;
-
-typedef struct drm_r128_vertex {
-	int prim;
-	int idx;			/* Index of vertex buffer */
-	int count;			/* Number of vertices in buffer */
-	int discard;			/* Client finished with buffer? */
-} drm_r128_vertex_t;
-
-typedef struct drm_r128_indices {
-	int prim;
-	int idx;
-	int start;
-	int end;
-	int discard;			/* Client finished with buffer? */
-} drm_r128_indices_t;
-
-typedef struct drm_r128_blit {
-	int idx;
-	int pitch;
-	int offset;
-	int format;
-	unsigned short x, y;
-	unsigned short width, height;
-} drm_r128_blit_t;
-
-typedef struct drm_r128_depth {
-	enum {
-		R128_WRITE_SPAN		= 0x01,
-		R128_WRITE_PIXELS	= 0x02,
-		R128_READ_SPAN		= 0x03,
-		R128_READ_PIXELS	= 0x04
-	} func;
-	int n;
-	int *x;
-	int *y;
-	unsigned int *buffer;
-	unsigned char *mask;
-} drm_r128_depth_t;
-
-typedef struct drm_r128_stipple {
-	unsigned int *mask;
-} drm_r128_stipple_t;
-
-typedef struct drm_r128_indirect {
-	int idx;
-	int start;
-	int end;
-	int discard;
-} drm_r128_indirect_t;
-
-typedef struct drm_r128_fullscreen {
-	enum {
-		R128_INIT_FULLSCREEN    = 0x01,
-		R128_CLEANUP_FULLSCREEN = 0x02
-	} func;
-} drm_r128_fullscreen_t;
-
-#endif
diff --git a/linux/r128_drv.c b/linux/r128_drv.c
index 32180a30..e2e42690 100644
--- a/linux/r128_drv.c
+++ b/linux/r128_drv.c
@@ -37,45 +37,6 @@
 #include "r128_drv.h"
 #include "ati_pcigart.h"
 
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"r128"
-#define DRIVER_DESC		"ATI Rage 128"
-#define DRIVER_DATE		"20010917"
-
-#define DRIVER_MAJOR		2
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-
-#define DRIVER_IOCTLS							    \
-   [DRM_IOCTL_NR(DRM_IOCTL_DMA)]             = { r128_cce_buffers,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)]       = { r128_cce_init,     1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)]  = { r128_cce_start,    1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)]   = { r128_cce_stop,     1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)]  = { r128_cce_reset,    1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)]   = { r128_cce_idle,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)]      = { r128_engine_reset, 1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen,   1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)]       = { r128_cce_swap,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)]      = { r128_cce_clear,    1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)]     = { r128_cce_vertex,   1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)]    = { r128_cce_indices,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)]       = { r128_cce_blit,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)]      = { r128_cce_depth,    1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)]    = { r128_cce_stipple,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)]   = { r128_cce_indirect, 1, 1 },
-
-
-#if 0
-/* GH: Count data sent to card via ring or vertex/indirect buffers.
- */
-#define __HAVE_COUNTERS         3
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#endif
-
-
 #include "drm_agpsupport.h"
 #include "drm_auth.h"
 #include "drm_bufs.h"
@@ -83,26 +44,6 @@
 #include "drm_dma.h"
 #include "drm_drawable.h"
 #include "drm_drv.h"
-
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init r128_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", r128_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/r128_drv.h b/linux/r128_drv.h
deleted file mode 100644
index 0485deda..00000000
--- a/linux/r128_drv.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
- * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- *    Michel D�nzer <daenzerm@student.ethz.ch>
- */
-
-#ifndef __R128_DRV_H__
-#define __R128_DRV_H__
-
-#define GET_RING_HEAD(ring)		readl( (volatile u32 *) (ring)->head )
-#define SET_RING_HEAD(ring,val)		writel( (val), (volatile u32 *) (ring)->head )
-
-typedef struct drm_r128_freelist {
-   	unsigned int age;
-   	drm_buf_t *buf;
-   	struct drm_r128_freelist *next;
-   	struct drm_r128_freelist *prev;
-} drm_r128_freelist_t;
-
-typedef struct drm_r128_ring_buffer {
-	u32 *start;
-	u32 *end;
-	int size;
-	int size_l2qw;
-
-	volatile u32 *head;
-	u32 tail;
-	u32 tail_mask;
-	int space;
-
-	int high_mark;
-} drm_r128_ring_buffer_t;
-
-typedef struct drm_r128_private {
-	drm_r128_ring_buffer_t ring;
-	drm_r128_sarea_t *sarea_priv;
-
-	int cce_mode;
-	int cce_fifo_size;
-	int cce_running;
-
-   	drm_r128_freelist_t *head;
-   	drm_r128_freelist_t *tail;
-
-	int usec_timeout;
-	int is_pci;
-	unsigned long phys_pci_gart;
-	dma_addr_t bus_pci_gart;
-	unsigned long cce_buffers_offset;
-
-	atomic_t idle_count;
-
-	int page_flipping;
-	int current_page;
-	u32 crtc_offset;
-	u32 crtc_offset_cntl;
-
-	u32 color_fmt;
-	unsigned int front_offset;
-	unsigned int front_pitch;
-	unsigned int back_offset;
-	unsigned int back_pitch;
-
-	u32 depth_fmt;
-	unsigned int depth_offset;
-	unsigned int depth_pitch;
-	unsigned int span_offset;
-
-	u32 front_pitch_offset_c;
-	u32 back_pitch_offset_c;
-	u32 depth_pitch_offset_c;
-	u32 span_pitch_offset_c;
-
-	drm_map_t *sarea;
-	drm_map_t *fb;
-	drm_map_t *mmio;
-	drm_map_t *cce_ring;
-	drm_map_t *ring_rptr;
-	drm_map_t *buffers;
-	drm_map_t *agp_textures;
-} drm_r128_private_t;
-
-typedef struct drm_r128_buf_priv {
-	u32 age;
-	int prim;
-	int discard;
-	int dispatched;
-   	drm_r128_freelist_t *list_entry;
-} drm_r128_buf_priv_t;
-
-				/* r128_cce.c */
-extern int r128_cce_init( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int r128_cce_start( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int r128_cce_stop( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int r128_cce_reset( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int r128_cce_idle( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int r128_engine_reset( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int r128_fullscreen( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int r128_cce_buffers( struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg );
-
-extern void r128_freelist_reset( drm_device_t *dev );
-extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
-
-extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
-
-static inline void
-r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
-{
-	ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 )
-		ring->space += ring->size;
-}
-
-extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
-extern int r128_do_cleanup_cce( drm_device_t *dev );
-extern int r128_do_cleanup_pageflip( drm_device_t *dev );
-
-				/* r128_state.c */
-extern int r128_cce_clear( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int r128_cce_swap( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int r128_cce_vertex( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int r128_cce_indices( struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg );
-extern int r128_cce_blit( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int r128_cce_depth( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int r128_cce_stipple( struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg );
-extern int r128_cce_indirect( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-
-
-/* Register definitions, register access macros and drmAddMap constants
- * for Rage 128 kernel driver.
- */
-
-#define R128_AUX_SC_CNTL		0x1660
-#	define R128_AUX1_SC_EN			(1 << 0)
-#	define R128_AUX1_SC_MODE_OR		(0 << 1)
-#	define R128_AUX1_SC_MODE_NAND		(1 << 1)
-#	define R128_AUX2_SC_EN			(1 << 2)
-#	define R128_AUX2_SC_MODE_OR		(0 << 3)
-#	define R128_AUX2_SC_MODE_NAND		(1 << 3)
-#	define R128_AUX3_SC_EN			(1 << 4)
-#	define R128_AUX3_SC_MODE_OR		(0 << 5)
-#	define R128_AUX3_SC_MODE_NAND		(1 << 5)
-#define R128_AUX1_SC_LEFT		0x1664
-#define R128_AUX1_SC_RIGHT		0x1668
-#define R128_AUX1_SC_TOP		0x166c
-#define R128_AUX1_SC_BOTTOM		0x1670
-#define R128_AUX2_SC_LEFT		0x1674
-#define R128_AUX2_SC_RIGHT		0x1678
-#define R128_AUX2_SC_TOP		0x167c
-#define R128_AUX2_SC_BOTTOM		0x1680
-#define R128_AUX3_SC_LEFT		0x1684
-#define R128_AUX3_SC_RIGHT		0x1688
-#define R128_AUX3_SC_TOP		0x168c
-#define R128_AUX3_SC_BOTTOM		0x1690
-
-#define R128_BRUSH_DATA0		0x1480
-#define R128_BUS_CNTL			0x0030
-#	define R128_BUS_MASTER_DIS		(1 << 6)
-
-#define R128_CLOCK_CNTL_INDEX		0x0008
-#define R128_CLOCK_CNTL_DATA		0x000c
-#	define R128_PLL_WR_EN			(1 << 7)
-#define R128_CONSTANT_COLOR_C		0x1d34
-#define R128_CRTC_OFFSET		0x0224
-#define R128_CRTC_OFFSET_CNTL		0x0228
-#	define R128_CRTC_OFFSET_FLIP_CNTL	(1 << 16)
-
-#define R128_DP_GUI_MASTER_CNTL		0x146c
-#       define R128_GMC_SRC_PITCH_OFFSET_CNTL	(1    <<  0)
-#       define R128_GMC_DST_PITCH_OFFSET_CNTL	(1    <<  1)
-#	define R128_GMC_BRUSH_SOLID_COLOR	(13   <<  4)
-#	define R128_GMC_BRUSH_NONE		(15   <<  4)
-#	define R128_GMC_DST_16BPP		(4    <<  8)
-#	define R128_GMC_DST_24BPP		(5    <<  8)
-#	define R128_GMC_DST_32BPP		(6    <<  8)
-#       define R128_GMC_DST_DATATYPE_SHIFT	8
-#	define R128_GMC_SRC_DATATYPE_COLOR	(3    << 12)
-#	define R128_DP_SRC_SOURCE_MEMORY	(2    << 24)
-#	define R128_DP_SRC_SOURCE_HOST_DATA	(3    << 24)
-#	define R128_GMC_CLR_CMP_CNTL_DIS	(1    << 28)
-#	define R128_GMC_AUX_CLIP_DIS		(1    << 29)
-#	define R128_GMC_WR_MSK_DIS		(1    << 30)
-#	define R128_ROP3_S			0x00cc0000
-#	define R128_ROP3_P			0x00f00000
-#define R128_DP_WRITE_MASK		0x16cc
-#define R128_DST_PITCH_OFFSET_C		0x1c80
-#	define R128_DST_TILE			(1 << 31)
-
-#define R128_GEN_RESET_CNTL		0x00f0
-#	define R128_SOFT_RESET_GUI		(1 <<  0)
-
-#define R128_GUI_SCRATCH_REG0		0x15e0
-#define R128_GUI_SCRATCH_REG1		0x15e4
-#define R128_GUI_SCRATCH_REG2		0x15e8
-#define R128_GUI_SCRATCH_REG3		0x15ec
-#define R128_GUI_SCRATCH_REG4		0x15f0
-#define R128_GUI_SCRATCH_REG5		0x15f4
-
-#define R128_GUI_STAT			0x1740
-#	define R128_GUI_FIFOCNT_MASK		0x0fff
-#	define R128_GUI_ACTIVE			(1 << 31)
-
-#define R128_MCLK_CNTL			0x000f
-#	define R128_FORCE_GCP			(1 << 16)
-#	define R128_FORCE_PIPE3D_CP		(1 << 17)
-#	define R128_FORCE_RCP			(1 << 18)
-
-#define R128_PC_GUI_CTLSTAT		0x1748
-#define R128_PC_NGUI_CTLSTAT		0x0184
-#	define R128_PC_FLUSH_GUI		(3 << 0)
-#	define R128_PC_RI_GUI			(1 << 2)
-#	define R128_PC_FLUSH_ALL		0x00ff
-#	define R128_PC_BUSY			(1 << 31)
-
-#define R128_PCI_GART_PAGE		0x017c
-#define R128_PRIM_TEX_CNTL_C		0x1cb0
-
-#define R128_SCALE_3D_CNTL		0x1a00
-#define R128_SEC_TEX_CNTL_C		0x1d00
-#define R128_SEC_TEXTURE_BORDER_COLOR_C	0x1d3c
-#define R128_SETUP_CNTL			0x1bc4
-#define R128_STEN_REF_MASK_C		0x1d40
-
-#define R128_TEX_CNTL_C			0x1c9c
-#	define R128_TEX_CACHE_FLUSH		(1 << 23)
-
-#define R128_WAIT_UNTIL			0x1720
-#	define R128_EVENT_CRTC_OFFSET		(1 << 0)
-#define R128_WINDOW_XY_OFFSET		0x1bcc
-
-
-/* CCE registers
- */
-#define R128_PM4_BUFFER_OFFSET		0x0700
-#define R128_PM4_BUFFER_CNTL		0x0704
-#	define R128_PM4_MASK			(15 << 28)
-#	define R128_PM4_NONPM4			(0  << 28)
-#	define R128_PM4_192PIO			(1  << 28)
-#	define R128_PM4_192BM			(2  << 28)
-#	define R128_PM4_128PIO_64INDBM		(3  << 28)
-#	define R128_PM4_128BM_64INDBM		(4  << 28)
-#	define R128_PM4_64PIO_128INDBM		(5  << 28)
-#	define R128_PM4_64BM_128INDBM		(6  << 28)
-#	define R128_PM4_64PIO_64VCBM_64INDBM	(7  << 28)
-#	define R128_PM4_64BM_64VCBM_64INDBM	(8  << 28)
-#	define R128_PM4_64PIO_64VCPIO_64INDPIO	(15 << 28)
-
-#define R128_PM4_BUFFER_WM_CNTL		0x0708
-#	define R128_WMA_SHIFT			0
-#	define R128_WMB_SHIFT			8
-#	define R128_WMC_SHIFT			16
-#	define R128_WB_WM_SHIFT			24
-
-#define R128_PM4_BUFFER_DL_RPTR_ADDR	0x070c
-#define R128_PM4_BUFFER_DL_RPTR		0x0710
-#define R128_PM4_BUFFER_DL_WPTR		0x0714
-#	define R128_PM4_BUFFER_DL_DONE		(1 << 31)
-
-#define R128_PM4_VC_FPU_SETUP		0x071c
-
-#define R128_PM4_IW_INDOFF		0x0738
-#define R128_PM4_IW_INDSIZE		0x073c
-
-#define R128_PM4_STAT			0x07b8
-#	define R128_PM4_FIFOCNT_MASK		0x0fff
-#	define R128_PM4_BUSY			(1 << 16)
-#	define R128_PM4_GUI_ACTIVE		(1 << 31)
-
-#define R128_PM4_MICROCODE_ADDR		0x07d4
-#define R128_PM4_MICROCODE_RADDR	0x07d8
-#define R128_PM4_MICROCODE_DATAH	0x07dc
-#define R128_PM4_MICROCODE_DATAL	0x07e0
-
-#define R128_PM4_BUFFER_ADDR		0x07f0
-#define R128_PM4_MICRO_CNTL		0x07fc
-#	define R128_PM4_MICRO_FREERUN		(1 << 30)
-
-#define R128_PM4_FIFO_DATA_EVEN		0x1000
-#define R128_PM4_FIFO_DATA_ODD		0x1004
-
-
-/* CCE command packets
- */
-#define R128_CCE_PACKET0		0x00000000
-#define R128_CCE_PACKET1		0x40000000
-#define R128_CCE_PACKET2		0x80000000
-#define R128_CCE_PACKET3		0xC0000000
-#	define R128_CNTL_HOSTDATA_BLT		0x00009400
-#	define R128_CNTL_PAINT_MULTI		0x00009A00
-#	define R128_CNTL_BITBLT_MULTI		0x00009B00
-#	define R128_3D_RNDR_GEN_INDX_PRIM	0x00002300
-
-#define R128_CCE_PACKET_MASK		0xC0000000
-#define R128_CCE_PACKET_COUNT_MASK	0x3fff0000
-#define R128_CCE_PACKET0_REG_MASK	0x000007ff
-#define R128_CCE_PACKET1_REG0_MASK	0x000007ff
-#define R128_CCE_PACKET1_REG1_MASK	0x003ff800
-
-#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE		0x00000000
-#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT	0x00000001
-#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE		0x00000002
-#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE	0x00000003
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST	0x00000004
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN	0x00000005
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP	0x00000006
-#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2	0x00000007
-#define R128_CCE_VC_CNTL_PRIM_WALK_IND		0x00000010
-#define R128_CCE_VC_CNTL_PRIM_WALK_LIST		0x00000020
-#define R128_CCE_VC_CNTL_PRIM_WALK_RING		0x00000030
-#define R128_CCE_VC_CNTL_NUM_SHIFT		16
-
-#define R128_DATATYPE_CI8		2
-#define R128_DATATYPE_ARGB1555		3
-#define R128_DATATYPE_RGB565		4
-#define R128_DATATYPE_RGB888		5
-#define R128_DATATYPE_ARGB8888		6
-#define R128_DATATYPE_RGB332		7
-#define R128_DATATYPE_RGB8		9
-#define R128_DATATYPE_ARGB4444		15
-
-/* Constants */
-#define R128_AGP_OFFSET			0x02000000
-
-#define R128_WATERMARK_L		16
-#define R128_WATERMARK_M		8
-#define R128_WATERMARK_N		8
-#define R128_WATERMARK_K		128
-
-#define R128_MAX_USEC_TIMEOUT		100000	/* 100 ms */
-
-#define R128_LAST_FRAME_REG		R128_GUI_SCRATCH_REG0
-#define R128_LAST_DISPATCH_REG		R128_GUI_SCRATCH_REG1
-#define R128_MAX_VB_AGE			0x7fffffff
-#define R128_MAX_VB_VERTS		(0xffff)
-
-#define R128_RING_HIGH_MARK		128
-
-#define R128_PERFORMANCE_BOXES		0
-
-
-#define R128_BASE(reg)		((unsigned long)(dev_priv->mmio->handle))
-#define R128_ADDR(reg)		(R128_BASE( reg ) + reg)
-
-#define R128_READ(reg)		readl( (volatile u32 *) R128_ADDR(reg) )
-#define R128_WRITE(reg,val)	writel( (val), (volatile u32 *) R128_ADDR(reg) )
-
-#define R128_READ8(reg)		readb( (volatile u8 *) R128_ADDR(reg) )
-#define R128_WRITE8(reg,val)	writeb( (val), (volatile u8 *) R128_ADDR(reg) )
-
-#define R128_WRITE_PLL(addr,val)					\
-do {									\
-	R128_WRITE8(R128_CLOCK_CNTL_INDEX,				\
-		    ((addr) & 0x1f) | R128_PLL_WR_EN);			\
-	R128_WRITE(R128_CLOCK_CNTL_DATA, (val));			\
-} while (0)
-
-extern int R128_READ_PLL(drm_device_t *dev, int addr);
-
-
-#define CCE_PACKET0( reg, n )		(R128_CCE_PACKET0 |		\
-					 ((n) << 16) | ((reg) >> 2))
-#define CCE_PACKET1( reg0, reg1 )	(R128_CCE_PACKET1 |		\
-					 (((reg1) >> 2) << 11) | ((reg0) >> 2))
-#define CCE_PACKET2()			(R128_CCE_PACKET2)
-#define CCE_PACKET3( pkt, n )		(R128_CCE_PACKET3 |		\
-					 (pkt) | ((n) << 16))
-
-
-/* ================================================================
- * Misc helper macros
- */
-
-#define LOCK_TEST_WITH_RETURN( dev )					\
-do {									\
-	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
-	     dev->lock.pid != current->pid ) {				\
-		DRM_ERROR( "%s called without lock held\n",		\
-			   __FUNCTION__ );				\
-		return -EINVAL;						\
-	}								\
-} while (0)
-
-#define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;		\
-	if ( ring->space < ring->high_mark ) {				\
-		for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	\
-			r128_update_ring_snapshot( ring );		\
-			if ( ring->space >= ring->high_mark )		\
-				goto __ring_space_done;			\
-			udelay( 1 );					\
-		}							\
-		DRM_ERROR( "ring space check failed!\n" );		\
-		return -EBUSY;						\
-	}								\
- __ring_space_done:							\
-} while (0)
-
-#define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
-	if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) {		\
-		int __ret = r128_do_cce_idle( dev_priv );		\
-		if ( __ret < 0 ) return __ret;				\
-		sarea_priv->last_dispatch = 0;				\
-		r128_freelist_reset( dev );				\
-	}								\
-} while (0)
-
-#define R128_WAIT_UNTIL_PAGE_FLIPPED() do {				\
-	OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( R128_EVENT_CRTC_OFFSET );				\
-} while (0)
-
-
-/* ================================================================
- * Ring control
- */
-
-#if defined(__powerpc__)
-#define r128_flush_write_combine()	(void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define r128_flush_write_combine()	mb()
-#endif
-
-
-#define R128_VERBOSE	0
-
-#define RING_LOCALS							\
-	int write; unsigned int tail_mask; volatile u32 *ring;
-
-#define BEGIN_RING( n ) do {						\
-	if ( R128_VERBOSE ) {						\
-		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
-			   (n), __FUNCTION__ );				\
-	}								\
-	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
-		r128_wait_ring( dev_priv, (n) * sizeof(u32) );		\
-	}								\
-	dev_priv->ring.space -= (n) * sizeof(u32);			\
-	ring = dev_priv->ring.start;					\
-	write = dev_priv->ring.tail;					\
-	tail_mask = dev_priv->ring.tail_mask;				\
-} while (0)
-
-/* You can set this to zero if you want.  If the card locks up, you'll
- * need to keep this set.  It works around a bug in early revs of the
- * Rage 128 chipset, where the CCE would read 32 dwords past the end of
- * the ring buffer before wrapping around.
- */
-#define R128_BROKEN_CCE	1
-
-#define ADVANCE_RING() do {						\
-	if ( R128_VERBOSE ) {						\
-		DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",	\
-			  write, dev_priv->ring.tail );			\
-	}								\
-	if ( R128_BROKEN_CCE && write < 32 ) {				\
-		memcpy( dev_priv->ring.end,				\
-			dev_priv->ring.start,				\
-			write * sizeof(u32) );				\
-	}								\
-	r128_flush_write_combine();					\
-	dev_priv->ring.tail = write;					\
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write );			\
-} while (0)
-
-#define OUT_RING( x ) do {						\
-	if ( R128_VERBOSE ) {						\
-		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
-			   (unsigned int)(x), write );			\
-	}								\
-	ring[write++] = cpu_to_le32( x );				\
-	write &= tail_mask;						\
-} while (0)
-
-#endif /* __R128_DRV_H__ */
diff --git a/linux/r128_state.c b/linux/r128_state.c
deleted file mode 100644
index a5b925f5..00000000
--- a/linux/r128_state.c
+++ /dev/null
@@ -1,1595 +0,0 @@
-/* r128_state.c -- State support for r128 -*- linux-c -*-
- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "r128.h"
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-#include "drm.h"
-#include <linux/delay.h>
-
-
-/* ================================================================
- * CCE hardware state programming functions
- */
-
-static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
-				  drm_clip_rect_t *boxes, int count )
-{
-	u32 aux_sc_cntl = 0x00000000;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 17 );
-
-	if ( count >= 1 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
-		OUT_RING( boxes[0].x1 );
-		OUT_RING( boxes[0].x2 - 1 );
-		OUT_RING( boxes[0].y1 );
-		OUT_RING( boxes[0].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
-	}
-	if ( count >= 2 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) );
-		OUT_RING( boxes[1].x1 );
-		OUT_RING( boxes[1].x2 - 1 );
-		OUT_RING( boxes[1].y1 );
-		OUT_RING( boxes[1].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
-	}
-	if ( count >= 3 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) );
-		OUT_RING( boxes[2].x1 );
-		OUT_RING( boxes[2].x2 - 1 );
-		OUT_RING( boxes[2].y1 );
-		OUT_RING( boxes[2].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
-	}
-
-	OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) );
-	OUT_RING( aux_sc_cntl );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_core( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) );
-	OUT_RING( ctx->scale_3d_cntl );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_context( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 13 );
-
-	OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) );
-	OUT_RING( ctx->dst_pitch_offset_c );
-	OUT_RING( ctx->dp_gui_master_cntl_c );
-	OUT_RING( ctx->sc_top_left_c );
-	OUT_RING( ctx->sc_bottom_right_c );
-	OUT_RING( ctx->z_offset_c );
-	OUT_RING( ctx->z_pitch_c );
-	OUT_RING( ctx->z_sten_cntl_c );
-	OUT_RING( ctx->tex_cntl_c );
-	OUT_RING( ctx->misc_3d_state_cntl_reg );
-	OUT_RING( ctx->texture_clr_cmp_clr_c );
-	OUT_RING( ctx->texture_clr_cmp_msk_c );
-	OUT_RING( ctx->fog_color_c );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_setup( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 3 );
-
-	OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) );
-	OUT_RING( ctx->setup_cntl );
-	OUT_RING( ctx->pm4_vc_fpu_setup );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_masks( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 5 );
-
-	OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-	OUT_RING( ctx->dp_write_mask );
-
-	OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) );
-	OUT_RING( ctx->sten_ref_mask_c );
-	OUT_RING( ctx->plane_3d_mask_c );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_window( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) );
-	OUT_RING( ctx->window_xy_offset );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_tex0( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
-
-	OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
-			       2 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	OUT_RING( ctx->tex_size_pitch_c );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
-
-	OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) );
-	OUT_RING( ctx->constant_color_c );
-	OUT_RING( tex->tex_border_color );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_tex1( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
-
-	OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
-			       1 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
-
-	OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
-
-	ADVANCE_RING();
-}
-
-static inline void r128_emit_state( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
-
-	if ( dirty & R128_UPLOAD_CORE ) {
-		r128_emit_core( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_CORE;
-	}
-
-	if ( dirty & R128_UPLOAD_CONTEXT ) {
-		r128_emit_context( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & R128_UPLOAD_SETUP ) {
-		r128_emit_setup( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
-	}
-
-	if ( dirty & R128_UPLOAD_MASKS ) {
-		r128_emit_masks( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
-	}
-
-	if ( dirty & R128_UPLOAD_WINDOW ) {
-		r128_emit_window( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
-	}
-
-	if ( dirty & R128_UPLOAD_TEX0 ) {
-		r128_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
-	}
-
-	if ( dirty & R128_UPLOAD_TEX1 ) {
-		r128_emit_tex1( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
-	}
-
-	/* Turn off the texture cache flushing */
-	sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
-
-	sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
-}
-
-
-#if R128_PERFORMANCE_BOXES
-/* ================================================================
- * Performance monitoring functions
- */
-
-static void r128_clear_box( drm_r128_private_t *dev_priv,
-			    int x, int y, int w, int h,
-			    int r, int g, int b )
-{
-	u32 pitch, offset;
-	u32 fb_bpp, color;
-	RING_LOCALS;
-
-	switch ( dev_priv->fb_bpp ) {
-	case 16:
-		fb_bpp = R128_GMC_DST_16BPP;
-		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
-		break;
-	case 24:
-		fb_bpp = R128_GMC_DST_24BPP;
-		color = ((r << 16) | (g << 8) | b);
-		break;
-	case 32:
-		fb_bpp = R128_GMC_DST_32BPP;
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
-		break;
-	default:
-		return;
-	}
-
-	offset = dev_priv->back_offset;
-	pitch = dev_priv->back_pitch >> 3;
-
-	BEGIN_RING( 6 );
-
-	OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_SOLID_COLOR |
-		  fb_bpp |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_P |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_AUX_CLIP_DIS );
-
-	OUT_RING( (pitch << 21) | (offset >> 5) );
-	OUT_RING( color );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv )
-{
-	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
-		r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
-	} else {
-		atomic_set( &dev_priv->idle_count, 0 );
-	}
-}
-
-#endif
-
-
-/* ================================================================
- * CCE command dispatch functions
- */
-
-static void r128_print_dirty( const char *msg, unsigned int flags )
-{
-	DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
-		  msg,
-		  flags,
-		  (flags & R128_UPLOAD_CORE)        ? "core, " : "",
-		  (flags & R128_UPLOAD_CONTEXT)     ? "context, " : "",
-		  (flags & R128_UPLOAD_SETUP)       ? "setup, " : "",
-		  (flags & R128_UPLOAD_TEX0)        ? "tex0, " : "",
-		  (flags & R128_UPLOAD_TEX1)        ? "tex1, " : "",
-		  (flags & R128_UPLOAD_MASKS)       ? "masks, " : "",
-		  (flags & R128_UPLOAD_WINDOW)      ? "window, " : "",
-		  (flags & R128_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
-		  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
-}
-
-static void r128_cce_dispatch_clear( drm_device_t *dev,
-				     drm_r128_clear_t *clear )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	unsigned int flags = clear->flags;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
-		unsigned int tmp = flags;
-
-		flags &= ~(R128_FRONT | R128_BACK);
-		if ( tmp & R128_FRONT ) flags |= R128_BACK;
-		if ( tmp & R128_BACK )  flags |= R128_FRONT;
-	}
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   pbox[i].x1, pbox[i].y1, pbox[i].x2,
-			   pbox[i].y2, flags );
-
-		if ( flags & (R128_FRONT | R128_BACK) ) {
-			BEGIN_RING( 2 );
-
-			OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-			OUT_RING( clear->color_mask );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_FRONT ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
-
-			OUT_RING( dev_priv->front_pitch_offset_c );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_BACK ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
-
-			OUT_RING( dev_priv->back_pitch_offset_c );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_DEPTH ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( clear->clear_depth );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-	}
-}
-
-static void r128_cce_dispatch_swap( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-#if R128_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	r128_cce_performance_boxes( dev_priv );
-#endif
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		BEGIN_RING( 7 );
-
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_AUX_CLIP_DIS |
-			  R128_GMC_WR_MSK_DIS );
-
-		OUT_RING( dev_priv->back_pitch_offset_c );
-		OUT_RING( dev_priv->front_pitch_offset_c );
-
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
-
-		ADVANCE_RING();
-	}
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_dispatch_flip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
-
-#if R128_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	r128_cce_performance_boxes( dev_priv );
-#endif
-
-	BEGIN_RING( 4 );
-
-	R128_WAIT_UNTIL_PAGE_FLIPPED();
-	OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
-
-	if ( dev_priv->current_page == 0 ) {
-		OUT_RING( dev_priv->back_offset );
-		dev_priv->current_page = 1;
-	} else {
-		OUT_RING( dev_priv->front_offset );
-		dev_priv->current_page = 0;
-	}
-
-	ADVANCE_RING();
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_dispatch_vertex( drm_device_t *dev,
-				      drm_buf_t *buf )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int format = sarea_priv->vc_format;
-	int offset = buf->bus_address;
-	int size = buf->used;
-	int prim = buf_priv->prim;
-	int i = 0;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: buf=%d nbox=%d\n",
-		   __FUNCTION__, buf->idx, sarea_priv->nbox );
-
-	if ( 0 )
-		r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
-
-	if ( buf->used ) {
-		buf_priv->dispatched = 1;
-
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
-		}
-
-		do {
-			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
-			}
-
-			/* Emit the vertex buffer rendering commands */
-			BEGIN_RING( 5 );
-
-			OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-			OUT_RING( offset );
-			OUT_RING( size );
-			OUT_RING( format );
-			OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
-				  (size << R128_CCE_VC_CNTL_NUM_SHIFT) );
-
-			ADVANCE_RING();
-
-			i += 3;
-		} while ( i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		buf->used = 0;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-
-	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
-	sarea_priv->nbox = 0;
-}
-
-static void r128_cce_dispatch_indirect( drm_device_t *dev,
-					drm_buf_t *buf,
-					int start, int end )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
-
-	if ( start != end ) {
-		int offset = buf->bus_address + start;
-		int dwords = (end - start + 3) / sizeof(u32);
-
-		/* Indirect buffer data must be an even number of
-		 * dwords, so if we've been given an odd number we must
-		 * pad the data with a Type-2 CCE packet.
-		 */
-		if ( dwords & 1 ) {
-			u32 *data = (u32 *)
-				((char *)dev_priv->buffers->handle
-				 + buf->offset + start);
-			data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 );
-		}
-
-		buf_priv->dispatched = 1;
-
-		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
-
-		OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
-
-		ADVANCE_RING();
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the indirect buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		buf->used = 0;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-}
-
-static void r128_cce_dispatch_indices( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       int start, int end,
-				       int count )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int format = sarea_priv->vc_format;
-	int offset = dev_priv->buffers->offset - dev_priv->cce_buffers_offset;
-	int prim = buf_priv->prim;
-	u32 *data;
-	int dwords;
-	int i = 0;
-	RING_LOCALS;
-	DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
-
-	if ( 0 )
-		r128_print_dirty( "dispatch_indices", sarea_priv->dirty );
-
-	if ( start != end ) {
-		buf_priv->dispatched = 1;
-
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
-		}
-
-		dwords = (end - start + 3) / sizeof(u32);
-
-		data = (u32 *)((char *)dev_priv->buffers->handle
-			       + buf->offset + start);
-
-		data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM,
-						    dwords-2 ) );
-
-		data[1] = cpu_to_le32( offset );
-		data[2] = cpu_to_le32( R128_MAX_VB_VERTS );
-		data[3] = cpu_to_le32( format );
-		data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
-					(count << 16)) );
-
-		if ( count & 0x1 ) {
-#ifdef __LITTLE_ENDIAN
-			data[dwords-1] &= 0x0000ffff;
-#else
-			data[dwords-1] &= 0xffff0000;
-#endif
-		}
-
-		do {
-			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
-			}
-
-			r128_cce_dispatch_indirect( dev, buf, start, end );
-
-			i += 3;
-		} while ( i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-
-	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
-	sarea_priv->nbox = 0;
-}
-
-static int r128_cce_dispatch_blit( drm_device_t *dev,
-				   drm_r128_blit_t *blit )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	u32 *data;
-	int dword_shift, dwords;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The compiler won't optimize away a division by a variable,
-	 * even if the only legal values are powers of two.  Thus, we'll
-	 * use a shift instead.
-	 */
-	switch ( blit->format ) {
-	case R128_DATATYPE_ARGB8888:
-		dword_shift = 0;
-		break;
-	case R128_DATATYPE_ARGB1555:
-	case R128_DATATYPE_RGB565:
-	case R128_DATATYPE_ARGB4444:
-		dword_shift = 1;
-		break;
-	case R128_DATATYPE_CI8:
-	case R128_DATATYPE_RGB8:
-		dword_shift = 2;
-		break;
-	default:
-		DRM_ERROR( "invalid blit format %d\n", blit->format );
-		return -EINVAL;
-	}
-
-	/* Flush the pixel cache, and mark the contents as Read Invalid.
-	 * This ensures no pixel data gets mixed up with the texture
-	 * data from the host data blit, otherwise part of the texture
-	 * image may be corrupted.
-	 */
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
-
-	ADVANCE_RING();
-
-	/* Dispatch the indirect buffer.
-	 */
-	buf = dma->buflist[blit->idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
-		return -EINVAL;
-	}
-
-	buf_priv->discard = 1;
-
-	dwords = (blit->width * blit->height) >> dword_shift;
-
-	data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
-
-	data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) );
-	data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL |
-				R128_GMC_BRUSH_NONE |
-				(blit->format << 8) |
-				R128_GMC_SRC_DATATYPE_COLOR |
-				R128_ROP3_S |
-				R128_DP_SRC_SOURCE_HOST_DATA |
-				R128_GMC_CLR_CMP_CNTL_DIS |
-				R128_GMC_AUX_CLIP_DIS |
-				R128_GMC_WR_MSK_DIS) );
-
-	data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) );
-	data[3] = cpu_to_le32( 0xffffffff );
-	data[4] = cpu_to_le32( 0xffffffff );
-	data[5] = cpu_to_le32( (blit->y << 16) | blit->x );
-	data[6] = cpu_to_le32( (blit->height << 16) | blit->width );
-	data[7] = cpu_to_le32( dwords );
-
-	buf->used = (dwords + 8) * sizeof(u32);
-
-	r128_cce_dispatch_indirect( dev, buf, 0, buf->used );
-
-	/* Flush the pixel cache after the blit completes.  This ensures
-	 * the texture data is written out to memory before rendering
-	 * continues.
-	 */
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_FLUSH_GUI );
-
-	ADVANCE_RING();
-
-	return 0;
-}
-
-
-/* ================================================================
- * Tiled depth buffer management
- *
- * FIXME: These should all set the destination write mask for when we
- * have hardware stencil support.
- */
-
-static int r128_cce_dispatch_write_span( drm_device_t *dev,
-					 drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, x, y;
-	u32 *buffer;
-	u8 *mask;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
-		return -EFAULT;
-	}
-	if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
-		return -EFAULT;
-	}
-
-	buffer = kmalloc( depth->n * sizeof(u32), GFP_KERNEL );
-	if ( buffer == NULL )
-		return -ENOMEM;
-	if ( copy_from_user( buffer, depth->buffer,
-			     depth->n * sizeof(u32) ) ) {
-		kfree( buffer );
-		return -EFAULT;
-	}
-
-	if ( depth->mask ) {
-		mask = kmalloc( depth->n * sizeof(u8), GFP_KERNEL );
-		if ( mask == NULL ) {
-			kfree( buffer );
-			return -ENOMEM;
-		}
-		if ( copy_from_user( mask, depth->mask,
-				     depth->n * sizeof(u8) ) ) {
-			kfree( buffer );
-			kfree( mask );
-			return -EFAULT;
-		}
-
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
-
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
-
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
-
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (1 << 16) | 1 );
-
-				ADVANCE_RING();
-			}
-		}
-
-		kfree( mask );
-	} else {
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (1 << 16) | 1 );
-
-			ADVANCE_RING();
-		}
-	}
-
-	kfree( buffer );
-
-	return 0;
-}
-
-static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
-					   drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, *x, *y;
-	u32 *buffer;
-	u8 *mask;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-
-	x = kmalloc( count * sizeof(*x), GFP_KERNEL );
-	if ( x == NULL ) {
-		return -ENOMEM;
-	}
-	y = kmalloc( count * sizeof(*y), GFP_KERNEL );
-	if ( y == NULL ) {
-		kfree( x );
-		return -ENOMEM;
-	}
-	if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
-		kfree( x );
-		kfree( y );
-		return -EFAULT;
-	}
-	if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
-		kfree( x );
-		kfree( y );
-		return -EFAULT;
-	}
-
-	buffer = kmalloc( depth->n * sizeof(u32), GFP_KERNEL );
-	if ( buffer == NULL ) {
-		kfree( x );
-		kfree( y );
-		return -ENOMEM;
-	}
-	if ( copy_from_user( buffer, depth->buffer,
-			     depth->n * sizeof(u32) ) ) {
-		kfree( x );
-		kfree( y );
-		kfree( buffer );
-		return -EFAULT;
-	}
-
-	if ( depth->mask ) {
-		mask = kmalloc( depth->n * sizeof(u8), GFP_KERNEL );
-		if ( mask == NULL ) {
-			kfree( x );
-			kfree( y );
-			kfree( buffer );
-			return -ENOMEM;
-		}
-		if ( copy_from_user( mask, depth->mask,
-				     depth->n * sizeof(u8) ) ) {
-			kfree( x );
-			kfree( y );
-			kfree( buffer );
-			kfree( mask );
-			return -EFAULT;
-		}
-
-		for ( i = 0 ; i < count ; i++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
-
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
-
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
-
-				OUT_RING( (x[i] << 16) | y[i] );
-				OUT_RING( (1 << 16) | 1 );
-
-				ADVANCE_RING();
-			}
-		}
-
-		kfree( mask );
-	} else {
-		for ( i = 0 ; i < count ; i++ ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
-
-			OUT_RING( (x[i] << 16) | y[i] );
-			OUT_RING( (1 << 16) | 1 );
-
-			ADVANCE_RING();
-		}
-	}
-
-	kfree( x );
-	kfree( y );
-	kfree( buffer );
-
-	return 0;
-}
-
-static int r128_cce_dispatch_read_span( drm_device_t *dev,
-					drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, x, y;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( copy_from_user( &x, depth->x, sizeof(x) ) ) {
-		return -EFAULT;
-	}
-	if ( copy_from_user( &y, depth->y, sizeof(y) ) ) {
-		return -EFAULT;
-	}
-
-	BEGIN_RING( 7 );
-
-	OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-	OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-		  R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_NONE |
-		  (dev_priv->depth_fmt << 8) |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_S |
-		  R128_DP_SRC_SOURCE_MEMORY |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_WR_MSK_DIS );
-
-	OUT_RING( dev_priv->depth_pitch_offset_c );
-	OUT_RING( dev_priv->span_pitch_offset_c );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (0 << 16) | 0 );
-	OUT_RING( (count << 16) | 1 );
-
-	ADVANCE_RING();
-
-	return 0;
-}
-
-static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
-					  drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, *x, *y;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( count > dev_priv->depth_pitch ) {
-		count = dev_priv->depth_pitch;
-	}
-
-	x = kmalloc( count * sizeof(*x), GFP_KERNEL );
-	if ( x == NULL ) {
-		return -ENOMEM;
-	}
-	y = kmalloc( count * sizeof(*y), GFP_KERNEL );
-	if ( y == NULL ) {
-		kfree( x );
-		return -ENOMEM;
-	}
-	if ( copy_from_user( x, depth->x, count * sizeof(int) ) ) {
-		kfree( x );
-		kfree( y );
-		return -EFAULT;
-	}
-	if ( copy_from_user( y, depth->y, count * sizeof(int) ) ) {
-		kfree( x );
-		kfree( y );
-		return -EFAULT;
-	}
-
-	for ( i = 0 ; i < count ; i++ ) {
-		BEGIN_RING( 7 );
-
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->depth_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_WR_MSK_DIS );
-
-		OUT_RING( dev_priv->depth_pitch_offset_c );
-		OUT_RING( dev_priv->span_pitch_offset_c );
-
-		OUT_RING( (x[i] << 16) | y[i] );
-		OUT_RING( (i << 16) | 0 );
-		OUT_RING( (1 << 16) | 1 );
-
-		ADVANCE_RING();
-	}
-
-	kfree( x );
-	kfree( y );
-
-	return 0;
-}
-
-
-/* ================================================================
- * Polygon stipple
- */
-
-static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 33 );
-
-	OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
-	}
-
-	ADVANCE_RING();
-}
-
-
-/* ================================================================
- * IOCTL functions
- */
-
-int r128_cce_clear( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_clear_t clear;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &clear, (drm_r128_clear_t *) arg,
-			     sizeof(clear) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
-
-	r128_cce_dispatch_clear( dev, &clear );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
-
-	return 0;
-}
-
-int r128_cce_swap( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
-
-	if ( !dev_priv->page_flipping ) {
-		r128_cce_dispatch_swap( dev );
-		dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
-						R128_UPLOAD_MASKS);
-	} else {
-		r128_cce_dispatch_flip( dev );
-	}
-
-	return 0;
-}
-
-int r128_cce_vertex( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_vertex_t vertex;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &vertex, (drm_r128_vertex_t *)arg,
-			     sizeof(vertex) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
-		   __FUNCTION__, current->pid,
-		   vertex.idx, vertex.count, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		return -EINVAL;
-	}
-
-	buf->used = vertex.count;
-	buf_priv->prim = vertex.prim;
-	buf_priv->discard = vertex.discard;
-
-	r128_cce_dispatch_vertex( dev, buf );
-
-	return 0;
-}
-
-int r128_cce_indices( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_indices_t elts;
-	int count;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &elts, (drm_r128_indices_t *)arg,
-			     sizeof(elts) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n",
-		   __FUNCTION__, current->pid,
-		   elts.idx, elts.start, elts.end, elts.discard );
-
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-	if ( elts.prim < 0 ||
-	     elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[elts.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
-		return -EINVAL;
-	}
-
-	count = (elts.end - elts.start) / sizeof(u16);
-	elts.start -= R128_INDEX_PRIM_OFFSET;
-
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
-		return -EINVAL;
-	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
-		return -EINVAL;
-	}
-
-	buf->used = elts.end;
-	buf_priv->prim = elts.prim;
-	buf_priv->discard = elts.discard;
-
-	r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
-
-	return 0;
-}
-
-int r128_cce_blit( struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_blit_t blit;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &blit, (drm_r128_blit_t *)arg,
-			     sizeof(blit) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: pid=%d index=%d\n",
-		   __FUNCTION__, current->pid, blit.idx );
-
-	if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   blit.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	return r128_cce_dispatch_blit( dev, &blit );
-}
-
-int r128_cce_depth( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_depth_t depth;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &depth, (drm_r128_depth_t *)arg,
-			     sizeof(depth) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	switch ( depth.func ) {
-	case R128_WRITE_SPAN:
-		return r128_cce_dispatch_write_span( dev, &depth );
-	case R128_WRITE_PIXELS:
-		return r128_cce_dispatch_write_pixels( dev, &depth );
-	case R128_READ_SPAN:
-		return r128_cce_dispatch_read_span( dev, &depth );
-	case R128_READ_PIXELS:
-		return r128_cce_dispatch_read_pixels( dev, &depth );
-	}
-
-	return -EINVAL;
-}
-
-int r128_cce_stipple( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_stipple_t stipple;
-	u32 mask[32];
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &stipple, (drm_r128_stipple_t *)arg,
-			     sizeof(stipple) ) )
-		return -EFAULT;
-
-	if ( copy_from_user( &mask, stipple.mask,
-			     32 * sizeof(u32) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	r128_cce_dispatch_stipple( dev, mask );
-
-	return 0;
-}
-
-int r128_cce_indirect( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_indirect_t indirect;
-#if 0
-	RING_LOCALS;
-#endif
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &indirect, (drm_r128_indirect_t *)arg,
-			     sizeof(indirect) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
-
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-
-	buf = dma->buflist[indirect.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
-		return -EINVAL;
-	}
-
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf->used = indirect.end;
-	buf_priv->discard = indirect.discard;
-
-#if 0
-	/* Wait for the 3D stream to idle before the indirect buffer
-	 * containing 2D acceleration commands is processed.
-	 */
-	BEGIN_RING( 2 );
-	RADEON_WAIT_UNTIL_3D_IDLE();
-	ADVANCE_RING();
-#endif
-
-	/* Dispatch the indirect buffer full of commands from the
-	 * X server.  This is insecure and is thus only available to
-	 * privileged clients.
-	 */
-	r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end );
-
-	return 0;
-}
diff --git a/linux/radeon.h b/linux/radeon.h
deleted file mode 100644
index 0fdeb82a..00000000
--- a/linux/radeon.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* radeon.h -- ATI Radeon DRM template customization -*- linux-c -*-
- * Created: Wed Feb 14 17:07:34 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_H__
-#define __RADEON_H__
-
-/* This remains constant for all DRM template files.
- */
-#define DRM(x) radeon_##x
-
-/* General customization:
- */
-#define __HAVE_AGP		1
-#define __MUST_HAVE_AGP		0
-#define __HAVE_MTRR		1
-#define __HAVE_CTX_BITMAP	1
-#define __HAVE_SG		1
-#define __HAVE_PCI_DMA		1
-
-/* Driver customization:
- */
-#define DRIVER_PRERELEASE() do {					\
-	if ( dev->dev_private ) {					\
-		drm_radeon_private_t *dev_priv = dev->dev_private;	\
-		if ( dev_priv->page_flipping ) {			\
-			radeon_do_cleanup_pageflip( dev );		\
-		}							\
-	}								\
-} while (0)
-
-#define DRIVER_PRETAKEDOWN() do {					\
-	if ( dev->dev_private ) radeon_do_cleanup_cp( dev );		\
-} while (0)
-
-/* DMA customization:
- */
-#define __HAVE_DMA		1
-
-#if 0
-/* GH: Remove this for now... */
-#define __HAVE_DMA_QUIESCENT	1
-#define DRIVER_DMA_QUIESCENT() do {					\
-	drm_radeon_private_t *dev_priv = dev->dev_private;		\
-	return radeon_do_cp_idle( dev_priv );				\
-} while (0)
-#endif
-
-/* Buffer customization:
- */
-#define DRIVER_BUF_PRIV_T	drm_radeon_buf_priv_t
-
-#define DRIVER_AGP_BUFFERS_MAP( dev )					\
-	((drm_radeon_private_t *)((dev)->dev_private))->buffers
-
-#endif
diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
deleted file mode 100644
index 9428290b..00000000
--- a/linux/radeon_cp.c
+++ /dev/null
@@ -1,1590 +0,0 @@
-/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "radeon.h"
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-
-#include <linux/interrupt.h>	/* For task queue support */
-#include <linux/delay.h>
-
-#define RADEON_FIFO_DEBUG	0
-
-#if defined(__alpha__) || defined(__powerpc__)
-# define PCIGART_ENABLED
-#else
-# undef PCIGART_ENABLED
-#endif
-
-
-/* CP microcode (from ATI) */
-static u32 R200_cp_microcode[][2] = {
-	{ 0x21007000, 0000000000 },        
-	{ 0x20007000, 0000000000 }, 
-	{ 0x000000ab, 0x00000004 },
-	{ 0x000000af, 0x00000004 },
-	{ 0x66544a49, 0000000000 },
-	{ 0x49494174, 0000000000 },
-	{ 0x54517d83, 0000000000 },
-	{ 0x498d8b64, 0000000000 },
-	{ 0x49494949, 0000000000 },
-	{ 0x49da493c, 0000000000 },
-	{ 0x49989898, 0000000000 },
-	{ 0xd34949d5, 0000000000 },
-	{ 0x9dc90e11, 0000000000 },
-	{ 0xce9b9b9b, 0000000000 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x352e232c, 0000000000 },
-	{ 0x00000013, 0x00000004 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x352e272c, 0000000000 },
-	{ 0x000f0001, 0x00000016 },
-	{ 0x3239362f, 0000000000 },
-	{ 0x000077ef, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000020, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00000016, 0x00000004 },
-	{ 0x0003802a, 0x00000002 },
-	{ 0x040067e0, 0x00000002 },
-	{ 0x00000016, 0x00000004 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000037e1, 0x00000002 },
-	{ 0x040067e1, 0x00000006 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x000077e1, 0x00000002 },
-	{ 0x000077e1, 0x00000006 },
-	{ 0xffffffff, 0000000000 },
-	{ 0x10000000, 0000000000 },
-	{ 0x0003802a, 0x00000002 },
-	{ 0x040067e0, 0x00000006 },
-	{ 0x00007675, 0x00000002 },
-	{ 0x00007676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x04002676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0000002e, 0x00000018 },
-	{ 0x0000002e, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x01605000, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00098000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x64c0603d, 0x00000004 },
-	{ 0x00080000, 0x00000016 },
-	{ 0000000000, 0000000000 },
-	{ 0x0400251d, 0x00000002 },
-	{ 0x00007580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x04002580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x00000046, 0x00000004 },
-	{ 0x00005000, 0000000000 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x00019000, 0x00000002 },
-	{ 0x00011055, 0x00000014 },
-	{ 0x00000055, 0x00000012 },
-	{ 0x0400250f, 0x00000002 },
-	{ 0x0000504a, 0x00000004 },
-	{ 0x00007565, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000051, 0x00000004 },
-	{ 0x01e655b4, 0x00000002 },
-	{ 0x4401b0dc, 0x00000002 },
-	{ 0x01c110dc, 0x00000002 },
-	{ 0x2666705d, 0x00000018 },
-	{ 0x040c2565, 0x00000002 },
-	{ 0x0000005d, 0x00000018 },
-	{ 0x04002564, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000054, 0x00000004 },
-	{ 0x00401060, 0x00000008 },
-	{ 0x00101000, 0x00000002 },
-	{ 0x000d80ff, 0x00000002 },
-	{ 0x00800063, 0x00000008 },
-	{ 0x000f9000, 0x00000002 },
-	{ 0x000e00ff, 0x00000002 },
-	{ 0000000000, 0x00000006 },
-	{ 0x00000080, 0x00000018 },
-	{ 0x00000054, 0x00000004 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00009000, 0x00000002 },
-	{ 0x00041000, 0x00000002 },
-	{ 0x0c00350e, 0x00000002 },
-	{ 0x00049000, 0x00000002 },
-	{ 0x00051000, 0x00000002 },
-	{ 0x01e785f8, 0x00000002 },
-	{ 0x00200000, 0x00000002 },
-	{ 0x00600073, 0x0000000c },
-	{ 0x00007563, 0x00000002 },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x20007068, 0x00000004 },
-	{ 0x00005068, 0x00000004 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00007577, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x0000750f, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00600076, 0x0000000c },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x000075f8, 0x00000002 },
-	{ 0x00000076, 0x00000004 },
-	{ 0x000a750e, 0x00000002 },
-	{ 0x0020750f, 0x00000002 },
-	{ 0x00600079, 0x00000004 },
-	{ 0x00007570, 0x00000002 },
-	{ 0x00007571, 0x00000002 },
-	{ 0x00007572, 0x00000006 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00007568, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000084, 0x0000000c },
-	{ 0x00058000, 0x00000002 },
-	{ 0x0c607562, 0x00000002 },
-	{ 0x00000086, 0x00000004 },
-	{ 0x00600085, 0x00000004 },
-	{ 0x400070dd, 0000000000 },
-	{ 0x000380dd, 0x00000002 },
-	{ 0x00000093, 0x0000001c },
-	{ 0x00065095, 0x00000018 },
-	{ 0x040025bb, 0x00000002 },
-	{ 0x00061096, 0x00000018 },
-	{ 0x040075bc, 0000000000 },
-	{ 0x000075bb, 0x00000002 },
-	{ 0x000075bc, 0000000000 },
-	{ 0x00090000, 0x00000006 },
-	{ 0x00090000, 0x00000002 },
-	{ 0x000d8002, 0x00000006 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x01665000, 0x00000002 },
-	{ 0x000a0000, 0x00000002 },
-	{ 0x000671cc, 0x00000002 },
-	{ 0x0286f1cd, 0x00000002 },
-	{ 0x000000a3, 0x00000010 },
-	{ 0x21007000, 0000000000 },
-	{ 0x000000aa, 0x0000001c },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000a0000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x000b0000, 0x00000002 },
-	{ 0x38067000, 0x00000002 },
-	{ 0x000a00a6, 0x00000004 },
-	{ 0x20007000, 0000000000 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20077000, 0x00000002 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20007000, 0000000000 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0120751b, 0x00000002 },
-	{ 0x8040750a, 0x00000002 },
-	{ 0x8040750b, 0x00000002 },
-	{ 0x00110000, 0x00000002 },
-	{ 0x000380dd, 0x00000002 },
-	{ 0x000000bd, 0x0000001c },
-	{ 0x00061096, 0x00000018 },
-	{ 0x844075bd, 0x00000002 },
-	{ 0x00061095, 0x00000018 },
-	{ 0x840075bb, 0x00000002 },
-	{ 0x00061096, 0x00000018 },
-	{ 0x844075bc, 0x00000002 },
-	{ 0x000000c0, 0x00000004 },
-	{ 0x804075bd, 0x00000002 },
-	{ 0x800075bb, 0x00000002 },
-	{ 0x804075bc, 0x00000002 },
-	{ 0x00108000, 0x00000002 },
-	{ 0x01400000, 0x00000002 },
-	{ 0x006000c4, 0x0000000c },
-	{ 0x20c07000, 0x00000020 },
-	{ 0x000000c6, 0x00000012 },
-	{ 0x00800000, 0x00000006 },
-	{ 0x0080751d, 0x00000006 },
-	{ 0x000025bb, 0x00000002 },
-	{ 0x000040c0, 0x00000004 },
-	{ 0x0000775c, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460275d, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x00007999, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460299b, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x01e00830, 0x00000002 },
-	{ 0x21007000, 0000000000 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00038042, 0x00000002 },
-	{ 0x040025e0, 0x00000002 },
-	{ 0x000075e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000380d9, 0x00000002 },
-	{ 0x04007394, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-};
-
-
-static u32 radeon_cp_microcode[][2] = {
-	{ 0x21007000, 0000000000 },
-	{ 0x20007000, 0000000000 },
-	{ 0x000000b4, 0x00000004 },
-	{ 0x000000b8, 0x00000004 },
-	{ 0x6f5b4d4c, 0000000000 },
-	{ 0x4c4c427f, 0000000000 },
-	{ 0x5b568a92, 0000000000 },
-	{ 0x4ca09c6d, 0000000000 },
-	{ 0xad4c4c4c, 0000000000 },
-	{ 0x4ce1af3d, 0000000000 },
-	{ 0xd8afafaf, 0000000000 },
-	{ 0xd64c4cdc, 0000000000 },
-	{ 0x4cd10d10, 0000000000 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f242d, 0000000000 },
-	{ 0x00000012, 0x00000004 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f282d, 0000000000 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x000f0001, 0x00000016 },
-	{ 0x333a3730, 0000000000 },
-	{ 0x000077ef, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00000017, 0x00000004 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000002 },
-	{ 0x00000017, 0x00000004 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000037e1, 0x00000002 },
-	{ 0x040067e1, 0x00000006 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x000077e1, 0x00000002 },
-	{ 0x000077e1, 0x00000006 },
-	{ 0xffffffff, 0000000000 },
-	{ 0x10000000, 0000000000 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000006 },
-	{ 0x00007675, 0x00000002 },
-	{ 0x00007676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0003802c, 0x00000002 },
-	{ 0x04002676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x00000030, 0x00000018 },
-	{ 0x00000030, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x01605000, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00098000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x64c0603e, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00080000, 0x00000016 },
-	{ 0000000000, 0000000000 },
-	{ 0x0400251d, 0x00000002 },
-	{ 0x00007580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x04002580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x00000049, 0x00000004 },
-	{ 0x00005000, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x00019000, 0x00000002 },
-	{ 0x00011055, 0x00000014 },
-	{ 0x00000055, 0x00000012 },
-	{ 0x0400250f, 0x00000002 },
-	{ 0x0000504f, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007565, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000058, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x01e655b4, 0x00000002 },
-	{ 0x4401b0e4, 0x00000002 },
-	{ 0x01c110e4, 0x00000002 },
-	{ 0x26667066, 0x00000018 },
-	{ 0x040c2565, 0x00000002 },
-	{ 0x00000066, 0x00000018 },
-	{ 0x04002564, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x0000005d, 0x00000004 },
-	{ 0x00401069, 0x00000008 },
-	{ 0x00101000, 0x00000002 },
-	{ 0x000d80ff, 0x00000002 },
-	{ 0x0080006c, 0x00000008 },
-	{ 0x000f9000, 0x00000002 },
-	{ 0x000e00ff, 0x00000002 },
-	{ 0000000000, 0x00000006 },
-	{ 0x0000008f, 0x00000018 },
-	{ 0x0000005b, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00009000, 0x00000002 },
-	{ 0x00041000, 0x00000002 },
-	{ 0x0c00350e, 0x00000002 },
-	{ 0x00049000, 0x00000002 },
-	{ 0x00051000, 0x00000002 },
-	{ 0x01e785f8, 0x00000002 },
-	{ 0x00200000, 0x00000002 },
-	{ 0x0060007e, 0x0000000c },
-	{ 0x00007563, 0x00000002 },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x20007073, 0x00000004 },
-	{ 0x00005073, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00007577, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x0000750f, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00600083, 0x0000000c },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x000075f8, 0x00000002 },
-	{ 0x00000083, 0x00000004 },
-	{ 0x000a750e, 0x00000002 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x0020750f, 0x00000002 },
-	{ 0x00600086, 0x00000004 },
-	{ 0x00007570, 0x00000002 },
-	{ 0x00007571, 0x00000002 },
-	{ 0x00007572, 0x00000006 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00007568, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000095, 0x0000000c },
-	{ 0x00058000, 0x00000002 },
-	{ 0x0c607562, 0x00000002 },
-	{ 0x00000097, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00600096, 0x00000004 },
-	{ 0x400070e5, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000a8, 0x0000001c },
-	{ 0x000650aa, 0x00000018 },
-	{ 0x040025bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x040075bc, 0000000000 },
-	{ 0x000075bb, 0x00000002 },
-	{ 0x000075bc, 0000000000 },
-	{ 0x00090000, 0x00000006 },
-	{ 0x00090000, 0x00000002 },
-	{ 0x000d8002, 0x00000006 },
-	{ 0x00007832, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x00007820, 0x00000002 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20077000, 0x00000002 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20007000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0120751b, 0x00000002 },
-	{ 0x8040750a, 0x00000002 },
-	{ 0x8040750b, 0x00000002 },
-	{ 0x00110000, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000c6, 0x0000001c },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bd, 0x00000002 },
-	{ 0x000610aa, 0x00000018 },
-	{ 0x840075bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bc, 0x00000002 },
-	{ 0x000000c9, 0x00000004 },
-	{ 0x804075bd, 0x00000002 },
-	{ 0x800075bb, 0x00000002 },
-	{ 0x804075bc, 0x00000002 },
-	{ 0x00108000, 0x00000002 },
-	{ 0x01400000, 0x00000002 },
-	{ 0x006000cd, 0x0000000c },
-	{ 0x20c07000, 0x00000020 },
-	{ 0x000000cf, 0x00000012 },
-	{ 0x00800000, 0x00000006 },
-	{ 0x0080751d, 0x00000006 },
-	{ 0000000000, 0000000000 },
-	{ 0x0000775c, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460275d, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x01e00830, 0x00000002 },
-	{ 0x21007000, 0000000000 },
-	{ 0x6464614d, 0000000000 },
-	{ 0x69687420, 0000000000 },
-	{ 0x00000073, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380d0, 0x00000002 },
-	{ 0x040025e0, 0x00000002 },
-	{ 0x000075e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000380e0, 0x00000002 },
-	{ 0x04002394, 0x00000002 },
-	{ 0x00005000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00000008, 0000000000 },
-	{ 0x00000004, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-};
-
-
-int RADEON_READ_PLL(drm_device_t *dev, int addr)
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-
-	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
-}
-
-#if RADEON_FIFO_DEBUG
-static void radeon_status( drm_radeon_private_t *dev_priv )
-{
-	printk( "%s:\n", __FUNCTION__ );
-	printk( "RBBM_STATUS = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
-	printk( "CP_RB_RTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
-	printk( "CP_RB_WTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
-	printk( "AIC_CNTL = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
-	printk( "AIC_STAT = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
-	printk( "AIC_PT_BASE = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
-	printk( "TLB_ADDR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
-	printk( "TLB_DATA = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
-}
-#endif
-
-
-/* ================================================================
- * Engine, FIFO control
- */
-
-static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
-{
-	u32 tmp;
-	int i;
-
-	tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
-	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
-	RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
-		       & RADEON_RB2D_DC_BUSY) ) {
-			return 0;
-		}
-		udelay( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	return -EBUSY;
-}
-
-static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
-				    int entries )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
-			      & RADEON_RBBM_FIFOCNT_MASK );
-		if ( slots >= entries ) return 0;
-		udelay( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	return -EBUSY;
-}
-
-static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
-{
-	int i, ret;
-
-	ret = radeon_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret < 0 ) return ret;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RBBM_STATUS )
-		       & RADEON_RBBM_ACTIVE) ) {
-			radeon_do_pixcache_flush( dev_priv );
-			return 0;
-		}
-		udelay( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	return -EBUSY;
-}
-
-
-/* ================================================================
- * CP control, initialization
- */
-
-/* Load the microcode for the CP */
-static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
-{
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
-
-	if (dev_priv->is_r200)
-	{
-		DRM_INFO("Loading R200 Microcode\n");
-		for ( i = 0 ; i < 256 ; i++ ) 
-		{
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
-				      R200_cp_microcode[i][1] );
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
-				      R200_cp_microcode[i][0] );
-		}
-	}
-	else
-	{
-		for ( i = 0 ; i < 256 ; i++ ) {
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
-				      radeon_cp_microcode[i][1] );
-			RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
-				      radeon_cp_microcode[i][0] );
-		}
-	}
-}
-
-/* Flush any pending commands to the CP.  This should only be used just
- * prior to a wait for idle, as it informs the engine that the command
- * stream is ending.
- */
-static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-#if 0
-	u32 tmp;
-
-	tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
-	RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
-#endif
-}
-
-/* Wait for the CP to go idle.
- */
-int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 6 );
-
-	RADEON_PURGE_CACHE();
-	RADEON_PURGE_ZCACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-	COMMIT_RING();
-
-	return radeon_do_wait_for_idle( dev_priv );
-}
-
-/* Start the Command Processor.
- */
-static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
-
-	dev_priv->cp_running = 1;
-
-	BEGIN_RING( 6 );
-
-	RADEON_PURGE_CACHE();
-	RADEON_PURGE_ZCACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-	COMMIT_RING();
-}
-
-/* Reset the Command Processor.  This will not flush any pending
- * commands, so you must wait for the CP command stream to complete
- * before calling this routine.
- */
-static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
-{
-	u32 cur_read_ptr;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	*dev_priv->ring.head = cur_read_ptr;
-	dev_priv->ring.tail = cur_read_ptr;
-}
-
-/* Stop the Command Processor.  This will not flush any pending
- * commands, so you must flush the command stream and wait for the CP
- * to go idle before calling this routine.
- */
-static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
-
-	dev_priv->cp_running = 0;
-}
-
-/* Reset the engine.  This will stop the CP if it is running.
- */
-static int radeon_do_engine_reset( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_pixcache_flush( dev_priv );
-
-	clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
-	mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
-					      RADEON_FORCEON_MCLKA |
-					      RADEON_FORCEON_MCLKB |
- 					      RADEON_FORCEON_YCLKA |
-					      RADEON_FORCEON_YCLKB |
-					      RADEON_FORCEON_MC |
-					      RADEON_FORCEON_AIC ) );
-
-	rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
-
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
-						RADEON_SOFT_RESET_CP |
-						RADEON_SOFT_RESET_HI |
-						RADEON_SOFT_RESET_SE |
-						RADEON_SOFT_RESET_RE |
-						RADEON_SOFT_RESET_PP |
-						RADEON_SOFT_RESET_E2 |
-						RADEON_SOFT_RESET_RB ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
-						~( RADEON_SOFT_RESET_CP |
-						   RADEON_SOFT_RESET_HI |
-						   RADEON_SOFT_RESET_SE |
-						   RADEON_SOFT_RESET_RE |
-						   RADEON_SOFT_RESET_PP |
-						   RADEON_SOFT_RESET_E2 |
-						   RADEON_SOFT_RESET_RB ) ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
-	RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
-
-	/* Reset the CP ring */
-	radeon_do_cp_reset( dev_priv );
-
-	/* The CP is no longer running after an engine reset */
-	dev_priv->cp_running = 0;
-
-	/* Reset any pending vertex, indirect buffers */
-	radeon_freelist_reset( dev );
-
-	return 0;
-}
-
-static void radeon_cp_init_ring_buffer( drm_device_t *dev,
-				        drm_radeon_private_t *dev_priv )
-{
-	u32 ring_start, cur_read_ptr;
-	u32 tmp;
-
-	/* Initialize the memory controller */
-	RADEON_WRITE( RADEON_MC_FB_LOCATION,
-		      (dev_priv->agp_vm_start - 1) & 0xffff0000 );
-
-	if ( !dev_priv->is_pci ) {
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
-			      (((dev_priv->agp_vm_start - 1 +
-				 dev_priv->agp_size) & 0xffff0000) |
-			       (dev_priv->agp_vm_start >> 16)) );
-	}
-
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		ring_start = (dev_priv->cp_ring->offset
-			      - dev->agp->base
-			      + dev_priv->agp_vm_start);
-       else
-#endif
-		ring_start = (dev_priv->cp_ring->offset
-			      - dev->sg->handle
-			      + dev_priv->agp_vm_start);
-
-	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
-
-	/* Set the write pointer delay */
-	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
-
-	/* Initialize the ring buffer's read and write pointers */
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	*dev_priv->ring.head = cur_read_ptr;
-	dev_priv->ring.tail = cur_read_ptr;
-
-	if ( !dev_priv->is_pci ) {
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			      dev_priv->ring_rptr->offset );
-	} else {
-		drm_sg_mem_t *entry = dev->sg;
-		unsigned long tmp_ofs, page_ofs;
-
-		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
-		page_ofs = tmp_ofs >> PAGE_SHIFT;
-
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			     entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
-			   entry->busaddr[page_ofs],
-			   entry->handle + tmp_ofs );
-	}
-
-	/* Set ring buffer size */
-#ifdef __BIG_ENDIAN
-	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
-#else
-	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
-#endif
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	/* Turn on bus mastering */
-	tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
-	RADEON_WRITE( RADEON_BUS_CNTL, tmp );
-
-	/* Sync everything up */
-	RADEON_WRITE( RADEON_ISYNC_CNTL,
-		      (RADEON_ISYNC_ANY2D_IDLE3D |
-		       RADEON_ISYNC_ANY3D_IDLE2D |
-		       RADEON_ISYNC_WAIT_IDLEGUI |
-		       RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
-}
-
-static int radeon_do_init_cp( drm_device_t *dev,
-			      drm_radeon_init_t *init )
-{
-	drm_radeon_private_t *dev_priv;
-	struct list_head *list;
-	u32 tmp;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
-		return -ENOMEM;
-
-	memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
-
-	dev_priv->is_pci = init->is_pci;
-
-#if !defined(PCIGART_ENABLED)
-	/* PCI support is not 100% working, so we disable it here.
-	 */
-	if ( dev_priv->is_pci ) {
-		DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-#endif
-
-	if ( dev_priv->is_pci && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-
-	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-
-	dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
-	dev_priv->cp_mode = init->cp_mode;
-
-	/* Simple idle check.
-	 */
-	atomic_set( &dev_priv->idle_count, 0 );
-
-	/* We don't support anything other than bus-mastering ring mode,
-	 * but the ring can be in either AGP or PCI space for the ring
-	 * read pointer.
-	 */
-	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
-	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
-		DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-
-	switch ( init->fb_bpp ) {
-	case 16:
-		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
-		break;
-	case 32:
-	default:
-		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
-		break;
-	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	switch ( init->depth_bpp ) {
-	case 16:
-		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
-		break;
-	case 32:
-	default:
-		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
-		break;
-	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-
-	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
-					(dev_priv->front_offset >> 10));
-	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
-				       (dev_priv->back_offset >> 10));
-	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
-					(dev_priv->depth_offset >> 10));
-
-	/* Hardware state for depth clears.  Remove this if/when we no
-	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
-	 * all values to prevent unwanted 3D state from slipping through
-	 * and screwing with the clear operation.
-	 */
-	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
-					   (dev_priv->color_fmt << 10) |
-					   (1<<15));
-
-	dev_priv->depth_clear.rb3d_zstencilcntl = 
-		(dev_priv->depth_fmt |
-		 RADEON_Z_TEST_ALWAYS |
-		 RADEON_STENCIL_TEST_ALWAYS |
-		 RADEON_STENCIL_S_FAIL_REPLACE |
-		 RADEON_STENCIL_ZPASS_REPLACE |
-		 RADEON_STENCIL_ZFAIL_REPLACE |
-		 RADEON_Z_WRITE_ENABLE);
-
-	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
-					 RADEON_BFACE_SOLID |
-					 RADEON_FFACE_SOLID |
-					 RADEON_FLAT_SHADE_VTX_LAST |
-					 RADEON_DIFFUSE_SHADE_FLAT |
-					 RADEON_ALPHA_SHADE_FLAT |
-					 RADEON_SPECULAR_SHADE_FLAT |
-					 RADEON_FOG_SHADE_FLAT |
-					 RADEON_VTX_PIX_CENTER_OGL |
-					 RADEON_ROUND_MODE_TRUNC |
-					 RADEON_ROUND_PREC_8TH_PIX);
-
-	list_for_each(list, &dev->maplist->head) {
-		drm_map_list_t *r_list = (drm_map_list_t *)list;
-		if( r_list->map &&
-		    r_list->map->type == _DRM_SHM &&
-		    r_list->map->flags & _DRM_CONTAINS_LOCK ) {
-			dev_priv->sarea = r_list->map;
- 			break;
- 		}
- 	}
-	if(!dev_priv->sarea) {
-		DRM_ERROR("could not find sarea!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR("could not find framebuffer!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR("could not find mmio region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
-	if(!dev_priv->cp_ring) {
-		DRM_ERROR("could not find cp ring region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
-	if(!dev_priv->ring_rptr) {
-		DRM_ERROR("could not find ring read pointer!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR("could not find dma buffer region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		return -EINVAL;
-	}
-
-	if ( !dev_priv->is_pci ) {
-		DRM_FIND_MAP( dev_priv->agp_textures,
-			      init->agp_textures_offset );
-		if(!dev_priv->agp_textures) {
-			DRM_ERROR("could not find agp texture region!\n");
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			return -EINVAL;
-		}
-	}
-
-	dev_priv->sarea_priv =
-		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				       init->sarea_priv_offset);
-
-	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cp_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
-		if(!dev_priv->cp_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev_priv->buffers->handle) {
-			DRM_ERROR("could not find ioremap agp regions!\n");
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			return -EINVAL;
-		}
-	} else {
-		dev_priv->cp_ring->handle =
-			(void *)dev_priv->cp_ring->offset;
-		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
-
-		DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
-			   dev_priv->cp_ring->handle );
-		DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
-			   dev_priv->ring_rptr->handle );
-		DRM_DEBUG( "dev_priv->buffers->handle %p\n",
-			   dev_priv->buffers->handle );
-	}
-
-
-	dev_priv->agp_size = init->agp_size;
-	dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
-						- dev->agp->base
-						+ dev_priv->agp_vm_start);
-	else
-#endif
-		dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
-						- dev->sg->handle
-						+ dev_priv->agp_vm_start);
-
-	DRM_DEBUG( "dev_priv->agp_size %d\n",
-		   dev_priv->agp_size );
-	DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
-		   dev_priv->agp_vm_start );
-	DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
-		   dev_priv->agp_buffers_offset );
-
-	dev_priv->ring.head = ((__volatile__ u32 *)
-			       dev_priv->ring_rptr->handle);
-
-	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
-			      + init->ring_size / sizeof(u32));
-	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
-
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
-
-	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
-
-#if 0
-	/* Initialize the scratch register pointer.  This will cause
-	 * the scratch register values to be written out to memory
-	 * whenever they are updated.
-	 * FIXME: This doesn't quite work yet, so we're disabling it
-	 * for the release.
-	 */
-	RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
-					    RADEON_SCRATCH_REG_OFFSET) );
-	RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
-#endif
-
-	dev_priv->scratch = ((__volatile__ u32 *)
-			     dev_priv->ring_rptr->handle +
-			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
-
-	dev_priv->sarea_priv->last_frame = 0;
-	RADEON_WRITE( RADEON_LAST_FRAME_REG,
-		      dev_priv->sarea_priv->last_frame );
-
-	dev_priv->sarea_priv->last_dispatch = 0;
-	RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
-		      dev_priv->sarea_priv->last_dispatch );
-
-	dev_priv->sarea_priv->last_clear = 0;
-	RADEON_WRITE( RADEON_LAST_CLEAR_REG,
-		      dev_priv->sarea_priv->last_clear );
-
-	if ( dev_priv->is_pci ) {
-		if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
-					    &dev_priv->bus_pci_gart)) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			return -ENOMEM;
-		}
-		/* Turn on PCI GART
-		 */
-		tmp = RADEON_READ( RADEON_AIC_CNTL )
-		      | RADEON_PCIGART_TRANSLATE_EN;
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-
-		/* set PCI GART page-table base address
-		 */
-		RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
-
-		/* set address range for PCI address translate
-		 */
-		RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
-		RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
-						  + dev_priv->agp_size - 1);
-
-		/* Turn off AGP aperture -- is this required for PCIGART?
-		 */
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
-		RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
-	} else {
-		/* Turn off PCI GART
-		 */
-		tmp = RADEON_READ( RADEON_AIC_CNTL )
-		      & ~RADEON_PCIGART_TRANSLATE_EN;
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-	}
-
-	radeon_cp_load_microcode( dev_priv );
-	radeon_cp_init_ring_buffer( dev, dev_priv );
-
-	dev_priv->last_buf = 0;
-
-	dev->dev_private = (void *)dev_priv;
-
-	radeon_do_engine_reset( dev );
-
-	return 0;
-}
-
-int radeon_do_cleanup_cp( drm_device_t *dev )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev->dev_private ) {
-		drm_radeon_private_t *dev_priv = dev->dev_private;
-
-		if ( !dev_priv->is_pci ) {
-			DRM_IOREMAPFREE( dev_priv->cp_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
-		} else {
-			if (!DRM(ati_pcigart_cleanup)( dev,
-						dev_priv->phys_pci_gart,
-						dev_priv->bus_pci_gart ))
-				DRM_ERROR( "failed to cleanup PCI GART!\n" );
-		}
-
-		DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int radeon_cp_init( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_radeon_init_t init;
-
-	if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) )
-		return -EFAULT;
-
-	switch ( init.func ) {
-	case RADEON_INIT_CP:
-	case RADEON_INIT_R200_CP:
-		return radeon_do_init_cp( dev, &init );
-	case RADEON_CLEANUP_CP:
-		return radeon_do_cleanup_cp( dev );
-	}
-
-	return -EINVAL;
-}
-
-int radeon_cp_start( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cp_running ) {
-		DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
-		return 0;
-	}
-	if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
-		DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
-			   __FUNCTION__, dev_priv->cp_mode );
-		return 0;
-	}
-
-	radeon_do_cp_start( dev_priv );
-
-	return 0;
-}
-
-/* Stop the CP.  The engine must have been idled before calling this
- * routine.
- */
-int radeon_cp_stop( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_cp_stop_t stop;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) )
-		return -EFAULT;
-
-	/* Flush any pending CP commands.  This ensures any outstanding
-	 * commands are exectuted by the engine before we turn it off.
-	 */
-	if ( stop.flush ) {
-		radeon_do_cp_flush( dev_priv );
-	}
-
-	/* If we fail to make the engine go idle, we return an error
-	 * code so that the DRM ioctl wrapper can try again.
-	 */
-	if ( stop.idle ) {
-		ret = radeon_do_cp_idle( dev_priv );
-		if ( ret < 0 ) return ret;
-	}
-
-	/* Finally, we can turn off the CP.  If the engine isn't idle,
-	 * we will get some dropped triangles as they won't be fully
-	 * rendered before the CP is shut down.
-	 */
-	radeon_do_cp_stop( dev_priv );
-
-	/* Reset the engine */
-	radeon_do_engine_reset( dev );
-
-	return 0;
-}
-
-/* Just reset the CP ring.  Called as part of an X Server engine reset.
- */
-int radeon_cp_reset( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	radeon_do_cp_reset( dev_priv );
-
-	/* The CP is no longer running after an engine reset */
-	dev_priv->cp_running = 0;
-
-	return 0;
-}
-
-int radeon_cp_idle( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return radeon_do_cp_idle( dev_priv );
-}
-
-int radeon_engine_reset( struct inode *inode, struct file *filp,
-			 unsigned int cmd, unsigned long arg )
-{
-        drm_file_t *priv = filp->private_data;
-        drm_device_t *dev = priv->dev;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return radeon_do_engine_reset( dev );
-}
-
-
-/* ================================================================
- * Fullscreen mode
- */
-
-/* KW: Deprecated to say the least:
- */
-int radeon_fullscreen( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	return 0;
-}
-
-
-/* ================================================================
- * Freelist management
- */
-
-/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
- *   bufs until freelist code is used.  Note this hides a problem with
- *   the scratch register * (used to keep track of last buffer
- *   completed) being written to before * the last buffer has actually
- *   completed rendering.  
- *
- * KW:  It's also a good way to find free buffers quickly.
- */
-
-drm_buf_t *radeon_freelist_get( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_buf_t *buf;
-	int i, t;
-	int start;
-
-	if ( ++dev_priv->last_buf >= dma->buf_count )
-		dev_priv->last_buf = 0;
-
-	start = dev_priv->last_buf;
-
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-		u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
-		for ( i = start ; i < dma->buf_count ; i++ ) {
-			buf = dma->buflist[i];
-			buf_priv = buf->dev_private;
-			if ( buf->pid == 0 || (buf->pending && 
-					       buf_priv->age <= done_age) ) {
-				buf->pending = 0;
-				return buf;
-			}
-			start = 0;
-		}
-		udelay( 1 );
-	}
-
-	DRM_ERROR( "returning NULL!\n" );
-	return NULL;
-}
-
-void radeon_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	int i;
-
-	dev_priv->last_buf = 0;
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		drm_buf_t *buf = dma->buflist[i];
-		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-		buf_priv->age = 0;
-	}
-}
-
-
-/* ================================================================
- * CP command submission
- */
-
-int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
-{
-	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		radeon_update_ring_snapshot( ring );
-		if ( ring->space > n )
-			return 0;
-		udelay( 1 );
-	}
-
-	/* FIXME: This return value is ignored in the BEGIN_RING macro! */
-#if RADEON_FIFO_DEBUG
-	radeon_status( dev_priv );
-	DRM_ERROR( "failed!\n" );
-#endif
-	return -EBUSY;
-}
-
-static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
-{
-	int i;
-	drm_buf_t *buf;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = radeon_freelist_get( dev );
-		if ( !buf ) return -EAGAIN;
-
-		buf->pid = current->pid;
-
-		if ( copy_to_user( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
-			return -EFAULT;
-		if ( copy_to_user( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
-			return -EFAULT;
-
-		d->granted_count++;
-	}
-	return 0;
-}
-
-int radeon_cp_buffers( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-	int ret = 0;
-	drm_dma_t d;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
-		return -EFAULT;
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   current->pid, d.send_count );
-		return -EINVAL;
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   current->pid, d.request_count, dma->buf_count );
-		return -EINVAL;
-	}
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		ret = radeon_cp_get_buffers( dev, &d );
-	}
-
-	if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
-		return -EFAULT;
-
-	return ret;
-}
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
deleted file mode 100644
index b7a83804..00000000
--- a/linux/radeon_drm.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- *    Keith Whitwell <keith_whitwell@yahoo.com>
- */
-
-#ifndef __RADEON_DRM_H__
-#define __RADEON_DRM_H__
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the X server file (radeon_sarea.h)
- */
-#ifndef __RADEON_SAREA_DEFINES__
-#define __RADEON_SAREA_DEFINES__
-
-/* Old style state flags, required for sarea interface (1.1 and 1.2
- * clears) and 1.2 drm_vertex2 ioctl.
- */
-#define RADEON_UPLOAD_CONTEXT		0x00000001
-#define RADEON_UPLOAD_VERTFMT		0x00000002
-#define RADEON_UPLOAD_LINE		0x00000004
-#define RADEON_UPLOAD_BUMPMAP		0x00000008
-#define RADEON_UPLOAD_MASKS		0x00000010
-#define RADEON_UPLOAD_VIEWPORT		0x00000020
-#define RADEON_UPLOAD_SETUP		0x00000040
-#define RADEON_UPLOAD_TCL		0x00000080
-#define RADEON_UPLOAD_MISC		0x00000100
-#define RADEON_UPLOAD_TEX0		0x00000200
-#define RADEON_UPLOAD_TEX1		0x00000400
-#define RADEON_UPLOAD_TEX2		0x00000800
-#define RADEON_UPLOAD_TEX0IMAGES	0x00001000
-#define RADEON_UPLOAD_TEX1IMAGES	0x00002000
-#define RADEON_UPLOAD_TEX2IMAGES	0x00004000
-#define RADEON_UPLOAD_CLIPRECTS		0x00008000 /* handled client-side */
-#define RADEON_REQUIRE_QUIESCENCE	0x00010000
-#define RADEON_UPLOAD_ZBIAS		0x00020000 /* version 1.2 and newer */
-#define RADEON_UPLOAD_ALL		0x003effff
-#define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
-
-
-/* New style per-packet identifiers for use in cmd_buffer ioctl with
- * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
- * state bits and the packet size:
- */
-#define RADEON_EMIT_PP_MISC                         0 /* context/7 */
-#define RADEON_EMIT_PP_CNTL                         1 /* context/3 */
-#define RADEON_EMIT_RB3D_COLORPITCH                 2 /* context/1 */
-#define RADEON_EMIT_RE_LINE_PATTERN                 3 /* line/2 */
-#define RADEON_EMIT_SE_LINE_WIDTH                   4 /* line/1 */
-#define RADEON_EMIT_PP_LUM_MATRIX                   5 /* bumpmap/1 */
-#define RADEON_EMIT_PP_ROT_MATRIX_0                 6 /* bumpmap/2 */
-#define RADEON_EMIT_RB3D_STENCILREFMASK             7 /* masks/3 */
-#define RADEON_EMIT_SE_VPORT_XSCALE                 8 /* viewport/6 */
-#define RADEON_EMIT_SE_CNTL                         9 /* setup/2 */
-#define RADEON_EMIT_SE_CNTL_STATUS                  10 /* setup/1 */
-#define RADEON_EMIT_RE_MISC                         11 /* misc/1 */
-#define RADEON_EMIT_PP_TXFILTER_0                   12 /* tex0/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_0               13 /* tex0/1 */
-#define RADEON_EMIT_PP_TXFILTER_1                   14 /* tex1/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_1               15 /* tex1/1 */
-#define RADEON_EMIT_PP_TXFILTER_2                   16 /* tex2/6 */
-#define RADEON_EMIT_PP_BORDER_COLOR_2               17 /* tex2/1 */
-#define RADEON_EMIT_SE_ZBIAS_FACTOR                 18 /* zbias/2 */
-#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19 /* tcl/11 */
-#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
-#define R200_EMIT_PP_TXCBLEND_0                     21 /* tex0/4 */
-#define R200_EMIT_PP_TXCBLEND_1                     22 /* tex1/4 */
-#define R200_EMIT_PP_TXCBLEND_2                     23 /* tex2/4 */
-#define R200_EMIT_PP_TXCBLEND_3                     24 /* tex3/4 */
-#define R200_EMIT_PP_TXCBLEND_4                     25 /* tex4/4 */
-#define R200_EMIT_PP_TXCBLEND_5                     26 /* tex5/4 */
-#define R200_EMIT_PP_TXCBLEND_6                     27 /* ???/4 */
-#define R200_EMIT_PP_TXCBLEND_7                     28 /* ???/4 */
-#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29 /* tcl/7 */
-#define R200_EMIT_TFACTOR_0                         30 /* tf/7 */
-#define R200_EMIT_VTX_FMT_0                         31 /* vtx/5 */
-#define R200_EMIT_VAP_CTL                           32 /* vap/1 */
-#define R200_EMIT_MATRIX_SELECT_0                   33 /* msl/5 */
-#define R200_EMIT_TEX_PROC_CTL_2                    34 /* tcg/5 */
-#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35 /* tcl/1 */
-#define R200_EMIT_PP_TXFILTER_0                     36 /* tex0/6 */
-#define R200_EMIT_PP_TXFILTER_1                     37 /* tex1/6 */
-#define R200_EMIT_PP_TXFILTER_2                     38 /* tex2/6 */
-#define R200_EMIT_PP_TXFILTER_3                     39 /* tex3/6 */
-#define R200_EMIT_PP_TXFILTER_4                     40 /* tex4/6 */
-#define R200_EMIT_PP_TXFILTER_5                     41 /* tex5/6 */
-#define R200_EMIT_PP_TXOFFSET_0                     42 /* tex0/1 */
-#define R200_EMIT_PP_TXOFFSET_1                     43 /* tex1/1 */
-#define R200_EMIT_PP_TXOFFSET_2                     44 /* tex2/1 */
-#define R200_EMIT_PP_TXOFFSET_3                     45 /* tex3/1 */
-#define R200_EMIT_PP_TXOFFSET_4                     46 /* tex4/1 */
-#define R200_EMIT_PP_TXOFFSET_5                     47 /* tex5/1 */
-#define R200_EMIT_VTE_CNTL                          48 /* vte/1 */
-#define R200_EMIT_OUTPUT_VTX_COMP_SEL               49 /* vtx/1 */
-#define R200_EMIT_PP_TAM_DEBUG3                     50 /* tam/1 */
-#define R200_EMIT_PP_CNTL_X                         51 /* cst/1 */
-#define R200_EMIT_RB3D_DEPTHXY_OFFSET               52 /* cst/1 */
-#define R200_EMIT_RE_AUX_SCISSOR_CNTL               53 /* cst/1 */
-#define R200_EMIT_RE_SCISSOR_TL_0                   54 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_1                   55 /* cst/2 */
-#define R200_EMIT_RE_SCISSOR_TL_2                   56 /* cst/2 */
-#define R200_EMIT_SE_VAP_CNTL_STATUS                57 /* cst/1 */
-#define R200_EMIT_SE_VTX_STATE_CNTL                 58 /* cst/1 */
-#define R200_EMIT_RE_POINTSIZE                      59 /* cst/1 */
-#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60 /* cst/4 */
-#define RADEON_MAX_STATE_PACKETS                    61
-
-
-/* Commands understood by cmd_buffer ioctl.  More can be added but
- * obviously these can't be removed or changed:
- */
-#define RADEON_CMD_PACKET      1 /* emit one of the register packets above */
-#define RADEON_CMD_SCALARS     2 /* emit scalar data */
-#define RADEON_CMD_VECTORS     3 /* emit vector data */
-#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
-#define RADEON_CMD_PACKET3     5 /* emit hw packet */
-#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
-#define RADEON_CMD_SCALARS2     7 /* r200 stopgap */
-
-
-typedef union {
-	int i;
-	struct { 
-		unsigned char cmd_type, pad0, pad1, pad2;
-	} header;
-	struct { 
-		unsigned char cmd_type, packet_id, pad0, pad1;
-	} packet;
-	struct { 
-		unsigned char cmd_type, offset, stride, count; 
-	} scalars;
-	struct { 
-		unsigned char cmd_type, offset, stride, count; 
-	} vectors;
-	struct { 
-		unsigned char cmd_type, buf_idx, pad0, pad1; 
-	} dma;
-} drm_radeon_cmd_header_t;
-
-
-#define RADEON_FRONT			0x1
-#define RADEON_BACK			0x2
-#define RADEON_DEPTH			0x4
-#define RADEON_STENCIL                  0x8
-
-/* Primitive types
- */
-#define RADEON_POINTS			0x1
-#define RADEON_LINES			0x2
-#define RADEON_LINE_STRIP		0x3
-#define RADEON_TRIANGLES		0x4
-#define RADEON_TRIANGLE_FAN		0x5
-#define RADEON_TRIANGLE_STRIP		0x6
-
-/* Vertex/indirect buffer size
- */
-#define RADEON_BUFFER_SIZE		65536
-
-/* Byte offsets for indirect buffer data
- */
-#define RADEON_INDEX_PRIM_OFFSET	20
-
-#define RADEON_SCRATCH_REG_OFFSET	32
-
-#define RADEON_NR_SAREA_CLIPRECTS	12
-
-/* There are 2 heaps (local/AGP).  Each region within a heap is a
- * minimum of 64k, and there are at most 64 of them per heap.
- */
-#define RADEON_LOCAL_TEX_HEAP		0
-#define RADEON_AGP_TEX_HEAP		1
-#define RADEON_NR_TEX_HEAPS		2
-#define RADEON_NR_TEX_REGIONS		64
-#define RADEON_LOG_TEX_GRANULARITY	16
-
-#define RADEON_MAX_TEXTURE_LEVELS	12
-#define RADEON_MAX_TEXTURE_UNITS	3
-
-#endif /* __RADEON_SAREA_DEFINES__ */
-
-typedef struct {
-	unsigned int red;
-	unsigned int green;
-	unsigned int blue;
-	unsigned int alpha;
-} radeon_color_regs_t;
-
-typedef struct {
-	/* Context state */
-	unsigned int pp_misc;				/* 0x1c14 */
-	unsigned int pp_fog_color;
-	unsigned int re_solid_color;
-	unsigned int rb3d_blendcntl;
-	unsigned int rb3d_depthoffset;
-	unsigned int rb3d_depthpitch;
-	unsigned int rb3d_zstencilcntl;
-
-	unsigned int pp_cntl;				/* 0x1c38 */
-	unsigned int rb3d_cntl;
-	unsigned int rb3d_coloroffset;
-	unsigned int re_width_height;
-	unsigned int rb3d_colorpitch;
-	unsigned int se_cntl;
-
-	/* Vertex format state */
-	unsigned int se_coord_fmt;			/* 0x1c50 */
-
-	/* Line state */
-	unsigned int re_line_pattern;			/* 0x1cd0 */
-	unsigned int re_line_state;
-
-	unsigned int se_line_width;			/* 0x1db8 */
-
-	/* Bumpmap state */
-	unsigned int pp_lum_matrix;			/* 0x1d00 */
-
-	unsigned int pp_rot_matrix_0;			/* 0x1d58 */
-	unsigned int pp_rot_matrix_1;
-
-	/* Mask state */
-	unsigned int rb3d_stencilrefmask;		/* 0x1d7c */
-	unsigned int rb3d_ropcntl;
-	unsigned int rb3d_planemask;
-
-	/* Viewport state */
-	unsigned int se_vport_xscale;			/* 0x1d98 */
-	unsigned int se_vport_xoffset;
-	unsigned int se_vport_yscale;
-	unsigned int se_vport_yoffset;
-	unsigned int se_vport_zscale;
-	unsigned int se_vport_zoffset;
-
-	/* Setup state */
-	unsigned int se_cntl_status;			/* 0x2140 */
-
-	/* Misc state */
-	unsigned int re_top_left;			/* 0x26c0 */
-	unsigned int re_misc;
-} drm_radeon_context_regs_t;
-
-typedef struct {
-	/* Zbias state */
-	unsigned int se_zbias_factor;			/* 0x1dac */
-	unsigned int se_zbias_constant;
-} drm_radeon_context2_regs_t;
-
-
-/* Setup registers for each texture unit
- */
-typedef struct {
-	unsigned int pp_txfilter;
-	unsigned int pp_txformat;
-	unsigned int pp_txoffset;
-	unsigned int pp_txcblend;
-	unsigned int pp_txablend;
-	unsigned int pp_tfactor;
-	unsigned int pp_border_color;
-} drm_radeon_texture_regs_t;
-
-typedef struct {
-	unsigned int start;
-	unsigned int finish;
-	unsigned int prim:8;
-	unsigned int stateidx:8;
-	unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
-        unsigned int vc_format;   /* vertex format */
-} drm_radeon_prim_t;
-
-
-typedef struct {
-	drm_radeon_context_regs_t context;
-	drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
-	drm_radeon_context2_regs_t context2;
-	unsigned int dirty;
-} drm_radeon_state_t;
-
-
-typedef struct {
-	unsigned char next, prev;
-	unsigned char in_use;
-	int age;
-} drm_radeon_tex_region_t;
-
-typedef struct {
-	/* The channel for communication of state information to the
-	 * kernel on firing a vertex buffer with either of the
-	 * obsoleted vertex/index ioctls.
-	 */
-	drm_radeon_context_regs_t context_state;
-	drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
-	unsigned int dirty;
-	unsigned int vertsize;
-	unsigned int vc_format;
-
-	/* The current cliprects, or a subset thereof.
-	 */
-	drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
-	unsigned int nbox;
-
-	/* Counters for client-side throttling of rendering clients.
-	 */
-	unsigned int last_frame;
-	unsigned int last_dispatch;
-	unsigned int last_clear;
-
-	drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
-	int tex_age[RADEON_NR_TEX_HEAPS];
-	int ctx_owner;
-        int pfState;                /* number of 3d windows (0,1,2ormore) */
-        int pfCurrentPage;	    /* which buffer is being displayed? */
-} drm_radeon_sarea_t;
-
-
-/* WARNING: If you change any of these defines, make sure to change the
- * defines in the Xserver file (xf86drmRadeon.h)
- *
- * KW: actually it's illegal to change any of this (backwards compatibility).
- */
-
-/* Radeon specific ioctls
- * The device specific ioctl range is 0x40 to 0x79.
- */
-#define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( 0x40, drm_radeon_init_t)
-#define DRM_IOCTL_RADEON_CP_START   DRM_IO(  0x41)
-#define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( 0x42, drm_radeon_cp_stop_t)
-#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  0x43)
-#define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  0x44)
-#define DRM_IOCTL_RADEON_RESET      DRM_IO(  0x45)
-#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
-#define DRM_IOCTL_RADEON_SWAP       DRM_IO(  0x47)
-#define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( 0x48, drm_radeon_clear_t)
-#define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( 0x49, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_INDICES    DRM_IOW( 0x4a, drm_radeon_indices_t)
-#define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( 0x4c, drm_radeon_stipple_t)
-#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(0x4d, drm_radeon_indirect_t)
-#define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(0x4e, drm_radeon_texture_t)
-#define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( 0x4f, drm_radeon_vertex_t)
-#define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( 0x50, drm_radeon_cmd_buffer_t)
-#define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(0x51, drm_radeon_getparam_t)
-#define DRM_IOCTL_RADEON_FLIP	    DRM_IO(  0x52)
-
-typedef struct drm_radeon_init {
-	enum {
-		RADEON_INIT_CP    = 0x01,
-		RADEON_CLEANUP_CP = 0x02,
-		RADEON_INIT_R200_CP = 0x03,	
-	} func;
-	unsigned long sarea_priv_offset;
-	int is_pci;
-	int cp_mode;
-	int agp_size;
-	int ring_size;
-	int usec_timeout;
-
-	unsigned int fb_bpp;
-	unsigned int front_offset, front_pitch;
-	unsigned int back_offset, back_pitch;
-	unsigned int depth_bpp;
-	unsigned int depth_offset, depth_pitch;
-
-	unsigned long fb_offset;
-	unsigned long mmio_offset;
-	unsigned long ring_offset;
-	unsigned long ring_rptr_offset;
-	unsigned long buffers_offset;
-	unsigned long agp_textures_offset;
-} drm_radeon_init_t;
-
-
-typedef struct drm_radeon_cp_stop {
-	int flush;
-	int idle;
-} drm_radeon_cp_stop_t;
-
-typedef struct drm_radeon_fullscreen {
-	enum {
-		RADEON_INIT_FULLSCREEN    = 0x01,
-		RADEON_CLEANUP_FULLSCREEN = 0x02
-	} func;
-} drm_radeon_fullscreen_t;
-
-#define CLEAR_X1	0
-#define CLEAR_Y1	1
-#define CLEAR_X2	2
-#define CLEAR_Y2	3
-#define CLEAR_DEPTH	4
-
-typedef union drm_radeon_clear_rect {
-	float f[5];
-	unsigned int ui[5];
-} drm_radeon_clear_rect_t;
-
-typedef struct drm_radeon_clear {
-	unsigned int flags;
-	unsigned int clear_color;
-	unsigned int clear_depth;
-	unsigned int color_mask;
-	unsigned int depth_mask;   /* misnamed field:  should be stencil */
-	drm_radeon_clear_rect_t *depth_boxes;
-} drm_radeon_clear_t;
-
-typedef struct drm_radeon_vertex {
-	int prim;
-	int idx;			/* Index of vertex buffer */
-	int count;			/* Number of vertices in buffer */
-	int discard;			/* Client finished with buffer? */
-} drm_radeon_vertex_t;
-
-typedef struct drm_radeon_indices {
-	int prim;
-	int idx;
-	int start;
-	int end;
-	int discard;			/* Client finished with buffer? */
-} drm_radeon_indices_t;
-
-/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
- *      - allows multiple primitives and state changes in a single ioctl
- *      - supports driver change to emit native primitives
- */
-typedef struct drm_radeon_vertex2 {
-	int idx;			/* Index of vertex buffer */
-	int discard;			/* Client finished with buffer? */
-	int nr_states;
-	drm_radeon_state_t *state;
-	int nr_prims;
-	drm_radeon_prim_t *prim;
-} drm_radeon_vertex2_t;
-
-/* v1.3 - obsoletes drm_radeon_vertex2
- *      - allows arbitarily large cliprect list 
- *      - allows updating of tcl packet, vector and scalar state
- *      - allows memory-efficient description of state updates
- *      - allows state to be emitted without a primitive 
- *           (for clears, ctx switches)
- *      - allows more than one dma buffer to be referenced per ioctl
- *      - supports tcl driver
- *      - may be extended in future versions with new cmd types, packets
- */
-typedef struct drm_radeon_cmd_buffer {
-	int bufsz;
-	char *buf;
-	int nbox;
-	drm_clip_rect_t *boxes;
-} drm_radeon_cmd_buffer_t;
-
-typedef struct drm_radeon_tex_image {
-	unsigned int x, y;		/* Blit coordinates */
-	unsigned int width, height;
-	const void *data;
-} drm_radeon_tex_image_t;
-
-typedef struct drm_radeon_texture {
-	int offset;
-	int pitch;
-	int format;
-	int width;			/* Texture image coordinates */
-	int height;
-	drm_radeon_tex_image_t *image;
-} drm_radeon_texture_t;
-
-typedef struct drm_radeon_stipple {
-	unsigned int *mask;
-} drm_radeon_stipple_t;
-
-typedef struct drm_radeon_indirect {
-	int idx;
-	int start;
-	int end;
-	int discard;
-} drm_radeon_indirect_t;
-
-
-/* 1.3: An ioctl to get parameters that aren't available to the 3d
- * client any other way.  
- */
-#define RADEON_PARAM_AGP_BUFFER_OFFSET 0x1
-
-typedef struct drm_radeon_getparam {
-	int param;
-	int *value;
-} drm_radeon_getparam_t;
-
-#endif
diff --git a/linux/radeon_drv.c b/linux/radeon_drv.c
index d7f8d945..df859360 100644
--- a/linux/radeon_drv.c
+++ b/linux/radeon_drv.c
@@ -35,52 +35,6 @@
 #include "radeon_drv.h"
 #include "ati_pcigart.h"
 
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"radeon"
-#define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20020611"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		4
-#define DRIVER_PATCHLEVEL	0
-
-/* Interface history:
- *
- * 1.1 - ??
- * 1.2 - Add vertex2 ioctl (keith)
- *     - Add stencil capability to clear ioctl (gareth, keith)
- *     - Increase MAX_TEXTURE_LEVELS (brian)
- * 1.3 - Add cmdbuf ioctl (keith)
- *     - Add support for new radeon packets (keith)
- *     - Add getparam ioctl (keith)
- *     - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
- * 1.4 - Add r200 packets to cmdbuf ioctl (keith)
- *     - Add r200 init command to RADEON_CP_INIT
- *     - R200 support in clear ioclt (TODO)
- */
-#define DRIVER_IOCTLS							     \
- [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)]    = { radeon_cp_init,     1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)]   = { radeon_cp_start,    1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)]    = { radeon_cp_stop,     1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)]   = { radeon_cp_reset,    1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)]    = { radeon_cp_idle,     1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)]    = { radeon_engine_reset,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)]       = { radeon_cp_swap,     1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)]      = { radeon_cp_clear,    1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)]     = { radeon_cp_vertex,   1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)]    = { radeon_cp_indices,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_TEXTURE)]    = { radeon_cp_texture,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)]    = { radeon_cp_stipple,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)]   = { radeon_cp_indirect, 1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX2)]    = { radeon_cp_vertex2,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CMDBUF)]     = { radeon_cp_cmdbuf,   1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_GETPARAM)]   = { radeon_cp_getparam, 1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FLIP)]       = { radeon_cp_flip,     1, 0 }, 
-
-
 #include "drm_agpsupport.h"
 #include "drm_auth.h"
 #include "drm_bufs.h"
@@ -88,26 +42,6 @@
 #include "drm_dma.h"
 #include "drm_drawable.h"
 #include "drm_drv.h"
-
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init radeon_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", radeon_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
deleted file mode 100644
index 2f0524ed..00000000
--- a/linux/radeon_drv.h
+++ /dev/null
@@ -1,839 +0,0 @@
-/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_DRV_H__
-#define __RADEON_DRV_H__
-
-#define GET_RING_HEAD(ring)		readl( (volatile u32 *) (ring)->head )
-#define SET_RING_HEAD(ring,val)		writel( (val), (volatile u32 *) (ring)->head )
-
-typedef struct drm_radeon_freelist {
-   	unsigned int age;
-   	drm_buf_t *buf;
-   	struct drm_radeon_freelist *next;
-   	struct drm_radeon_freelist *prev;
-} drm_radeon_freelist_t;
-
-typedef struct drm_radeon_ring_buffer {
-	u32 *start;
-	u32 *end;
-	int size;
-	int size_l2qw;
-
-	volatile u32 *head;
-	u32 tail;
-	u32 tail_mask;
-	int space;
-
-	int high_mark;
-} drm_radeon_ring_buffer_t;
-
-typedef struct drm_radeon_depth_clear_t {
-	u32 rb3d_cntl;
-	u32 rb3d_zstencilcntl;
-	u32 se_cntl;
-} drm_radeon_depth_clear_t;
-
-typedef struct drm_radeon_private {
-	drm_radeon_ring_buffer_t ring;
-	drm_radeon_sarea_t *sarea_priv;
-
-	int agp_size;
-	u32 agp_vm_start;
-	unsigned long agp_buffers_offset;
-
-	int cp_mode;
-	int cp_running;
-
-   	drm_radeon_freelist_t *head;
-   	drm_radeon_freelist_t *tail;
-	int last_buf;
-	volatile u32 *scratch;
-
-	int usec_timeout;
-
-	int is_r200;
-
-	int is_pci;
-	unsigned long phys_pci_gart;
-	dma_addr_t bus_pci_gart;
-
-	atomic_t idle_count;
-
-	int page_flipping;
-	int current_page;
-	u32 crtc_offset;
-	u32 crtc_offset_cntl;
-
-	u32 color_fmt;
-	unsigned int front_offset;
-	unsigned int front_pitch;
-	unsigned int back_offset;
-	unsigned int back_pitch;
-
-	u32 depth_fmt;
-	unsigned int depth_offset;
-	unsigned int depth_pitch;
-
-	u32 front_pitch_offset;
-	u32 back_pitch_offset;
-	u32 depth_pitch_offset;
-
-	drm_radeon_depth_clear_t depth_clear;
-
-	drm_map_t *sarea;
-	drm_map_t *fb;
-	drm_map_t *mmio;
-	drm_map_t *cp_ring;
-	drm_map_t *ring_rptr;
-	drm_map_t *buffers;
-	drm_map_t *agp_textures;
-} drm_radeon_private_t;
-
-typedef struct drm_radeon_buf_priv {
-	u32 age;
-} drm_radeon_buf_priv_t;
-
-				/* radeon_cp.c */
-extern int radeon_cp_init( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int radeon_cp_start( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int radeon_cp_stop( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int radeon_cp_reset( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int radeon_cp_idle( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int radeon_engine_reset( struct inode *inode, struct file *filp,
-				unsigned int cmd, unsigned long arg );
-extern int radeon_fullscreen( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_buffers( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-
-extern void radeon_freelist_reset( drm_device_t *dev );
-extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
-
-extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
-
-static inline void
-radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
-{
-	ring->space = (GET_RING_HEAD(ring) - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 )
-		ring->space += ring->size;
-}
-
-extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
-extern int radeon_do_cleanup_cp( drm_device_t *dev );
-extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
-
-				/* radeon_state.c */
-extern int radeon_cp_clear( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int radeon_cp_swap( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-extern int radeon_cp_vertex( struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg );
-extern int radeon_cp_indices( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_texture( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_indirect( struct inode *inode, struct file *filp,
-			       unsigned int cmd, unsigned long arg );
-extern int radeon_cp_vertex2( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_getparam( struct inode *inode, struct file *filp,
-			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_flip( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-
-
-
-/* Register definitions, register access macros and drmAddMap constants
- * for Radeon kernel driver.
- */
-
-#define RADEON_AGP_COMMAND		0x0f60
-#define RADEON_AUX_SCISSOR_CNTL		0x26f0
-#	define RADEON_EXCLUSIVE_SCISSOR_0	(1 << 24)
-#	define RADEON_EXCLUSIVE_SCISSOR_1	(1 << 25)
-#	define RADEON_EXCLUSIVE_SCISSOR_2	(1 << 26)
-#	define RADEON_SCISSOR_0_ENABLE		(1 << 28)
-#	define RADEON_SCISSOR_1_ENABLE		(1 << 29)
-#	define RADEON_SCISSOR_2_ENABLE		(1 << 30)
-
-#define RADEON_BUS_CNTL			0x0030
-#	define RADEON_BUS_MASTER_DIS		(1 << 6)
-
-#define RADEON_CLOCK_CNTL_DATA		0x000c
-#	define RADEON_PLL_WR_EN			(1 << 7)
-#define RADEON_CLOCK_CNTL_INDEX		0x0008
-#define RADEON_CONFIG_APER_SIZE		0x0108
-#define RADEON_CRTC_OFFSET		0x0224
-#define RADEON_CRTC_OFFSET_CNTL		0x0228
-#	define RADEON_CRTC_TILE_EN		(1 << 15)
-#	define RADEON_CRTC_OFFSET_FLIP_CNTL	(1 << 16)
-
-#define RADEON_RB3D_COLORPITCH		0x1c48
-
-#define RADEON_DP_GUI_MASTER_CNTL	0x146c
-#	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)
-#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
-#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)
-#	define RADEON_GMC_BRUSH_NONE		(15 << 4)
-#	define RADEON_GMC_DST_16BPP		(4 << 8)
-#	define RADEON_GMC_DST_24BPP		(5 << 8)
-#	define RADEON_GMC_DST_32BPP		(6 << 8)
-#	define RADEON_GMC_DST_DATATYPE_SHIFT	8
-#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3 << 12)
-#	define RADEON_DP_SRC_SOURCE_MEMORY	(2 << 24)
-#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3 << 24)
-#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1 << 28)
-#	define RADEON_GMC_WR_MSK_DIS		(1 << 30)
-#	define RADEON_ROP3_S			0x00cc0000
-#	define RADEON_ROP3_P			0x00f00000
-#define RADEON_DP_WRITE_MASK		0x16cc
-#define RADEON_DST_PITCH_OFFSET		0x142c
-#define RADEON_DST_PITCH_OFFSET_C	0x1c80
-#	define RADEON_DST_TILE_LINEAR		(0 << 30)
-#	define RADEON_DST_TILE_MACRO		(1 << 30)
-#	define RADEON_DST_TILE_MICRO		(2 << 30)
-#	define RADEON_DST_TILE_BOTH		(3 << 30)
-
-#define RADEON_SCRATCH_REG0		0x15e0
-#define RADEON_SCRATCH_REG1		0x15e4
-#define RADEON_SCRATCH_REG2		0x15e8
-#define RADEON_SCRATCH_REG3		0x15ec
-#define RADEON_SCRATCH_REG4		0x15f0
-#define RADEON_SCRATCH_REG5		0x15f4
-#define RADEON_SCRATCH_UMSK		0x0770
-#define RADEON_SCRATCH_ADDR		0x0774
-
-#define RADEON_HOST_PATH_CNTL		0x0130
-#	define RADEON_HDP_SOFT_RESET		(1 << 26)
-#	define RADEON_HDP_WC_TIMEOUT_MASK	(7 << 28)
-#	define RADEON_HDP_WC_TIMEOUT_28BCLK	(7 << 28)
-
-#define RADEON_ISYNC_CNTL		0x1724
-#	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)
-#	define RADEON_ISYNC_ANY3D_IDLE2D	(1 << 1)
-#	define RADEON_ISYNC_TRIG2D_IDLE3D	(1 << 2)
-#	define RADEON_ISYNC_TRIG3D_IDLE2D	(1 << 3)
-#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)
-#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
-
-#define RADEON_RBBM_GUICNTL		0x172c
-#	define RADEON_HOST_DATA_SWAP_NONE	(0 << 0)
-#	define RADEON_HOST_DATA_SWAP_16BIT	(1 << 0)
-#	define RADEON_HOST_DATA_SWAP_32BIT	(2 << 0)
-#	define RADEON_HOST_DATA_SWAP_HDW	(3 << 0)
-
-#define RADEON_MC_AGP_LOCATION		0x014c
-#define RADEON_MC_FB_LOCATION		0x0148
-#define RADEON_MCLK_CNTL		0x0012
-#	define RADEON_FORCEON_MCLKA		(1 << 16)
-#	define RADEON_FORCEON_MCLKB		(1 << 17)
-#	define RADEON_FORCEON_YCLKA		(1 << 18)
-#	define RADEON_FORCEON_YCLKB		(1 << 19)
-#	define RADEON_FORCEON_MC		(1 << 20)
-#	define RADEON_FORCEON_AIC		(1 << 21)
-
-#define RADEON_PP_BORDER_COLOR_0	0x1d40
-#define RADEON_PP_BORDER_COLOR_1	0x1d44
-#define RADEON_PP_BORDER_COLOR_2	0x1d48
-#define RADEON_PP_CNTL			0x1c38
-#	define RADEON_SCISSOR_ENABLE		(1 <<  1)
-#define RADEON_PP_LUM_MATRIX		0x1d00
-#define RADEON_PP_MISC			0x1c14
-#define RADEON_PP_ROT_MATRIX_0		0x1d58
-#define RADEON_PP_TXFILTER_0		0x1c54
-#define RADEON_PP_TXFILTER_1		0x1c6c
-#define RADEON_PP_TXFILTER_2		0x1c84
-
-#define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
-#	define RADEON_RB2D_DC_FLUSH		(3 << 0)
-#	define RADEON_RB2D_DC_FREE		(3 << 2)
-#	define RADEON_RB2D_DC_FLUSH_ALL		0xf
-#	define RADEON_RB2D_DC_BUSY		(1 << 31)
-#define RADEON_RB3D_CNTL		0x1c3c
-#	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
-#	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
-#	define RADEON_DITHER_ENABLE		(1 << 2)
-#	define RADEON_ROUND_ENABLE		(1 << 3)
-#	define RADEON_SCALE_DITHER_ENABLE	(1 << 4)
-#	define RADEON_DITHER_INIT		(1 << 5)
-#	define RADEON_ROP_ENABLE		(1 << 6)
-#	define RADEON_STENCIL_ENABLE		(1 << 7)
-#	define RADEON_Z_ENABLE			(1 << 8)
-#define RADEON_RB3D_DEPTHOFFSET		0x1c24
-#define RADEON_RB3D_DEPTHPITCH		0x1c28
-#define RADEON_RB3D_PLANEMASK		0x1d84
-#define RADEON_RB3D_STENCILREFMASK	0x1d7c
-#define RADEON_RB3D_ZCACHE_MODE		0x3250
-#define RADEON_RB3D_ZCACHE_CTLSTAT	0x3254
-#	define RADEON_RB3D_ZC_FLUSH		(1 << 0)
-#	define RADEON_RB3D_ZC_FREE		(1 << 2)
-#	define RADEON_RB3D_ZC_FLUSH_ALL		0x5
-#	define RADEON_RB3D_ZC_BUSY		(1 << 31)
-#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
-#	define RADEON_Z_TEST_MASK		(7 << 4)
-#	define RADEON_Z_TEST_ALWAYS		(7 << 4)
-#	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)
-#	define RADEON_STENCIL_S_FAIL_REPLACE	(2 << 16)
-#	define RADEON_STENCIL_ZPASS_REPLACE	(2 << 20)
-#	define RADEON_STENCIL_ZFAIL_REPLACE	(2 << 24)
-#	define RADEON_Z_WRITE_ENABLE		(1 << 30)
-#define RADEON_RBBM_SOFT_RESET		0x00f0
-#	define RADEON_SOFT_RESET_CP		(1 <<  0)
-#	define RADEON_SOFT_RESET_HI		(1 <<  1)
-#	define RADEON_SOFT_RESET_SE		(1 <<  2)
-#	define RADEON_SOFT_RESET_RE		(1 <<  3)
-#	define RADEON_SOFT_RESET_PP		(1 <<  4)
-#	define RADEON_SOFT_RESET_E2		(1 <<  5)
-#	define RADEON_SOFT_RESET_RB		(1 <<  6)
-#	define RADEON_SOFT_RESET_HDP		(1 <<  7)
-#define RADEON_RBBM_STATUS		0x0e40
-#	define RADEON_RBBM_FIFOCNT_MASK		0x007f
-#	define RADEON_RBBM_ACTIVE		(1 << 31)
-#define RADEON_RE_LINE_PATTERN		0x1cd0
-#define RADEON_RE_MISC			0x26c4
-#define RADEON_RE_TOP_LEFT		0x26c0
-#define RADEON_RE_WIDTH_HEIGHT		0x1c44
-#define RADEON_RE_STIPPLE_ADDR		0x1cc8
-#define RADEON_RE_STIPPLE_DATA		0x1ccc
-
-#define RADEON_SCISSOR_TL_0		0x1cd8
-#define RADEON_SCISSOR_BR_0		0x1cdc
-#define RADEON_SCISSOR_TL_1		0x1ce0
-#define RADEON_SCISSOR_BR_1		0x1ce4
-#define RADEON_SCISSOR_TL_2		0x1ce8
-#define RADEON_SCISSOR_BR_2		0x1cec
-#define RADEON_SE_COORD_FMT		0x1c50
-#define RADEON_SE_CNTL			0x1c4c
-#	define RADEON_FFACE_CULL_CW		(0 << 0)
-#	define RADEON_BFACE_SOLID		(3 << 1)
-#	define RADEON_FFACE_SOLID		(3 << 3)
-#	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)
-#	define RADEON_DIFFUSE_SHADE_FLAT	(1 << 8)
-#	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)
-#	define RADEON_ALPHA_SHADE_FLAT		(1 << 10)
-#	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)
-#	define RADEON_SPECULAR_SHADE_FLAT	(1 << 12)
-#	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)
-#	define RADEON_FOG_SHADE_FLAT		(1 << 14)
-#	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)
-#	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)
-#	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)
-#	define RADEON_VTX_PIX_CENTER_OGL	(1 << 27)
-#	define RADEON_ROUND_MODE_TRUNC		(0 << 28)
-#	define RADEON_ROUND_PREC_8TH_PIX	(1 << 30)
-#define RADEON_SE_CNTL_STATUS		0x2140
-#define RADEON_SE_LINE_WIDTH		0x1db8
-#define RADEON_SE_VPORT_XSCALE		0x1d98
-#define RADEON_SE_ZBIAS_FACTOR		0x1db0
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
-#define RADEON_SE_TCL_OUTPUT_VTX_FMT         0x2254
-#define RADEON_SE_TCL_VECTOR_INDX_REG        0x2200
-#       define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT  16
-#       define RADEON_VEC_INDX_DWORD_COUNT_SHIFT     28
-#define RADEON_SE_TCL_VECTOR_DATA_REG       0x2204
-#define RADEON_SE_TCL_SCALAR_INDX_REG       0x2208
-#       define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT  16
-#define RADEON_SE_TCL_SCALAR_DATA_REG       0x220C
-#define RADEON_SURFACE_ACCESS_FLAGS	0x0bf8
-#define RADEON_SURFACE_ACCESS_CLR	0x0bfc
-#define RADEON_SURFACE_CNTL		0x0b00
-#	define RADEON_SURF_TRANSLATION_DIS	(1 << 8)
-#	define RADEON_NONSURF_AP0_SWP_MASK	(3 << 20)
-#	define RADEON_NONSURF_AP0_SWP_LITTLE	(0 << 20)
-#	define RADEON_NONSURF_AP0_SWP_BIG16	(1 << 20)
-#	define RADEON_NONSURF_AP0_SWP_BIG32	(2 << 20)
-#	define RADEON_NONSURF_AP1_SWP_MASK	(3 << 22)
-#	define RADEON_NONSURF_AP1_SWP_LITTLE	(0 << 22)
-#	define RADEON_NONSURF_AP1_SWP_BIG16	(1 << 22)
-#	define RADEON_NONSURF_AP1_SWP_BIG32	(2 << 22)
-#define RADEON_SURFACE0_INFO		0x0b0c
-#	define RADEON_SURF_PITCHSEL_MASK	(0x1ff << 0)
-#	define RADEON_SURF_TILE_MODE_MASK	(3 << 16)
-#	define RADEON_SURF_TILE_MODE_MACRO	(0 << 16)
-#	define RADEON_SURF_TILE_MODE_MICRO	(1 << 16)
-#	define RADEON_SURF_TILE_MODE_32BIT_Z	(2 << 16)
-#	define RADEON_SURF_TILE_MODE_16BIT_Z	(3 << 16)
-#define RADEON_SURFACE0_LOWER_BOUND	0x0b04
-#define RADEON_SURFACE0_UPPER_BOUND	0x0b08
-#define RADEON_SURFACE1_INFO		0x0b1c
-#define RADEON_SURFACE1_LOWER_BOUND	0x0b14
-#define RADEON_SURFACE1_UPPER_BOUND	0x0b18
-#define RADEON_SURFACE2_INFO		0x0b2c
-#define RADEON_SURFACE2_LOWER_BOUND	0x0b24
-#define RADEON_SURFACE2_UPPER_BOUND	0x0b28
-#define RADEON_SURFACE3_INFO		0x0b3c
-#define RADEON_SURFACE3_LOWER_BOUND	0x0b34
-#define RADEON_SURFACE3_UPPER_BOUND	0x0b38
-#define RADEON_SURFACE4_INFO		0x0b4c
-#define RADEON_SURFACE4_LOWER_BOUND	0x0b44
-#define RADEON_SURFACE4_UPPER_BOUND	0x0b48
-#define RADEON_SURFACE5_INFO		0x0b5c
-#define RADEON_SURFACE5_LOWER_BOUND	0x0b54
-#define RADEON_SURFACE5_UPPER_BOUND	0x0b58
-#define RADEON_SURFACE6_INFO		0x0b6c
-#define RADEON_SURFACE6_LOWER_BOUND	0x0b64
-#define RADEON_SURFACE6_UPPER_BOUND	0x0b68
-#define RADEON_SURFACE7_INFO		0x0b7c
-#define RADEON_SURFACE7_LOWER_BOUND	0x0b74
-#define RADEON_SURFACE7_UPPER_BOUND	0x0b78
-#define RADEON_SW_SEMAPHORE		0x013c
-
-#define RADEON_WAIT_UNTIL		0x1720
-#	define RADEON_WAIT_CRTC_PFLIP		(1 << 0)
-#	define RADEON_WAIT_2D_IDLECLEAN		(1 << 16)
-#	define RADEON_WAIT_3D_IDLECLEAN		(1 << 17)
-#	define RADEON_WAIT_HOST_IDLECLEAN	(1 << 18)
-
-#define RADEON_RB3D_ZMASKOFFSET		0x1c34
-#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
-#	define RADEON_DEPTH_FORMAT_16BIT_INT_Z	(0 << 0)
-#	define RADEON_DEPTH_FORMAT_24BIT_INT_Z	(2 << 0)
-
-
-/* CP registers */
-#define RADEON_CP_ME_RAM_ADDR		0x07d4
-#define RADEON_CP_ME_RAM_RADDR		0x07d8
-#define RADEON_CP_ME_RAM_DATAH		0x07dc
-#define RADEON_CP_ME_RAM_DATAL		0x07e0
-
-#define RADEON_CP_RB_BASE		0x0700
-#define RADEON_CP_RB_CNTL		0x0704
-#	define RADEON_BUF_SWAP_32BIT		(2 << 16)
-#define RADEON_CP_RB_RPTR_ADDR		0x070c
-#define RADEON_CP_RB_RPTR		0x0710
-#define RADEON_CP_RB_WPTR		0x0714
-
-#define RADEON_CP_RB_WPTR_DELAY		0x0718
-#	define RADEON_PRE_WRITE_TIMER_SHIFT	0
-#	define RADEON_PRE_WRITE_LIMIT_SHIFT	23
-
-#define RADEON_CP_IB_BASE		0x0738
-
-#define RADEON_CP_CSQ_CNTL		0x0740
-#	define RADEON_CSQ_CNT_PRIMARY_MASK	(0xff << 0)
-#	define RADEON_CSQ_PRIDIS_INDDIS		(0 << 28)
-#	define RADEON_CSQ_PRIPIO_INDDIS		(1 << 28)
-#	define RADEON_CSQ_PRIBM_INDDIS		(2 << 28)
-#	define RADEON_CSQ_PRIPIO_INDBM		(3 << 28)
-#	define RADEON_CSQ_PRIBM_INDBM		(4 << 28)
-#	define RADEON_CSQ_PRIPIO_INDPIO		(15 << 28)
-
-#define RADEON_AIC_CNTL			0x01d0
-#	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
-#define RADEON_AIC_STAT			0x01d4
-#define RADEON_AIC_PT_BASE		0x01d8
-#define RADEON_AIC_LO_ADDR		0x01dc
-#define RADEON_AIC_HI_ADDR		0x01e0
-#define RADEON_AIC_TLB_ADDR		0x01e4
-#define RADEON_AIC_TLB_DATA		0x01e8
-
-/* CP command packets */
-#define RADEON_CP_PACKET0		0x00000000
-#	define RADEON_ONE_REG_WR		(1 << 15)
-#define RADEON_CP_PACKET1		0x40000000
-#define RADEON_CP_PACKET2		0x80000000
-#define RADEON_CP_PACKET3		0xC0000000
-#	define RADEON_3D_RNDR_GEN_INDX_PRIM	0x00002300
-#	define RADEON_WAIT_FOR_IDLE		0x00002600
-#	define RADEON_3D_DRAW_VBUF		0x00002800
-#	define RADEON_3D_DRAW_IMMD		0x00002900
-#	define RADEON_3D_DRAW_INDX		0x00002A00
-#	define RADEON_3D_LOAD_VBPNTR		0x00002F00
-#	define RADEON_CNTL_HOSTDATA_BLT		0x00009400
-#	define RADEON_CNTL_PAINT_MULTI		0x00009A00
-#	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
-#       define RADEON_CCE_SET_SCISSORS          0xC0001E00
-
-#define RADEON_CP_PACKET_MASK		0xC0000000
-#define RADEON_CP_PACKET_COUNT_MASK	0x3fff0000
-#define RADEON_CP_PACKET0_REG_MASK	0x000007ff
-#define RADEON_CP_PACKET1_REG0_MASK	0x000007ff
-#define RADEON_CP_PACKET1_REG1_MASK	0x003ff800
-
-#define RADEON_VTX_Z_PRESENT			(1 << 31)
-#define RADEON_VTX_PKCOLOR_PRESENT		(1 << 3)
-
-#define RADEON_PRIM_TYPE_NONE			(0 << 0)
-#define RADEON_PRIM_TYPE_POINT			(1 << 0)
-#define RADEON_PRIM_TYPE_LINE			(2 << 0)
-#define RADEON_PRIM_TYPE_LINE_STRIP		(3 << 0)
-#define RADEON_PRIM_TYPE_TRI_LIST		(4 << 0)
-#define RADEON_PRIM_TYPE_TRI_FAN		(5 << 0)
-#define RADEON_PRIM_TYPE_TRI_STRIP		(6 << 0)
-#define RADEON_PRIM_TYPE_TRI_TYPE2		(7 << 0)
-#define RADEON_PRIM_TYPE_RECT_LIST		(8 << 0)
-#define RADEON_PRIM_TYPE_3VRT_POINT_LIST	(9 << 0)
-#define RADEON_PRIM_TYPE_3VRT_LINE_LIST		(10 << 0)
-#define RADEON_PRIM_TYPE_MASK                   0xf
-#define RADEON_PRIM_WALK_IND			(1 << 4)
-#define RADEON_PRIM_WALK_LIST			(2 << 4)
-#define RADEON_PRIM_WALK_RING			(3 << 4)
-#define RADEON_COLOR_ORDER_BGRA			(0 << 6)
-#define RADEON_COLOR_ORDER_RGBA			(1 << 6)
-#define RADEON_MAOS_ENABLE			(1 << 7)
-#define RADEON_VTX_FMT_R128_MODE		(0 << 8)
-#define RADEON_VTX_FMT_RADEON_MODE		(1 << 8)
-#define RADEON_NUM_VERTICES_SHIFT		16
-
-#define RADEON_COLOR_FORMAT_CI8		2
-#define RADEON_COLOR_FORMAT_ARGB1555	3
-#define RADEON_COLOR_FORMAT_RGB565	4
-#define RADEON_COLOR_FORMAT_ARGB8888	6
-#define RADEON_COLOR_FORMAT_RGB332	7
-#define RADEON_COLOR_FORMAT_RGB8	9
-#define RADEON_COLOR_FORMAT_ARGB4444	15
-
-#define RADEON_TXFORMAT_I8		0
-#define RADEON_TXFORMAT_AI88		1
-#define RADEON_TXFORMAT_RGB332		2
-#define RADEON_TXFORMAT_ARGB1555	3
-#define RADEON_TXFORMAT_RGB565		4
-#define RADEON_TXFORMAT_ARGB4444	5
-#define RADEON_TXFORMAT_ARGB8888	6
-#define RADEON_TXFORMAT_RGBA8888	7
-
-#define R200_PP_TXCBLEND_0                0x2f00
-#define R200_PP_TXCBLEND_1                0x2f10
-#define R200_PP_TXCBLEND_2                0x2f20
-#define R200_PP_TXCBLEND_3                0x2f30
-#define R200_PP_TXCBLEND_4                0x2f40
-#define R200_PP_TXCBLEND_5                0x2f50
-#define R200_PP_TXCBLEND_6                0x2f60
-#define R200_PP_TXCBLEND_7                0x2f70
-#define R200_SE_TCL_LIGHT_MODEL_CTL_0     0x2268 
-#define R200_PP_TFACTOR_0                 0x2ee0
-#define R200_SE_VTX_FMT_0                 0x2088
-#define R200_SE_VAP_CNTL                  0x2080
-#define R200_SE_TCL_MATRIX_SEL_0          0x2230
-#define R200_SE_TCL_TEX_PROC_CTL_2        0x22a8 
-#define R200_SE_TCL_UCP_VERT_BLEND_CTL    0x22c0 
-#define R200_PP_TXFILTER_5                0x2ca0 
-#define R200_PP_TXFILTER_4                0x2c80 
-#define R200_PP_TXFILTER_3                0x2c60 
-#define R200_PP_TXFILTER_2                0x2c40 
-#define R200_PP_TXFILTER_1                0x2c20 
-#define R200_PP_TXFILTER_0                0x2c00 
-#define R200_PP_TXOFFSET_5                0x2d78
-#define R200_PP_TXOFFSET_4                0x2d60
-#define R200_PP_TXOFFSET_3                0x2d48
-#define R200_PP_TXOFFSET_2                0x2d30
-#define R200_PP_TXOFFSET_1                0x2d18
-#define R200_PP_TXOFFSET_0                0x2d00
-#define R200_RE_AUX_SCISSOR_CNTL          0x26f0
-#define R200_SE_VTE_CNTL                  0x20b0
-#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL   0x2250
-#define R200_PP_TAM_DEBUG3                0x2d9c
-#define R200_PP_CNTL_X                    0x2cc4
-#define R200_SE_VAP_CNTL_STATUS           0x2140
-#define R200_RE_SCISSOR_TL_0              0x1cd8
-#define R200_RE_SCISSOR_TL_1              0x1ce0
-#define R200_RE_SCISSOR_TL_2              0x1ce8
-#define R200_RB3D_DEPTHXY_OFFSET          0x1d60 
-#define R200_RE_AUX_SCISSOR_CNTL          0x26f0
-#define R200_SE_VTX_STATE_CNTL            0x2180
-#define R200_RE_POINTSIZE                 0x2648
-#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2554
-
-
-#define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
-#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000
-#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT                 0x00000012
-#define SE_VTE_CNTL__VTX_XY_FMT_MASK                       0x00000100
-#define SE_VTE_CNTL__VTX_Z_FMT_MASK                        0x00000200
-#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK                  0x00000001
-#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK                  0x00000002
-#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT               0x0000000b
-#define R200_3D_DRAW_IMMD_2      0xC0003500
-#define R200_SE_VTX_FMT_1                 0x208c
-#define R200_RE_CNTL                      0x1c50 
-
-
-/* Constants */
-#define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
-
-#define RADEON_LAST_FRAME_REG		RADEON_SCRATCH_REG0
-#define RADEON_LAST_DISPATCH_REG	RADEON_SCRATCH_REG1
-#define RADEON_LAST_CLEAR_REG		RADEON_SCRATCH_REG2
-#define RADEON_LAST_DISPATCH		1
-
-#define RADEON_MAX_VB_AGE		0x7fffffff
-#define RADEON_MAX_VB_VERTS		(0xffff)
-
-#define RADEON_RING_HIGH_MARK		128
-
-
-
-#define RADEON_BASE(reg)	((unsigned long)(dev_priv->mmio->handle))
-#define RADEON_ADDR(reg)	(RADEON_BASE( reg ) + reg)
-
-#define RADEON_READ(reg)	readl( (volatile u32 *) RADEON_ADDR(reg) )
-#define RADEON_WRITE(reg,val)	writel( (val), (volatile u32 *) RADEON_ADDR(reg) )
-
-#define RADEON_READ8(reg)	readb( (volatile u8 *) RADEON_ADDR(reg) )
-#define RADEON_WRITE8(reg,val)	writeb( (val), (volatile u8 *) RADEON_ADDR(reg) )
-
-#define RADEON_WRITE_PLL( addr, val )					\
-do {									\
-	RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,				\
-		       ((addr) & 0x1f) | RADEON_PLL_WR_EN );		\
-	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
-} while (0)
-
-extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
-
-
-#define CP_PACKET0( reg, n )						\
-	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
-#define CP_PACKET0_TABLE( reg, n )					\
-	(RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
-#define CP_PACKET1( reg0, reg1 )					\
-	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
-#define CP_PACKET2()							\
-	(RADEON_CP_PACKET2)
-#define CP_PACKET3( pkt, n )						\
-	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
-
-
-/* ================================================================
- * Engine control helper macros
- */
-
-#define RADEON_WAIT_UNTIL_2D_IDLE() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_3D_IDLE() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_IDLE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
-		   RADEON_WAIT_3D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( RADEON_WAIT_CRTC_PFLIP );				\
-} while (0)
-
-#define RADEON_FLUSH_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB2D_DC_FLUSH );				\
-} while (0)
-
-#define RADEON_PURGE_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );				\
-} while (0)
-
-#define RADEON_FLUSH_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
-} while (0)
-
-#define RADEON_PURGE_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
-} while (0)
-
-
-/* ================================================================
- * Misc helper macros
- */
-
-#define LOCK_TEST_WITH_RETURN( dev )					\
-do {									\
-	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
-	     dev->lock.pid != current->pid ) {				\
-		DRM_ERROR( "%s called without lock held\n",		\
-			   __FUNCTION__ );				\
-		return -EINVAL;						\
-	}								\
-} while (0)
-
-#define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i;	\
-	if ( ring->space < ring->high_mark ) {				\
-		for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	\
-			radeon_update_ring_snapshot( ring );		\
-			if ( ring->space >= ring->high_mark )		\
-				goto __ring_space_done;			\
-			udelay( 1 );					\
-		}							\
-		DRM_ERROR( "ring space check from memory failed, reading register...\n" );	\
-		/* If ring space check fails from RAM, try reading the	\
-		   register directly */					\
-		ring->space = 4 * ( RADEON_READ( RADEON_CP_RB_RPTR ) - ring->tail );	\
-		if ( ring->space <= 0 )					\
-			ring->space += ring->size;			\
-		if ( ring->space >= ring->high_mark )			\
-			goto __ring_space_done;				\
-									\
-		DRM_ERROR( "ring space check failed!\n" );		\
-		return -EBUSY;						\
-	}								\
- __ring_space_done:							\
-} while (0)
-
-#define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
-	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
-		int __ret = radeon_do_cp_idle( dev_priv );		\
-		if ( __ret < 0 ) return __ret;				\
-		sarea_priv->last_dispatch = 0;				\
-		radeon_freelist_reset( dev );				\
-	}								\
-} while (0)
-
-#define RADEON_DISPATCH_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-#define RADEON_FRAME_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-#define RADEON_CLEAR_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-
-/* ================================================================
- * Ring control
- */
-
-#if defined(__powerpc__)
-#define radeon_flush_write_combine()	(void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine()	mb()
-#endif
-
-
-#define RADEON_VERBOSE	0
-
-#define RING_LOCALS	int write, _nr; unsigned int mask; volatile u32 *ring;
-
-#define BEGIN_RING( n ) do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
-			   n, __FUNCTION__ );				\
-	}								\
-	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
-                COMMIT_RING();						\
-		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
-	}								\
-	_nr = n; dev_priv->ring.space -= (n) * sizeof(u32);		\
-	ring = dev_priv->ring.start;					\
-	write = dev_priv->ring.tail;					\
-	mask = dev_priv->ring.tail_mask;				\
-} while (0)
-
-#define ADVANCE_RING() do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",	\
-			  write, dev_priv->ring.tail );			\
-	}								\
-	if (((dev_priv->ring.tail + _nr) & mask) != write) {		\
-		DRM_ERROR( 						\
-			"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",	\
-			((dev_priv->ring.tail + _nr) & mask),		\
-			write, __LINE__);						\
-	} else								\
-		dev_priv->ring.tail = write;				\
-} while (0)
-
-#define COMMIT_RING() do {					    \
-	RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );		    \
-} while (0)
-
-#define OUT_RING( x ) do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
-			   (unsigned int)(x), write );			\
-	}								\
-	ring[write++] = (x);						\
-	write &= mask;							\
-} while (0)
-
-#define OUT_RING_REG( reg, val ) do {					\
-	OUT_RING( CP_PACKET0( reg, 0 ) );				\
-	OUT_RING( val );						\
-} while (0)
-
-
-#define OUT_RING_USER_TABLE( tab, sz ) do {			\
-	int _size = (sz);					\
-	int *_tab = (tab);					\
-								\
-	if (write + _size > mask) {				\
-		int i = (mask+1) - write;			\
-		if (__copy_from_user( (int *)(ring+write),	\
-				      _tab, i*4 ))		\
-			return -EFAULT;				\
-		write = 0;					\
-		_size -= i;					\
-		_tab += i;					\
-	}							\
-								\
-	if (_size && __copy_from_user( (int *)(ring+write),	\
-			               _tab, _size*4 ))		\
-		return -EFAULT;					\
-								\
-	write += _size;						\
-	write &= mask;						\
-} while (0)
-
-
-#define RADEON_PERFORMANCE_BOXES	0
-
-#endif /* __RADEON_DRV_H__ */
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
deleted file mode 100644
index f199d2cb..00000000
--- a/linux/radeon_state.c
+++ /dev/null
@@ -1,2111 +0,0 @@
-/* radeon_state.c -- State support for Radeon -*- linux-c -*-
- *
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- *    Kevin E. Martin <martin@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "radeon.h"
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-#include <linux/delay.h>
-
-
-/* ================================================================
- * CP hardware state programming functions
- */
-
-static inline void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
-					  drm_clip_rect_t *box )
-{
-	RING_LOCALS;
-
-	DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
-		   box->x1, box->y1, box->x2, box->y2 );
-
-	BEGIN_RING( 4 );
-	OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
-	OUT_RING( (box->y1 << 16) | box->x1 );
-	OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
-/*     OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );*/
-	OUT_RING( (box->y2 << 16) | box->x2 );
-	ADVANCE_RING();
-}
-
-/* Emit 1.1 state
- */
-static void radeon_emit_state( drm_radeon_private_t *dev_priv,
-			       drm_radeon_context_regs_t *ctx,
-			       drm_radeon_texture_regs_t *tex,
-			       unsigned int dirty )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
-
-	if ( dirty & RADEON_UPLOAD_CONTEXT ) {
-		BEGIN_RING( 14 );
-		OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
-		OUT_RING( ctx->pp_misc );
-		OUT_RING( ctx->pp_fog_color );
-		OUT_RING( ctx->re_solid_color );
-		OUT_RING( ctx->rb3d_blendcntl );
-		OUT_RING( ctx->rb3d_depthoffset );
-		OUT_RING( ctx->rb3d_depthpitch );
-		OUT_RING( ctx->rb3d_zstencilcntl );
-		OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
-		OUT_RING( ctx->pp_cntl );
-		OUT_RING( ctx->rb3d_cntl );
-		OUT_RING( ctx->rb3d_coloroffset );
-		OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
-		OUT_RING( ctx->rb3d_colorpitch );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_VERTFMT ) {
-		BEGIN_RING( 2 );
-		OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
-		OUT_RING( ctx->se_coord_fmt );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_LINE ) {
-		BEGIN_RING( 5 );
-		OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
-		OUT_RING( ctx->re_line_pattern );
-		OUT_RING( ctx->re_line_state );
-		OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
-		OUT_RING( ctx->se_line_width );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
-		BEGIN_RING( 5 );
-		OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
-		OUT_RING( ctx->pp_lum_matrix );
-		OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
-		OUT_RING( ctx->pp_rot_matrix_0 );
-		OUT_RING( ctx->pp_rot_matrix_1 );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_MASKS ) {
-		BEGIN_RING( 4 );
-		OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
-		OUT_RING( ctx->rb3d_stencilrefmask );
-		OUT_RING( ctx->rb3d_ropcntl );
-		OUT_RING( ctx->rb3d_planemask );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
-		BEGIN_RING( 7 );
-		OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
-		OUT_RING( ctx->se_vport_xscale );
-		OUT_RING( ctx->se_vport_xoffset );
-		OUT_RING( ctx->se_vport_yscale );
-		OUT_RING( ctx->se_vport_yoffset );
-		OUT_RING( ctx->se_vport_zscale );
-		OUT_RING( ctx->se_vport_zoffset );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_SETUP ) {
-		BEGIN_RING( 4 );
-		OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
-		OUT_RING( ctx->se_cntl );
-		OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
-		OUT_RING( ctx->se_cntl_status );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_MISC ) {
-		BEGIN_RING( 2 );
-		OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
-		OUT_RING( ctx->re_misc );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_TEX0 ) {
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
-		OUT_RING( tex[0].pp_txfilter );
-		OUT_RING( tex[0].pp_txformat );
-		OUT_RING( tex[0].pp_txoffset );
-		OUT_RING( tex[0].pp_txcblend );
-		OUT_RING( tex[0].pp_txablend );
-		OUT_RING( tex[0].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
-		OUT_RING( tex[0].pp_border_color );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_TEX1 ) {
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
-		OUT_RING( tex[1].pp_txfilter );
-		OUT_RING( tex[1].pp_txformat );
-		OUT_RING( tex[1].pp_txoffset );
-		OUT_RING( tex[1].pp_txcblend );
-		OUT_RING( tex[1].pp_txablend );
-		OUT_RING( tex[1].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
-		OUT_RING( tex[1].pp_border_color );
-		ADVANCE_RING();
-	}
-
-	if ( dirty & RADEON_UPLOAD_TEX2 ) {
-		BEGIN_RING( 9 );
-		OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
-		OUT_RING( tex[2].pp_txfilter );
-		OUT_RING( tex[2].pp_txformat );
-		OUT_RING( tex[2].pp_txoffset );
-		OUT_RING( tex[2].pp_txcblend );
-		OUT_RING( tex[2].pp_txablend );
-		OUT_RING( tex[2].pp_tfactor );
-		OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
-		OUT_RING( tex[2].pp_border_color );
-		ADVANCE_RING();
-	}
-}
-
-/* Emit 1.2 state
- */
-static void radeon_emit_state2( drm_radeon_private_t *dev_priv,
-				drm_radeon_state_t *state )
-{
-	RING_LOCALS;
-
-	if (state->dirty & RADEON_UPLOAD_ZBIAS) {
-		BEGIN_RING( 3 );
-		OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
-		OUT_RING( state->context2.se_zbias_factor ); 
-		OUT_RING( state->context2.se_zbias_constant ); 
-		ADVANCE_RING();
-	}
-
-	radeon_emit_state( dev_priv, &state->context, 
-			   state->tex, state->dirty );
-}
-
-/* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
- * 1.3 cmdbuffers allow all previous state to be updated as well as
- * the tcl scalar and vector areas.  
- */
-static struct { 
-	int start; 
-	int len; 
-	const char *name;
-} packet[RADEON_MAX_STATE_PACKETS] = {
-	{ RADEON_PP_MISC,7,"RADEON_PP_MISC" },
-	{ RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
-	{ RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
-	{ RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
-	{ RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
-	{ RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
-	{ RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
-	{ RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
-	{ RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
-	{ RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
-	{ RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
-	{ RADEON_RE_MISC,1,"RADEON_RE_MISC" },
-	{ RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
-	{ RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
-	{ RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
-	{ RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
-	{ RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
-	{ RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
-	{ RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
-	{ RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
-	{ RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
-	{ R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
-	{ R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
-	{ R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
-	{ R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
-	{ R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
-	{ R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
-	{ R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
-	{ R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
-	{ R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
-	{ R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
-	{ R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
-	{ R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
-	{ R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
-	{ R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
-	{ R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
-	{ R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
-	{ R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
-	{ R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
-	{ R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
-	{ R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
-	{ R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
-	{ R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
-	{ R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
-	{ R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
-	{ R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
-	{ R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
-	{ R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
-	{ R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
-	{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
-	{ R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
-	{ R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 
-	{ R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 
-	{ R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 
-	{ R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 
-	{ R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 
-	{ R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 
-	{ R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 
-	{ R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 
-	{ R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 
-	{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
-};
-
-
-
-
-
-
-
-
-
-
-#if RADEON_PERFORMANCE_BOXES
-/* ================================================================
- * Performance monitoring functions
- */
-
-static void radeon_clear_box( drm_radeon_private_t *dev_priv,
-			      int x, int y, int w, int h,
-			      int r, int g, int b )
-{
-	u32 pitch, offset;
-	u32 color;
-	RING_LOCALS;
-
-	switch ( dev_priv->color_fmt ) {
-	case RADEON_COLOR_FORMAT_RGB565:
-		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
-		break;
-	case RADEON_COLOR_FORMAT_ARGB8888:
-	default:
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
-		break;
-	}
-
-	offset = dev_priv->back_offset;
-	pitch = dev_priv->back_pitch >> 3;
-
-	BEGIN_RING( 6 );
-
-	OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-		  RADEON_GMC_BRUSH_SOLID_COLOR |
-		  (dev_priv->color_fmt << 8) |
-		  RADEON_GMC_SRC_DATATYPE_COLOR |
-		  RADEON_ROP3_P |
-		  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-	OUT_RING( (pitch << 22) | (offset >> 5) );
-	OUT_RING( color );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
-{
-	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
-		radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
-	} else {
-		atomic_set( &dev_priv->idle_count, 0 );
-	}
-}
-
-#endif
-
-
-/* ================================================================
- * CP command dispatch functions
- */
-
-static void radeon_cp_dispatch_clear( drm_device_t *dev,
-				      drm_radeon_clear_t *clear,
-				      drm_radeon_clear_rect_t *depth_boxes )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	unsigned int flags = clear->flags;
-	u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( __FUNCTION__": flags = 0x%x\n", flags );
-
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
-		unsigned int tmp = flags;
-		flags &= ~(RADEON_FRONT | RADEON_BACK);
-		if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
-		if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
-	}
-
-	if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
-
-		BEGIN_RING( 4 );
-
-		/* Ensure the 3D stream is idle before doing a
-		 * 2D fill to clear the front or back buffer.
-		 */
-		RADEON_WAIT_UNTIL_3D_IDLE();
-		
-		OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
-		OUT_RING( clear->color_mask );
-
-		ADVANCE_RING();
-
-		/* Make sure we restore the 3D state next time.
-		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
-
-		for ( i = 0 ; i < nbox ; i++ ) {
-			int x = pbox[i].x1;
-			int y = pbox[i].y1;
-			int w = pbox[i].x2 - x;
-			int h = pbox[i].y2 - y;
-
-			DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-				   x, y, w, h, flags );
-
-			if ( flags & RADEON_FRONT ) {
-				BEGIN_RING( 6 );
-				
-				OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-					  RADEON_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->color_fmt << 8) |
-					  RADEON_GMC_SRC_DATATYPE_COLOR |
-					  RADEON_ROP3_P |
-					  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-				OUT_RING( dev_priv->front_pitch_offset );
-				OUT_RING( clear->clear_color );
-				
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (w << 16) | h );
-				
-				ADVANCE_RING();
-			}
-			
-			if ( flags & RADEON_BACK ) {
-				BEGIN_RING( 6 );
-				
-				OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-					  RADEON_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->color_fmt << 8) |
-					  RADEON_GMC_SRC_DATATYPE_COLOR |
-					  RADEON_ROP3_P |
-					  RADEON_GMC_CLR_CMP_CNTL_DIS );
-				
-				OUT_RING( dev_priv->back_pitch_offset );
-				OUT_RING( clear->clear_color );
-
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (w << 16) | h );
-
-				ADVANCE_RING();
-			}
-		}
-	}
-
-	/* We have to clear the depth and/or stencil buffers by
-	 * rendering a quad into just those buffers.  Thus, we have to
-	 * make sure the 3D engine is configured correctly.
-	 */
-	if ( dev_priv->is_r200 &&
-	     (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
-
-		int tempPP_CNTL;
-		int tempRE_CNTL;
-		int tempRB3D_CNTL;
-		int tempRB3D_ZSTENCILCNTL;
-		int tempRB3D_STENCILREFMASK;
-		int tempRB3D_PLANEMASK;
-		int tempSE_CNTL;
-		int tempSE_VTE_CNTL;
-		int tempSE_VTX_FMT_0;
-		int tempSE_VTX_FMT_1;
-		int tempSE_VAP_CNTL;
-		int tempRE_AUX_SCISSOR_CNTL;
-
-		tempPP_CNTL = 0;
-		tempRE_CNTL = 0;
-
-		tempRB3D_CNTL = depth_clear->rb3d_cntl;
-		tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
-
-		tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
-		tempRB3D_STENCILREFMASK = 0x0;
-
-		tempSE_CNTL = depth_clear->se_cntl;
-
-
-
-		/* Disable TCL */
-
-		tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
-				   (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
-
-		tempRB3D_PLANEMASK = 0x0;
-
-		tempRE_AUX_SCISSOR_CNTL = 0x0;
-
-		tempSE_VTE_CNTL =
-			SE_VTE_CNTL__VTX_XY_FMT_MASK |
-			SE_VTE_CNTL__VTX_Z_FMT_MASK;
-
-		/* Vertex format (X, Y, Z, W)*/
-		tempSE_VTX_FMT_0 =
-			SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
-			SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
-		tempSE_VTX_FMT_1 = 0x0;
-
-
-		/* 
-		 * Depth buffer specific enables 
-		 */
-		if (flags & RADEON_DEPTH) {
-			/* Enable depth buffer */
-			tempRB3D_CNTL |= RADEON_Z_ENABLE;
-		} else {
-			/* Disable depth buffer */
-			tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
-		}
-
-		/* 
-		 * Stencil buffer specific enables
-		 */
-		if ( flags & RADEON_STENCIL ) {
-			tempRB3D_CNTL |=  RADEON_STENCIL_ENABLE;
-			tempRB3D_STENCILREFMASK = clear->depth_mask; 
-		} else {
-			tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
-			tempRB3D_STENCILREFMASK = 0x00000000;
-		}
-
-		BEGIN_RING( 26 );
-		RADEON_WAIT_UNTIL_2D_IDLE();
-
-		OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
-		OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
-		OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
-		OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
-			      tempRB3D_ZSTENCILCNTL );
-		OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 
-			      tempRB3D_STENCILREFMASK );
-		OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
-		OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
-		OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
-		OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
-		OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
-		OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
-		OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, 
-			      tempRE_AUX_SCISSOR_CNTL );
-		ADVANCE_RING();
-
-		/* Make sure we restore the 3D state next time.
-		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
-
-		for ( i = 0 ; i < nbox ; i++ ) {
-			
-			/* Funny that this should be required -- 
-			 *  sets top-left?
-			 */
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-
-			BEGIN_RING( 14 );
-			OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
-			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
-				   RADEON_PRIM_WALK_RING |
-				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
-			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x3f800000 );
-			ADVANCE_RING();
-		}
-	} 
-	else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
-
-		rb3d_cntl = depth_clear->rb3d_cntl;
-
-		if ( flags & RADEON_DEPTH ) {
-			rb3d_cntl |=  RADEON_Z_ENABLE;
-		} else {
-			rb3d_cntl &= ~RADEON_Z_ENABLE;
-		}
-
-		if ( flags & RADEON_STENCIL ) {
-			rb3d_cntl |=  RADEON_STENCIL_ENABLE;
-			rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
-		} else {
-			rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
-			rb3d_stencilrefmask = 0x00000000;
-		}
-
-		BEGIN_RING( 13 );
-		RADEON_WAIT_UNTIL_2D_IDLE();
-
-		OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
-		OUT_RING( 0x00000000 );
-		OUT_RING( rb3d_cntl );
-		
-		OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
-			      depth_clear->rb3d_zstencilcntl );
-		OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
-			      rb3d_stencilrefmask );
-		OUT_RING_REG( RADEON_RB3D_PLANEMASK,
-			      0x00000000 );
-		OUT_RING_REG( RADEON_SE_CNTL,
-			      depth_clear->se_cntl );
-		ADVANCE_RING();
-
-		/* Make sure we restore the 3D state next time.
-		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
-
-		for ( i = 0 ; i < nbox ; i++ ) {
-			
-			/* Funny that this should be required -- 
-			 *  sets top-left?
-			 */
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-
-			BEGIN_RING( 15 );
-
-			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
-			OUT_RING( RADEON_VTX_Z_PRESENT |
-				  RADEON_VTX_PKCOLOR_PRESENT);
-			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
-				   RADEON_PRIM_WALK_RING |
-				   RADEON_MAOS_ENABLE |
-				   RADEON_VTX_FMT_RADEON_MODE |
-				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
-
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-			OUT_RING( 0x0 );
-
-			ADVANCE_RING();
-		}
-	}
-
-	/* Increment the clear counter.  The client-side 3D driver must
-	 * wait on this value before performing the clear ioctl.  We
-	 * need this because the card's so damned fast...
-	 */
-	dev_priv->sarea_priv->last_clear++;
-
-	BEGIN_RING( 4 );
-
-	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_dispatch_swap( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-#if RADEON_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	radeon_cp_performance_boxes( dev_priv );
-#endif
-
-	/* Wait for the 3D stream to idle before dispatching the bitblt.
-	 * This will prevent data corruption between the two streams.
-	 */
-	BEGIN_RING( 2 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
-	ADVANCE_RING();
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
-			   x, y, w, h );
-
-		BEGIN_RING( 7 );
-
-		OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  RADEON_GMC_SRC_DATATYPE_COLOR |
-			  RADEON_ROP3_S |
-			  RADEON_DP_SRC_SOURCE_MEMORY |
-			  RADEON_GMC_CLR_CMP_CNTL_DIS |
-			  RADEON_GMC_WR_MSK_DIS );
-		
-		/* Make this work even if front & back are flipped:
-		 */
-		if (dev_priv->current_page == 0) {
-			OUT_RING( dev_priv->back_pitch_offset );
-			OUT_RING( dev_priv->front_pitch_offset );
-		} 
-		else {
-			OUT_RING( dev_priv->front_pitch_offset );
-			OUT_RING( dev_priv->back_pitch_offset );
-		}
-
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
-
-		ADVANCE_RING();
-	}
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 4 );
-
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
-	RADEON_WAIT_UNTIL_2D_IDLE();
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_dispatch_flip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 
-		__FUNCTION__, 
-		dev_priv->current_page,
-		dev_priv->sarea_priv->pfCurrentPage);
-
-#if RADEON_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	radeon_cp_performance_boxes( dev_priv );
-#endif
-
-	BEGIN_RING( 4 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-/*
-	RADEON_WAIT_UNTIL_PAGE_FLIPPED();
-*/
-	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
-
-	if ( dev_priv->current_page == 0 ) {
-		OUT_RING( dev_priv->back_offset );
-		dev_priv->current_page = 1;
-	} else {
-		OUT_RING( dev_priv->front_offset );
-		dev_priv->current_page = 0;
-	}
-
-	ADVANCE_RING();
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
-
-	BEGIN_RING( 2 );
-
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-static int bad_prim_vertex_nr( int primitive, int nr )
-{
-	switch (primitive & RADEON_PRIM_TYPE_MASK) {
-	case RADEON_PRIM_TYPE_NONE:
-	case RADEON_PRIM_TYPE_POINT:
-		return nr < 1;
-	case RADEON_PRIM_TYPE_LINE:
-		return (nr & 1) || nr == 0;
-	case RADEON_PRIM_TYPE_LINE_STRIP:
-		return nr < 2;
-	case RADEON_PRIM_TYPE_TRI_LIST:
-	case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
-	case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
-	case RADEON_PRIM_TYPE_RECT_LIST:
-		return nr % 3 || nr == 0;
-	case RADEON_PRIM_TYPE_TRI_FAN:
-	case RADEON_PRIM_TYPE_TRI_STRIP:
-		return nr < 3;
-	default:
-		return 1;
-	}	
-}
-
-
-
-typedef struct {
-	unsigned int start;
-	unsigned int finish;
-	unsigned int prim;
-	unsigned int numverts;
-	unsigned int offset;   
-        unsigned int vc_format;
-} drm_radeon_tcl_prim_t;
-
-static void radeon_cp_dispatch_vertex( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       drm_radeon_tcl_prim_t *prim,
-				       drm_clip_rect_t *boxes,
-				       int nbox )
-
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_clip_rect_t box;
-	int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
-	int numverts = (int)prim->numverts;
-	int i = 0;
-	RING_LOCALS;
-
-	DRM_DEBUG("%s: hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
-		  __FUNCTION__,
-		  prim->prim,
-		  prim->vc_format,
-		  prim->start,
-		  prim->finish,
-		  prim->numverts);
-
-	if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
-		DRM_ERROR( "bad prim %x numverts %d\n", 
-			   prim->prim, prim->numverts );
-		return;
-	}
-
-	do {
-		/* Emit the next cliprect */
-		if ( i < nbox ) {
-			if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
-				return;
-
-			radeon_emit_clip_rect( dev_priv, &box );
-		}
-
-		/* Emit the vertex buffer rendering commands */
-		BEGIN_RING( 5 );
-
-		OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-		OUT_RING( offset );
-		OUT_RING( numverts );
-		OUT_RING( prim->vc_format );
-		OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
-			  RADEON_COLOR_ORDER_RGBA |
-			  RADEON_VTX_FMT_RADEON_MODE |
-			  (numverts << RADEON_NUM_VERTICES_SHIFT) );
-
-		ADVANCE_RING();
-
-		i++;
-	} while ( i < nbox );
-}
-
-
-
-static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-	RING_LOCALS;
-
-	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
-
-	/* Emit the vertex buffer age */
-	BEGIN_RING( 2 );
-	RADEON_DISPATCH_AGE( buf_priv->age );
-	ADVANCE_RING();
-
-	buf->pending = 1;
-	buf->used = 0;
-}
-
-static void radeon_cp_dispatch_indirect( drm_device_t *dev,
-					 drm_buf_t *buf,
-					 int start, int end )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
-
-	if ( start != end ) {
-		int offset = (dev_priv->agp_buffers_offset
-			      + buf->offset + start);
-		int dwords = (end - start + 3) / sizeof(u32);
-
-		/* Indirect buffer data must be an even number of
-		 * dwords, so if we've been given an odd number we must
-		 * pad the data with a Type-2 CP packet.
-		 */
-		if ( dwords & 1 ) {
-			u32 *data = (u32 *)
-				((char *)dev_priv->buffers->handle
-				 + buf->offset + start);
-			data[dwords++] = RADEON_CP_PACKET2;
-		}
-
-		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
-
-		OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
-
-		ADVANCE_RING();
-	}
-}
-
-
-static void radeon_cp_dispatch_indices( drm_device_t *dev,
-					drm_buf_t *elt_buf,
-					drm_radeon_tcl_prim_t *prim, 
-					drm_clip_rect_t *boxes,
-					int nbox )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_clip_rect_t box;
-	int offset = dev_priv->agp_buffers_offset + prim->offset;
-	u32 *data;
-	int dwords;
-	int i = 0;
-	int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
-	int count = (prim->finish - start) / sizeof(u16);
-
-	DRM_DEBUG("%s: hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
-		  __FUNCTION__,
-		  prim->prim,
-		  prim->vc_format,
-		  prim->start,
-		  prim->finish,
-		  prim->offset,
-		  prim->numverts);
-
-	if (bad_prim_vertex_nr( prim->prim, count )) {
-		DRM_ERROR( "bad prim %x count %d\n", 
-			   prim->prim, count );
-		return;
-	}
-
-
-	if ( start >= prim->finish ||
-	     (prim->start & 0x7) ) {
-		DRM_ERROR( "buffer prim %d\n", prim->prim );
-		return;
-	}
-
-	dwords = (prim->finish - prim->start + 3) / sizeof(u32);
-
-	data = (u32 *)((char *)dev_priv->buffers->handle +
-		       elt_buf->offset + prim->start);
-
-	data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
-	data[1] = offset;
-	data[2] = prim->numverts;
-	data[3] = prim->vc_format;
-	data[4] = (prim->prim |
-		   RADEON_PRIM_WALK_IND |
-		   RADEON_COLOR_ORDER_RGBA |
-		   RADEON_VTX_FMT_RADEON_MODE |
-		   (count << RADEON_NUM_VERTICES_SHIFT) );
-
-	do {
-		if ( i < nbox ) {
-			if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
-				return;
-			
-			radeon_emit_clip_rect( dev_priv, &box );
-		}
-
-		radeon_cp_dispatch_indirect( dev, elt_buf,
-					     prim->start,
-					     prim->finish );
-
-		i++;
-	} while ( i < nbox );
-
-}
-
-#define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
-
-static int radeon_cp_dispatch_texture( drm_device_t *dev,
-				       drm_radeon_texture_t *tex,
-				       drm_radeon_tex_image_t *image )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	u32 format;
-	u32 *buffer;
-	u8 *data;
-	int size, dwords, tex_width, blit_width;
-	u32 y, height;
-	int ret = 0, i;
-	RING_LOCALS;
-
-	/* FIXME: Be smarter about this...
-	 */
-	buf = radeon_freelist_get( dev );
-	if ( !buf ) return -EAGAIN;
-
-	DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
-		   tex->offset >> 10, tex->pitch, tex->format,
-		   image->x, image->y, image->width, image->height );
-
-	/* The compiler won't optimize away a division by a variable,
-	 * even if the only legal values are powers of two.  Thus, we'll
-	 * use a shift instead.
-	 */
-	switch ( tex->format ) {
-	case RADEON_TXFORMAT_ARGB8888:
-	case RADEON_TXFORMAT_RGBA8888:
-		format = RADEON_COLOR_FORMAT_ARGB8888;
-		tex_width = tex->width * 4;
-		blit_width = image->width * 4;
-		break;
-	case RADEON_TXFORMAT_AI88:
-	case RADEON_TXFORMAT_ARGB1555:
-	case RADEON_TXFORMAT_RGB565:
-	case RADEON_TXFORMAT_ARGB4444:
-		format = RADEON_COLOR_FORMAT_RGB565;
-		tex_width = tex->width * 2;
-		blit_width = image->width * 2;
-		break;
-	case RADEON_TXFORMAT_I8:
-	case RADEON_TXFORMAT_RGB332:
-		format = RADEON_COLOR_FORMAT_CI8;
-		tex_width = tex->width * 1;
-		blit_width = image->width * 1;
-		break;
-	default:
-		DRM_ERROR( "invalid texture format %d\n", tex->format );
-		return -EINVAL;
-	}
-
-	DRM_DEBUG( "   tex=%dx%d  blit=%d\n",
-		   tex_width, tex->height, blit_width );
-
-	/* Flush the pixel cache.  This ensures no pixel data gets mixed
-	 * up with the texture data from the host data blit, otherwise
-	 * part of the texture image may be corrupted.
-	 */
-	BEGIN_RING( 4 );
-
-	RADEON_FLUSH_CACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-
-#ifdef __BIG_ENDIAN
-	/* The Mesa texture functions provide the data in little endian as the
-	 * chip wants it, but we need to compensate for the fact that the CP
-	 * ring gets byte-swapped
-	 */
-	BEGIN_RING( 2 );
-	OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
-	ADVANCE_RING();
-#endif
-
-	/* Make a copy of the parameters in case we have to update them
-	 * for a multi-pass texture blit.
-	 */
-	y = image->y;
-	height = image->height;
-	data = (u8 *)image->data;
-
-	size = height * blit_width;
-
-	if ( size > RADEON_MAX_TEXTURE_SIZE ) {
-		/* Texture image is too large, do a multipass upload */
-		ret = -EAGAIN;
-
-		/* Adjust the blit size to fit the indirect buffer */
-		height = RADEON_MAX_TEXTURE_SIZE / blit_width;
-		size = height * blit_width;
-
-		/* Update the input parameters for next time */
-		image->y += height;
-		image->height -= height;
-		image->data = (char *)image->data + size;
-
-		if ( copy_to_user( tex->image, image, sizeof(*image) ) ) {
-			DRM_ERROR( "EFAULT on tex->image\n" );
-			return -EFAULT;
-		}
-	} else if ( size < 4 && size > 0 ) {
-		size = 4;
-	}
-
-	dwords = size / 4;
-
-	/* Dispatch the indirect buffer.
-	 */
-	buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
-
-	buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
-	buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-		     RADEON_GMC_BRUSH_NONE |
-		     (format << 8) |
-		     RADEON_GMC_SRC_DATATYPE_COLOR |
-		     RADEON_ROP3_S |
-		     RADEON_DP_SRC_SOURCE_HOST_DATA |
-		     RADEON_GMC_CLR_CMP_CNTL_DIS |
-		     RADEON_GMC_WR_MSK_DIS);
-
-	buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
-	buffer[3] = 0xffffffff;
-	buffer[4] = 0xffffffff;
-	buffer[5] = (y << 16) | image->x;
-	buffer[6] = (height << 16) | image->width;
-	buffer[7] = dwords;
-
-	buffer += 8;
-
-	if ( tex_width >= 32 ) {
-		/* Texture image width is larger than the minimum, so we
-		 * can upload it directly.
-		 */
-		if ( copy_from_user( buffer, data, dwords * sizeof(u32) ) ) {
-			DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
-			return -EFAULT;
-		}
-	} else {
-		/* Texture image width is less than the minimum, so we
-		 * need to pad out each image scanline to the minimum
-		 * width.
-		 */
-		for ( i = 0 ; i < tex->height ; i++ ) {
-			if ( copy_from_user( buffer, data, tex_width ) ) {
-				DRM_ERROR( "EFAULT on pad, %d bytes\n",
-					   tex_width );
-				return -EFAULT;
-			}
-			buffer += 8;
-			data += tex_width;
-		}
-	}
-
-	buf->pid = current->pid;
-	buf->used = (dwords + 8) * sizeof(u32);
-
-	radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
-	radeon_cp_discard_buffer( dev, buf );
-
-	/* Flush the pixel cache after the blit completes.  This ensures
-	 * the texture data is written out to memory before rendering
-	 * continues.
-	 */
-	BEGIN_RING( 4 );
-
-	RADEON_FLUSH_CACHE();
-	RADEON_WAIT_UNTIL_2D_IDLE();
-
-	ADVANCE_RING();
-
-	return ret;
-}
-
-static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 35 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
-	OUT_RING( 0x00000000 );
-
-	OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
-	}
-
-	ADVANCE_RING();
-}
-
-
-/* ================================================================
- * IOCTL functions
- */
-
-int radeon_cp_clear( struct inode *inode, struct file *filp,
-		     unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_clear_t clear;
-	drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &clear, (drm_radeon_clear_t *)arg,
-			     sizeof(clear) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
-
-	if ( copy_from_user( &depth_boxes, clear.depth_boxes,
-			     sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
-		return -EFAULT;
-
-	radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
-
-	COMMIT_RING();
-	return 0;
-}
-
-
-
-/* Not sure why this isn't set all the time:
- */ 
-static int radeon_do_init_pageflip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
-
-	BEGIN_RING( 4 );
-	RADEON_WAIT_UNTIL_3D_IDLE();
-	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
-	OUT_RING( dev_priv->crtc_offset_cntl | RADEON_CRTC_OFFSET_FLIP_CNTL );
-	ADVANCE_RING();
-
-
-	dev_priv->page_flipping = 1;
-	dev_priv->current_page = 0;
-	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
-
-	return 0;
-}
-
-int radeon_do_cleanup_pageflip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if (dev_priv->current_page != 0)
-		radeon_cp_dispatch_flip( dev );
-
-	/* FIXME: If the X server changes screen resolution, it
-	 * clobbers the value of RADEON_CRTC_OFFSET_CNTL, above,
-	 * leading to a flashing efect.
-	 */
-	dev_priv->page_flipping = 0;
-	return 0;
-}
-
-/* Swapping and flipping are different operations, need different ioctls.
- * They can & should be intermixed to support multiple 3d windows.  
- */
-int radeon_cp_flip( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if (!dev_priv->page_flipping) 
-		radeon_do_init_pageflip( dev );
-		
-	radeon_cp_dispatch_flip( dev );
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_swap( struct inode *inode, struct file *filp,
-		    unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
-
-	radeon_cp_dispatch_swap( dev );
-	dev_priv->sarea_priv->ctx_owner = 0;
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_vertex( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_vertex_t vertex;
-	drm_radeon_tcl_prim_t prim;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
-			     sizeof(vertex) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
-		   __FUNCTION__, current->pid,
-		   vertex.idx, vertex.count, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		return -EINVAL;
-	}
-
-	/* Build up a prim_t record:
-	 */
-	if (vertex.count) {
-		buf->used = vertex.count; /* not used? */
-
-		if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-			radeon_emit_state( dev_priv,
-					   &sarea_priv->context_state,
-					   sarea_priv->tex_state,
-					   sarea_priv->dirty );
-			
-			sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-					       RADEON_UPLOAD_TEX1IMAGES |
-					       RADEON_UPLOAD_TEX2IMAGES |
-					       RADEON_REQUIRE_QUIESCENCE);
-		}
-
-		prim.start = 0;
-		prim.finish = vertex.count; /* unused */
-		prim.prim = vertex.prim;
-		prim.numverts = vertex.count;
-		prim.vc_format = dev_priv->sarea_priv->vc_format;
-		
-		radeon_cp_dispatch_vertex( dev, buf, &prim,
-					   dev_priv->sarea_priv->boxes,
-					   dev_priv->sarea_priv->nbox );
-	}
-
-	if (vertex.discard) {
-		radeon_cp_discard_buffer( dev, buf );
-	}
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_indices( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_indices_t elts;
-	drm_radeon_tcl_prim_t prim;
-	int count;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &elts, (drm_radeon_indices_t *)arg,
-			     sizeof(elts) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
-		   __FUNCTION__, current->pid,
-		   elts.idx, elts.start, elts.end, elts.discard );
-
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-	if ( elts.prim < 0 ||
-	     elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[elts.idx];
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
-		return -EINVAL;
-	}
-
-	count = (elts.end - elts.start) / sizeof(u16);
-	elts.start -= RADEON_INDEX_PRIM_OFFSET;
-
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
-		return -EINVAL;
-	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
-		return -EINVAL;
-	}
-
-	buf->used = elts.end;
-
-	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-		radeon_emit_state( dev_priv,
-				   &sarea_priv->context_state,
-				   sarea_priv->tex_state,
-				   sarea_priv->dirty );
-
-		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-				       RADEON_UPLOAD_TEX1IMAGES |
-				       RADEON_UPLOAD_TEX2IMAGES |
-				       RADEON_REQUIRE_QUIESCENCE);
-	}
-
-
-	/* Build up a prim_t record:
-	 */
-	prim.start = elts.start;
-	prim.finish = elts.end; 
-	prim.prim = elts.prim;
-	prim.offset = 0;	/* offset from start of dma buffers */
-	prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
-	prim.vc_format = dev_priv->sarea_priv->vc_format;
-	
-	radeon_cp_dispatch_indices( dev, buf, &prim,
-				   dev_priv->sarea_priv->boxes,
-				   dev_priv->sarea_priv->nbox );
-	if (elts.discard) {
-		radeon_cp_discard_buffer( dev, buf );
-	}
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_texture( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_texture_t tex;
-	drm_radeon_tex_image_t image;
-	int ret;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &tex, (drm_radeon_texture_t *)arg, sizeof(tex) ) )
-		return -EFAULT;
-
-	if ( tex.image == NULL ) {
-		DRM_ERROR( "null texture image!\n" );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &image,
-			     (drm_radeon_tex_image_t *)tex.image,
-			     sizeof(image) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	ret = radeon_cp_dispatch_texture( dev, &tex, &image );
-
-	COMMIT_RING();
-	return ret;
-}
-
-int radeon_cp_stipple( struct inode *inode, struct file *filp,
-		       unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_stipple_t stipple;
-	u32 mask[32];
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( copy_from_user( &stipple, (drm_radeon_stipple_t *)arg,
-			     sizeof(stipple) ) )
-		return -EFAULT;
-
-	if ( copy_from_user( &mask, stipple.mask, 32 * sizeof(u32) ) )
-		return -EFAULT;
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	radeon_cp_dispatch_stipple( dev, mask );
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_indirect( struct inode *inode, struct file *filp,
-			unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_indirect_t indirect;
-	RING_LOCALS;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &indirect, (drm_radeon_indirect_t *)arg,
-			     sizeof(indirect) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
-
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-
-	buf = dma->buflist[indirect.idx];
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
-		return -EINVAL;
-	}
-
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf->used = indirect.end;
-
-	/* Wait for the 3D stream to idle before the indirect buffer
-	 * containing 2D acceleration commands is processed.
-	 */
-	BEGIN_RING( 2 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
-	ADVANCE_RING();
-
-	/* Dispatch the indirect buffer full of commands from the
-	 * X server.  This is insecure and is thus only available to
-	 * privileged clients.
-	 */
-	radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
-	if (indirect.discard) {
-		radeon_cp_discard_buffer( dev, buf );
-	}
-
-
-	COMMIT_RING();
-	return 0;
-}
-
-int radeon_cp_vertex2( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_vertex2_t vertex;
-	int i;
-	unsigned char laststate;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &vertex, (drm_radeon_vertex_t *)arg,
-			     sizeof(vertex) ) )
-		return -EFAULT;
-
-	DRM_DEBUG( __FUNCTION__": pid=%d index=%d discard=%d\n",
-		   current->pid, vertex.idx, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		return -EINVAL;
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-
-	if ( buf->pid != current->pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   current->pid, buf->pid );
-		return -EINVAL;
-	}
-
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		return -EINVAL;
-	}
-	
-	if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
-		return -EINVAL;
-
-	for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
-		drm_radeon_prim_t prim;
-		drm_radeon_tcl_prim_t tclprim;
-		
-		if ( copy_from_user( &prim, &vertex.prim[i], sizeof(prim) ) )
-			return -EFAULT;
-		
-		if ( prim.stateidx != laststate ) {
-			drm_radeon_state_t state;			       
-				
-			if ( copy_from_user( &state, 
-					     &vertex.state[prim.stateidx], 
-					     sizeof(state) ) )
-				return -EFAULT;
-
-			radeon_emit_state2( dev_priv, &state );
-
-			laststate = prim.stateidx;
-		}
-
-		tclprim.start = prim.start;
-		tclprim.finish = prim.finish;
-		tclprim.prim = prim.prim;
-		tclprim.vc_format = prim.vc_format;
-
-		if ( prim.prim & RADEON_PRIM_WALK_IND ) {
-			tclprim.offset = prim.numverts * 64;
-			tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
-
-			radeon_cp_dispatch_indices( dev, buf, &tclprim,
-						    sarea_priv->boxes,
-						    sarea_priv->nbox);
-		} else {
-			tclprim.numverts = prim.numverts;
-			tclprim.offset = 0; /* not used */
-
-			radeon_cp_dispatch_vertex( dev, buf, &tclprim,
-						   sarea_priv->boxes,
-						   sarea_priv->nbox);
-		}
-		
-		if (sarea_priv->nbox == 1)
-			sarea_priv->nbox = 0;
-	}
-
-	if ( vertex.discard ) {
-		radeon_cp_discard_buffer( dev, buf );
-	}
-
-	COMMIT_RING();
-	return 0;
-}
-
-
-static int radeon_emit_packets( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	int id = (int)header.packet.packet_id;
-	int sz = packet[id].len;
-	int reg = packet[id].start;
-	int *data = (int *)cmdbuf->buf;
-	RING_LOCALS;
-   
-	if (sz * sizeof(int) > cmdbuf->bufsz) 
-		return -EINVAL;
-
-	BEGIN_RING(sz+1);
-	OUT_RING( CP_PACKET0( reg, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
-	ADVANCE_RING();
-
-	cmdbuf->buf += sz * sizeof(int);
-	cmdbuf->bufsz -= sz * sizeof(int);
-	return 0;
-}
-
-static inline int radeon_emit_scalars( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	int sz = header.scalars.count;
-	int *data = (int *)cmdbuf->buf;
-	int start = header.scalars.offset;
-	int stride = header.scalars.stride;
-	RING_LOCALS;
-
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
-	ADVANCE_RING();
-	cmdbuf->buf += sz * sizeof(int);
-	cmdbuf->bufsz -= sz * sizeof(int);
-	return 0;
-}
-
-/* God this is ugly
- */
-static inline int radeon_emit_scalars2( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	int sz = header.scalars.count;
-	int *data = (int *)cmdbuf->buf;
-	int start = header.scalars.offset + 0x100;
-	int stride = header.scalars.stride;
-	RING_LOCALS;
-
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
-	OUT_RING_USER_TABLE( data, sz );
-	ADVANCE_RING();
-	cmdbuf->buf += sz * sizeof(int);
-	cmdbuf->bufsz -= sz * sizeof(int);
-	return 0;
-}
-
-static inline int radeon_emit_vectors( 
-	drm_radeon_private_t *dev_priv,
-	drm_radeon_cmd_header_t header,
-	drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	int sz = header.vectors.count;
-	int *data = (int *)cmdbuf->buf;
-	int start = (unsigned char)header.vectors.offset;
-	int stride = header.vectors.stride;
-	RING_LOCALS;
-
-	BEGIN_RING( 3+sz );
-	OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
-	OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
-	OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
-	OUT_RING_USER_TABLE( data, sz );
-	ADVANCE_RING();
-
-	cmdbuf->buf += sz * sizeof(int);
-	cmdbuf->bufsz -= sz * sizeof(int);
-	return 0;
-}
-
-
-static int radeon_emit_packet3( drm_device_t *dev,
-				drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	int cmdsz, tmp;
-	int *cmd = (int *)cmdbuf->buf;
-	RING_LOCALS;
-
-
-	DRM_DEBUG("%s\n", __FUNCTION__);
-
-	if (__get_user( tmp, &cmd[0]))
-		return -EFAULT;
-
-	cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
-
-	if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
-	    cmdsz * 4 > cmdbuf->bufsz)
-		return -EINVAL;
-
-	BEGIN_RING( cmdsz );
-	OUT_RING_USER_TABLE( cmd, cmdsz );
-	ADVANCE_RING();
-
-	cmdbuf->buf += cmdsz * 4;
-	cmdbuf->bufsz -= cmdsz * 4;
-	return 0;
-}
-
-
-static int radeon_emit_packet3_cliprect( drm_device_t *dev,
-					 drm_radeon_cmd_buffer_t *cmdbuf )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_clip_rect_t box;
-	int cmdsz, tmp;
-	int *cmd = (int *)cmdbuf->buf;
-	drm_clip_rect_t *boxes = cmdbuf->boxes;
-	int i = 0;
-	RING_LOCALS;
-
-	DRM_DEBUG("%s\n", __FUNCTION__);
-
-	if (__get_user( tmp, &cmd[0]))
-		return -EFAULT;
-
-	cmdsz = 2 + ((tmp & RADEON_CP_PACKET_COUNT_MASK) >> 16);
-
-	if ((tmp & 0xc0000000) != RADEON_CP_PACKET3 ||
-	    cmdsz * 4 > cmdbuf->bufsz)
-		return -EINVAL;
-
-	do {
-		if ( i < cmdbuf->nbox ) {
-			if (__copy_from_user( &box, &boxes[i], sizeof(box) ))
-				return -EFAULT;
-			radeon_emit_clip_rect( dev_priv, &box );
-		}
-		
-		BEGIN_RING( cmdsz );
-		OUT_RING_USER_TABLE( cmd, cmdsz );
-		ADVANCE_RING();
-
-	} while ( ++i < cmdbuf->nbox );
-
- 	if (cmdbuf->nbox == 1)
-		cmdbuf->nbox = 0;
-
-	cmdbuf->buf += cmdsz * 4;
-	cmdbuf->bufsz -= cmdsz * 4;
-	return 0;
-}
-
-
-
-int radeon_cp_cmdbuf( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf = 0;
-	int idx;
-	drm_radeon_cmd_buffer_t cmdbuf;
-	drm_radeon_cmd_header_t header;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &cmdbuf, (drm_radeon_cmd_buffer_t *)arg,
-			     sizeof(cmdbuf) ) ) {
-		DRM_ERROR("copy_from_user\n");
-		return -EFAULT;
-	}
-
-	DRM_DEBUG( __FUNCTION__": pid=%d\n", current->pid );
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-
-	if (verify_area( VERIFY_READ, cmdbuf.buf, cmdbuf.bufsz ))
-		return -EFAULT;
-
-	if (cmdbuf.nbox &&
-	    verify_area( VERIFY_READ, cmdbuf.boxes, 
-			 cmdbuf.nbox * sizeof(drm_clip_rect_t)))
-		return -EFAULT;
-
-	while ( cmdbuf.bufsz >= sizeof(header) ) {
-		
-		if (__get_user( header.i, (int *)cmdbuf.buf )) {
-			DRM_ERROR("__get_user %p\n", cmdbuf.buf);
-			return -EFAULT;
-		}
-
-		cmdbuf.buf += sizeof(header);
-		cmdbuf.bufsz -= sizeof(header);
-
-		switch (header.header.cmd_type) {
-		case RADEON_CMD_PACKET: 
-			DRM_DEBUG("RADEON_CMD_PACKET\n");
-			if (radeon_emit_packets( dev_priv, header, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_packets failed\n");
-				return -EINVAL;
-			}
-			break;
-
-		case RADEON_CMD_SCALARS:
-			DRM_DEBUG("RADEON_CMD_SCALARS\n");
-			if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_scalars failed\n");
-				return -EINVAL;
-			}
-			break;
-
-		case RADEON_CMD_VECTORS:
-			DRM_DEBUG("RADEON_CMD_VECTORS\n");
-			if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_vectors failed\n");
-				return -EINVAL;
-			}
-			break;
-
-		case RADEON_CMD_DMA_DISCARD:
-			DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
-			idx = header.dma.buf_idx;
-			if ( idx < 0 || idx >= dma->buf_count ) {
-				DRM_ERROR( "buffer index %d (of %d max)\n",
-					   idx, dma->buf_count - 1 );
-				return -EINVAL;
-			}
-
-			buf = dma->buflist[idx];
-			if ( buf->pid != current->pid || buf->pending ) {
-				DRM_ERROR( "bad buffer\n" );
-				return -EINVAL;
-			}
-
-			radeon_cp_discard_buffer( dev, buf );
-			break;
-
-		case RADEON_CMD_PACKET3:
-			DRM_DEBUG("RADEON_CMD_PACKET3\n");
-			if (radeon_emit_packet3( dev, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_packet3 failed\n");
-				return -EINVAL;
-			}
-			break;
-
-		case RADEON_CMD_PACKET3_CLIP:
-			DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
-			if (radeon_emit_packet3_cliprect( dev, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_packet3_clip failed\n");
-				return -EINVAL;
-			}
-			break;
-
-		case RADEON_CMD_SCALARS2:
-			DRM_DEBUG("RADEON_CMD_SCALARS2\n");
-			if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
-				DRM_ERROR("radeon_emit_scalars2 failed\n");
-				return -EINVAL;
-			}
-			break;
-		default:
-			DRM_ERROR("bad cmd_type %d at %p\n", 
-				  header.header.cmd_type,
-				  cmdbuf.buf - sizeof(header));
-			return -EINVAL;
-		}
-	}
-
-
-	DRM_DEBUG("DONE\n");
-	COMMIT_RING();
-	return 0;
-}
-
-
-
-int radeon_cp_getparam( struct inode *inode, struct file *filp,
-		      unsigned int cmd, unsigned long arg )
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_getparam_t param;
-	int value;
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		return -EINVAL;
-	}
-
-	if ( copy_from_user( &param, (drm_radeon_getparam_t *)arg,
-			     sizeof(param) ) ) {
-		DRM_ERROR("copy_from_user\n");
-		return -EFAULT;
-	}
-
-	DRM_DEBUG( __FUNCTION__": pid=%d\n", current->pid );
-
-	switch( param.param ) {
-	case RADEON_PARAM_AGP_BUFFER_OFFSET:
-		value = dev_priv->agp_buffers_offset;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if ( copy_to_user( param.value, &value, sizeof(int) ) ) {
-		DRM_ERROR( "copy_to_user\n" );
-		return -EFAULT;
-	}
-	
-	return 0;
-}
-
-
-
-
-
-
diff --git a/linux/sis.h b/linux/sis.h
index 02f03086..0bf3dfa9 100644
--- a/linux/sis.h
+++ b/linux/sis.h
@@ -42,6 +42,31 @@
 #define __HAVE_MTRR		1
 #define __HAVE_CTX_BITMAP	1
 
+#define DRIVER_AUTHOR	 "SIS"
+#define DRIVER_NAME	 "sis"
+#define DRIVER_DESC	 "SIS 300/630/540"
+#define DRIVER_DATE	 "20010503"
+#define DRIVER_MAJOR	 1
+#define DRIVER_MINOR	 0
+#define DRIVER_PATCHLEVEL  0
+
+#define DRIVER_IOCTLS \
+        [DRM_IOCTL_NR(SIS_IOCTL_FB_ALLOC)]   = { sis_fb_alloc,	  1, 0 }, \
+        [DRM_IOCTL_NR(SIS_IOCTL_FB_FREE)]    = { sis_fb_free,	  1, 0 }, \
+        /* AGP Memory Management */					  \
+        [DRM_IOCTL_NR(SIS_IOCTL_AGP_INIT)]   = { sisp_agp_init,	  1, 0 }, \
+        [DRM_IOCTL_NR(SIS_IOCTL_AGP_ALLOC)]  = { sisp_agp_alloc,  1, 0 }, \
+        [DRM_IOCTL_NR(SIS_IOCTL_AGP_FREE)]   = { sisp_agp_free,	  1, 0 }
+#if 0 /* these don't appear to be defined */
+	/* SIS Stereo */						 
+	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]    = { sis_control,	  1, 1 }, 
+        [DRM_IOCTL_NR(SIS_IOCTL_FLIP)]       = { sis_flip,	  1, 1 }, 
+        [DRM_IOCTL_NR(SIS_IOCTL_FLIP_INIT)]  = { sis_flip_init,	  1, 1 }, 
+        [DRM_IOCTL_NR(SIS_IOCTL_FLIP_FINAL)] = { sis_flip_final,  1, 1 }
+#endif
+
+#define __HAVE_COUNTERS		5
+
 /* Buffer customization:
  */
 #define DRIVER_AGP_BUFFERS_MAP( dev )					\
diff --git a/linux/sis_drv.c b/linux/sis_drv.c
index 2d9612f5..0c917bd4 100644
--- a/linux/sis_drv.c
+++ b/linux/sis_drv.c
@@ -31,31 +31,6 @@
 #include "sis_drm.h"
 #include "sis_drv.h"
 
-#define DRIVER_AUTHOR	 "SIS"
-#define DRIVER_NAME	 "sis"
-#define DRIVER_DESC	 "SIS 300/630/540"
-#define DRIVER_DATE	 "20010503"
-#define DRIVER_MAJOR	 1
-#define DRIVER_MINOR	 0
-#define DRIVER_PATCHLEVEL  0
-
-#define DRIVER_IOCTLS \
-        [DRM_IOCTL_NR(SIS_IOCTL_FB_ALLOC)]   = { sis_fb_alloc,	  1, 0 }, \
-        [DRM_IOCTL_NR(SIS_IOCTL_FB_FREE)]    = { sis_fb_free,	  1, 0 }, \
-        /* AGP Memory Management */					  \
-        [DRM_IOCTL_NR(SIS_IOCTL_AGP_INIT)]   = { sisp_agp_init,	  1, 0 }, \
-        [DRM_IOCTL_NR(SIS_IOCTL_AGP_ALLOC)]  = { sisp_agp_alloc,  1, 0 }, \
-        [DRM_IOCTL_NR(SIS_IOCTL_AGP_FREE)]   = { sisp_agp_free,	  1, 0 }
-#if 0 /* these don't appear to be defined */
-	/* SIS Stereo */						 
-	[DRM_IOCTL_NR(DRM_IOCTL_CONTROL)]    = { sis_control,	  1, 1 }, 
-        [DRM_IOCTL_NR(SIS_IOCTL_FLIP)]       = { sis_flip,	  1, 1 }, 
-        [DRM_IOCTL_NR(SIS_IOCTL_FLIP_INIT)]  = { sis_flip_init,	  1, 1 }, 
-        [DRM_IOCTL_NR(SIS_IOCTL_FLIP_FINAL)] = { sis_flip_final,  1, 1 }
-#endif
-
-#define __HAVE_COUNTERS		5
-
 #include "drm_auth.h"
 #include "drm_agpsupport.h"
 #include "drm_bufs.h"
diff --git a/linux/tdfx_drv.c b/linux/tdfx_drv.c
index 91499077..8b790188 100644
--- a/linux/tdfx_drv.c
+++ b/linux/tdfx_drv.c
@@ -82,25 +82,6 @@ static drm_pci_list_t DRM(idlist)[] = {
 #include "drm_drawable.h"
 #include "drm_drv.h"
 
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init tdfx_options( char *str )
-{
-	DRM(parse_options)( str );
-	return 1;
-}
-
-__setup( DRIVER_NAME "=", tdfx_options );
-#endif
-
 #include "drm_fops.h"
 #include "drm_init.h"
 #include "drm_ioctl.h"
author	Keith Whitwell <keith@tungstengraphics.com>	2002-07-15 20:21:18 +0000
committer	Keith Whitwell <keith@tungstengraphics.com>	2002-07-15 20:21:18 +0000
commit	eef49a73b541d69be5da9b289deff36f5bb96ab0 (patch)
tree	0cc0fa5559d7bf87c25d277ef63d816d0090ccf4 /linux
parent	deb296f395bb16ef7cf4bfe48f6e6c2cbacea0bc (diff)