Remove floating point calculations from kernel module for depth buffer

    clear. We should get rid of this at some stage, as it is considerably
    slower than color buffer clears.

4 files changed, 190 insertions, 192 deletions

diff --git a/linux/radeon_cp.c b/linux/radeon_cp.c
index 8d4c6167..1af1aade 100644
--- a/linux/radeon_cp.c
+++ b/linux/radeon_cp.c
@@ -466,9 +466,13 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 
 	dev_priv->cp_running = 1;
 
-	RADEON_WAIT_UNTIL_IDLE();
+	BEGIN_RING( 6 );
+
 	RADEON_FLUSH_CACHE();
 	RADEON_FLUSH_ZCACHE();
+	RADEON_WAIT_UNTIL_IDLE();
+
+	ADVANCE_RING();
 }
 
 /* Reset the Concurrent Command Engine.  This will not flush any pending
diff --git a/linux/radeon_drm.h b/linux/radeon_drm.h
index 3eba2c8b..a1698d51 100644
--- a/linux/radeon_drm.h
+++ b/linux/radeon_drm.h
@@ -270,11 +270,21 @@ typedef struct drm_radeon_fullscreen {
 	} func;
 } drm_radeon_fullscreen_t;
 
+#define CLEAR_X1	0
+#define CLEAR_Y1	1
+#define CLEAR_X2	2
+#define CLEAR_Y2	3
+#define CLEAR_DEPTH	4
+
 typedef struct drm_radeon_clear {
 	unsigned int flags;
 	int x, y, w, h;
 	unsigned int clear_color;
 	unsigned int clear_depth;
+	union {
+		float f[5];
+		unsigned int ui[5];
+	} rect;
 } drm_radeon_clear_t;
 
 typedef struct drm_radeon_vertex {
diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index d3647fd0..d97aa4b8 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -221,20 +221,23 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_CRTC_TILE_EN		(1 << 15)
 #	define RADEON_CRTC_OFFSET_FLIP_CNTL	(1 << 16)
 
+#define RADEON_RB3D_DEPTHCLEARVALUE	0x1c30
+#define RADEON_RB3D_DEPTHXY_OFFSET	0x1c60
+
 #define RADEON_DP_GUI_MASTER_CNTL	0x146c
-#       define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1    <<  0)
-#       define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1    <<  1)
-#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13   <<  4)
-#	define RADEON_GMC_BRUSH_NONE		(15   <<  4)
-#	define RADEON_GMC_DST_16BPP		(4    <<  8)
-#	define RADEON_GMC_DST_24BPP		(5    <<  8)
-#	define RADEON_GMC_DST_32BPP		(6    <<  8)
-#       define RADEON_GMC_DST_DATATYPE_SHIFT	8
-#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3    << 12)
-#	define RADEON_DP_SRC_SOURCE_MEMORY	(2    << 24)
-#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3    << 24)
-#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1    << 28)
-#	define RADEON_GMC_WR_MSK_DIS		(1    << 30)
+#	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)
+#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
+#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)
+#	define RADEON_GMC_BRUSH_NONE		(15 << 4)
+#	define RADEON_GMC_DST_16BPP		(4 << 8)
+#	define RADEON_GMC_DST_24BPP		(5 << 8)
+#	define RADEON_GMC_DST_32BPP		(6 << 8)
+#	define RADEON_GMC_DST_DATATYPE_SHIFT	8
+#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3 << 12)
+#	define RADEON_DP_SRC_SOURCE_MEMORY	(2 << 24)
+#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3 << 24)
+#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1 << 28)
+#	define RADEON_GMC_WR_MSK_DIS		(1 << 30)
 #	define RADEON_ROP3_S			0x00cc0000
 #	define RADEON_ROP3_P			0x00f00000
 #define RADEON_DP_WRITE_MASK		0x16cc
@@ -288,8 +291,18 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_RB2D_DC_FLUSH_ALL		0xf
 #	define RADEON_RB2D_DC_BUSY		(1 << 31)
 #define RADEON_RB3D_CNTL		0x1c3c
+#	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
 #	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
+#	define RADEON_DITHER_ENABLE		(1 << 2)
+#	define RADEON_ROUND_ENABLE		(1 << 3)
+#	define RADEON_SCALE_DITHER_ENABLE	(1 << 4)
+#	define RADEON_DITHER_INIT		(1 << 5)
+#	define RADEON_ROP_ENABLE		(1 << 6)
+#	define RADEON_STENCIL_ENABLE		(1 << 7)
 #	define RADEON_Z_ENABLE			(1 << 8)
+#	define RADEON_DEPTH_XZ_OFFEST_ENABLE	(1 << 9)
+#	define RADEON_ZBLOCK8			(0 << 15)
+#	define RADEON_ZBLOCK16			(1 << 15)
 #define RADEON_RB3D_DEPTHOFFSET		0x1c24
 #define RADEON_RB3D_PLANEMASK		0x1d84
 #define RADEON_RB3D_STENCILREFMASK	0x1d7c
@@ -299,8 +312,12 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_RB3D_ZC_FREE		(1 << 2)
 #	define RADEON_RB3D_ZC_BUSY		(1 << 31)
 #define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
-#	define RADEON_Z_TEST_MASK		(7 <<  4)
-#	define RADEON_Z_TEST_ALWAYS		(7 <<  4)
+#	define RADEON_Z_TEST_MASK		(7 << 4)
+#	define RADEON_Z_TEST_ALWAYS		(7 << 4)
+#	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)
+#	define RADEON_STENCIL_S_FAIL_KEEP	(0 << 16)
+#	define RADEON_STENCIL_ZPASS_KEEP	(0 << 20)
+#	define RADEON_STENCIL_ZFAIL_KEEP	(0 << 20)
 #	define RADEON_Z_WRITE_ENABLE		(1 << 30)
 #define RADEON_RBBM_SOFT_RESET		0x00f0
 #	define RADEON_SOFT_RESET_CP		(1 <<  0)
@@ -325,12 +342,19 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_SCISSOR_BR_2		0x1cec
 #define RADEON_SE_COORD_FMT		0x1c50
 #define RADEON_SE_CNTL			0x1c4c
-#	define RADEON_BFACE_SOLID		(3 <<  1)
-#	define RADEON_BFACE_CULL_MASK		(3 <<  1)
-#	define RADEON_FFACE_SOLID		(3 <<  3)
-#	define RADEON_FFACE_CULL_MASK		(3 <<  3)
+#	define RADEON_FFACE_CULL_CW		(0 << 0)
+#	define RADEON_BFACE_SOLID		(3 << 1)
+#	define RADEON_FFACE_SOLID		(3 << 3)
+#	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)
+#	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)
+#	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)
+#	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)
+#	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)
 #	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)
 #	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)
+#	define RADEON_VTX_PIX_CENTER_OGL	(1 << 27)
+#	define RADEON_ROUND_MODE_TRUNC		(0 << 28)
+#	define RADEON_ROUND_PREC_8TH_PIX	(1 << 30)
 #define RADEON_SE_CNTL_STATUS		0x2140
 #define RADEON_SE_LINE_WIDTH		0x1db8
 #define RADEON_SE_VPORT_XSCALE		0x1d98
@@ -384,6 +408,11 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_WAIT_3D_IDLECLEAN		(1 << 17)
 #	define RADEON_WAIT_HOST_IDLECLEAN	(1 << 18)
 
+#define RADEON_RB3D_ZMASKOFFSET		0x1c34
+#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
+#	define RADEON_DEPTH_FORMAT_16BIT_INT_Z	(0 << 0)
+#	define RADEON_DEPTH_FORMAT_24BIT_INT_Z	(2 << 0)
+
 
 /* CP registers */
 #define RADEON_CP_ME_RAM_ADDR		0x07d4
@@ -405,12 +434,12 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 
 #define RADEON_CP_CSQ_CNTL		0x0740
 #	define RADEON_CSQ_CNT_PRIMARY_MASK	(0xff << 0)
-#	define RADEON_CSQ_PRIDIS_INDDIS		(0    << 28)
-#	define RADEON_CSQ_PRIPIO_INDDIS		(1    << 28)
-#	define RADEON_CSQ_PRIBM_INDDIS		(2    << 28)
-#	define RADEON_CSQ_PRIPIO_INDBM		(3    << 28)
-#	define RADEON_CSQ_PRIBM_INDBM		(4    << 28)
-#	define RADEON_CSQ_PRIPIO_INDPIO		(15   << 28)
+#	define RADEON_CSQ_PRIDIS_INDDIS		(0 << 28)
+#	define RADEON_CSQ_PRIPIO_INDDIS		(1 << 28)
+#	define RADEON_CSQ_PRIBM_INDDIS		(2 << 28)
+#	define RADEON_CSQ_PRIPIO_INDBM		(3 << 28)
+#	define RADEON_CSQ_PRIBM_INDBM		(4 << 28)
+#	define RADEON_CSQ_PRIPIO_INDPIO		(15 << 28)
 
 #define RADEON_AIC_CNTL			0x01d0
 #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
@@ -423,6 +452,7 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #	define RADEON_3D_RNDR_GEN_INDX_PRIM	0x00002300
 #	define RADEON_WAIT_FOR_IDLE		0x00002600
 #	define RADEON_3D_DRAW_IMMD		0x00002900
+#	define RADEON_3D_CLEAR_ZMASK		0x00003200
 #	define RADEON_CNTL_HOSTDATA_BLT		0x00009400
 #	define RADEON_CNTL_PAINT_MULTI		0x00009A00
 #	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
@@ -433,29 +463,28 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_CP_PACKET1_REG0_MASK	0x000007ff
 #define RADEON_CP_PACKET1_REG1_MASK	0x003ff800
 
-#define RADEON_CP_VC_FRMT_XY				0x00000000
-#define RADEON_CP_VC_FRMT_Z				0x80000000
-
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE		0x00000000
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT		0x00000001
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE		0x00000002
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP		0x00000003
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST		0x00000004
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN		0x00000005
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP		0x00000006
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2		0x00000007
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST		0x00000008
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST	0x00000009
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST	0x0000000a
-#define RADEON_CP_VC_CNTL_PRIM_WALK_IND			0x00000010
-#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST		0x00000020
-#define RADEON_CP_VC_CNTL_PRIM_WALK_RING		0x00000030
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA		0x00000000
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA		0x00000040
-#define RADEON_CP_VC_CNTL_MAOS_ENABLE			0x00000080
-#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE	0x00000000
-#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE		0x00000100
-#define RADEON_CP_VC_CNTL_NUM_SHIFT			16
+#define RADEON_VTX_Z_PRESENT			(1 << 31)
+
+#define RADEON_PRIM_TYPE_NONE			(0 << 0)
+#define RADEON_PRIM_TYPE_POINT			(1 << 0)
+#define RADEON_PRIM_TYPE_LINE			(2 << 0)
+#define RADEON_PRIM_TYPE_LINE_STRIP		(3 << 0)
+#define RADEON_PRIM_TYPE_TRI_LIST		(4 << 0)
+#define RADEON_PRIM_TYPE_TRI_FAN		(5 << 0)
+#define RADEON_PRIM_TYPE_TRI_STRIP		(6 << 0)
+#define RADEON_PRIM_TYPE_TRI_TYPE2		(7 << 0)
+#define RADEON_PRIM_TYPE_RECT_LIST		(8 << 0)
+#define RADEON_PRIM_TYPE_3VRT_POINT_LIST	(9 << 0)
+#define RADEON_PRIM_TYPE_3VRT_LINE_LIST		(10 << 0)
+#define RADEON_PRIM_WALK_IND			(1 << 4)
+#define RADEON_PRIM_WALK_LIST			(2 << 4)
+#define RADEON_PRIM_WALK_RING			(3 << 4)
+#define RADEON_COLOR_ORDER_BGRA			(0 << 6)
+#define RADEON_COLOR_ORDER_RGBA			(1 << 6)
+#define RADEON_MAOS_ENABLE			(1 << 7)
+#define RADEON_VTX_FMT_R128_MODE		(0 << 8)
+#define RADEON_VTX_FMT_RADEON_MODE		(1 << 8)
+#define RADEON_NUM_VERTICES_SHIFT		16
 
 #define RADEON_COLOR_FORMAT_CI8		2
 #define RADEON_COLOR_FORMAT_ARGB1555	3
@@ -511,7 +540,7 @@ extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
 #define CP_PACKET0( reg, n )						\
 	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET1( reg0, reg1 )					\
-	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
+	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
 #define CP_PACKET2()							\
 	(RADEON_CP_PACKET2)
 #define CP_PACKET3( pkt, n )						\
@@ -524,62 +553,48 @@ extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
 
 #define RADEON_WAIT_UNTIL_2D_IDLE()					\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_WAIT_UNTIL_3D_IDLE()					\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_WAIT_UNTIL_IDLE()					\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
 		   RADEON_WAIT_3D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED()				\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( RADEON_WAIT_CRTC_PFLIP );				\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_FLUSH_CACHE()						\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB2D_DC_FLUSH );				\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_PURGE_CACHE()						\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );				\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE()						\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
-	ADVANCE_RING();							\
 } while (0)
 
 
@@ -600,26 +615,20 @@ do {									\
 
 #define RADEON_DISPATCH_AGE( age )					\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );		\
 	OUT_RING( age );						\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_FRAME_AGE( age )						\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );		\
 	OUT_RING( age );						\
-	ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_CLEAR_AGE( age )						\
 do {									\
-	BEGIN_RING( 2 );						\
 	OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );		\
 	OUT_RING( age );						\
-	ADVANCE_RING();							\
 } while (0)
 
 
diff --git a/linux/radeon_state.c b/linux/radeon_state.c
index 88ee2dd0..01918de7 100644
--- a/linux/radeon_state.c
+++ b/linux/radeon_state.c
@@ -227,21 +227,12 @@ static inline void radeon_emit_setup( drm_radeon_private_t *dev_priv )
 	 * with triangles.  In the future, we probably won't need this
 	 * optimization.
 	 */
-#if 0
-	/* Why doesn't CP_PACKET1 work? */
-	BEGIN_RING( 3 );
-
-	OUT_RING( CP_PACKET1( RADEON_SE_CNTL, RADEON_SE_CNTL_STATUS ) );
-	OUT_RING( ctx->se_cntl );
-	OUT_RING( ctx->se_cntl_status );
-#else
 	BEGIN_RING( 4 );
 
 	OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 	OUT_RING( ctx->se_cntl );
 	OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
 	OUT_RING( ctx->se_cntl_status );
-#endif
 
 	ADVANCE_RING();
 }
@@ -541,15 +532,13 @@ static void radeon_print_dirty( const char *msg, unsigned int flags )
 }
 
 static void radeon_cp_dispatch_clear( drm_device_t *dev,
-				      unsigned int flags,
-				      int cx, int cy, int cw, int ch,
-				      unsigned int clear_color,
-				      unsigned int clear_depth )
+				      drm_radeon_clear_t *clear )
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	int nbox = sarea_priv->nbox;
 	drm_clip_rect_t *pbox = sarea_priv->boxes;
+	unsigned int flags = clear->flags;
 	u32 fb_bpp, depth_bpp;
 	int i;
 	RING_LOCALS;
@@ -585,8 +574,6 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 		if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
 	}
 
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
 	for ( i = 0 ; i < nbox ; i++ ) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
@@ -598,7 +585,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 			   pbox[i].y2, flags );
 
 		if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
-			BEGIN_RING( 2 );
+			BEGIN_RING( 4 );
+
+			/* Ensure the 3D stream is idle before doing a
+			 * 2D fill to clear the front or back buffer.
+			 */
+			RADEON_WAIT_UNTIL_3D_IDLE();
 
 			OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 			OUT_RING( sarea_priv->context_state.rb3d_planemask );
@@ -618,7 +610,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 				  RADEON_GMC_CLR_CMP_CNTL_DIS );
 
 			OUT_RING( dev_priv->front_pitch_offset );
-			OUT_RING( clear_color );
+			OUT_RING( clear->clear_color );
 
 			OUT_RING( (x << 16) | y );
 			OUT_RING( (w << 16) | h );
@@ -638,7 +630,7 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 				  RADEON_GMC_CLR_CMP_CNTL_DIS );
 
 			OUT_RING( dev_priv->back_pitch_offset );
-			OUT_RING( clear_color );
+			OUT_RING( clear->clear_color );
 
 			OUT_RING( (x << 16) | y );
 			OUT_RING( (w << 16) | h );
@@ -647,117 +639,61 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 		}
 
 		if ( flags & RADEON_DEPTH ) {
-#if 0
-			BEGIN_RING( 6 );
-
-			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-				  RADEON_GMC_BRUSH_SOLID_COLOR |
-				  depth_bpp |
-				  RADEON_GMC_SRC_DATATYPE_COLOR |
-				  RADEON_ROP3_P |
-				  RADEON_GMC_CLR_CMP_CNTL_DIS |
-				  RADEON_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset );
-			OUT_RING( clear_depth );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-#else
-			int dx = x;
-			int dy = y;
 			drm_radeon_context_regs_t *ctx =
-				&sarea_priv->context_state;
+			   &sarea_priv->context_state;
 			u32 rb3d_cntl = ctx->rb3d_cntl;
 			u32 rb3d_zstencilcntl = ctx->rb3d_zstencilcntl;
 			u32 se_cntl = ctx->se_cntl;
 
-			rb3d_cntl |= ( RADEON_PLANE_MASK_ENABLE |
-				       RADEON_Z_ENABLE );
+			/* FIXME: Do re really need to do this?  Why
+			 * not just precalculate all the values?
+			 */
+			rb3d_cntl |= (RADEON_PLANE_MASK_ENABLE |
+				      RADEON_Z_ENABLE);
 
-			rb3d_zstencilcntl &= ~RADEON_Z_TEST_MASK;
-			rb3d_zstencilcntl |= ( RADEON_Z_TEST_ALWAYS |
-					       RADEON_Z_WRITE_ENABLE );
+			rb3d_zstencilcntl |= (RADEON_Z_TEST_ALWAYS |
+					      RADEON_Z_WRITE_ENABLE);
 
-			se_cntl &= ~( RADEON_VPORT_XY_XFORM_ENABLE |
-				      RADEON_VPORT_Z_XFORM_ENABLE |
-				      RADEON_FFACE_CULL_MASK |
-				      RADEON_BFACE_CULL_MASK );
-			se_cntl |= ( RADEON_FFACE_SOLID |
-				     RADEON_BFACE_SOLID );
+			se_cntl &= ~(RADEON_VPORT_XY_XFORM_ENABLE |
+				     RADEON_VPORT_Z_XFORM_ENABLE);
+			se_cntl |= (RADEON_FFACE_SOLID |
+				    RADEON_BFACE_SOLID);
 
-			BEGIN_RING( 28 );
+			/* FIXME: Render a rectangle to clear the depth
+			 * buffer.  So much for those "fast Z clears"...
+			 */
+			BEGIN_RING( 20 );
 
 			OUT_RING( CP_PACKET0( RADEON_RB3D_CNTL, 0 ) );
 			OUT_RING( rb3d_cntl );
-
 			OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
 			OUT_RING( rb3d_zstencilcntl );
-
 			OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
 			OUT_RING( 0x00000000 );
-
 			OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 			OUT_RING( se_cntl );
 
-			/* Draw rectangle */
 			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
-			OUT_RING( RADEON_CP_VC_FRMT_XY |
-				  RADEON_CP_VC_FRMT_Z );
-			OUT_RING( RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
-				  RADEON_CP_VC_CNTL_MAOS_ENABLE |
-				  RADEON_CP_VC_CNTL_PRIM_WALK_RING |
-				  RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
-				  ( 3 << RADEON_CP_VC_CNTL_NUM_SHIFT ) );
-			{
-				union {
-					float f;
-					u32 u;
-				} val;
-
-
-
-	/*
-	 * *************************************************************
-	 *
-	 * FIXME: GET RID OF THIS!!!  WE MUST NOT USE THE FPU IN THE
-	 * KERNEL, EVER!!!
-	 *
-	 * *************************************************************
-	 */
-
-
+			OUT_RING( RADEON_VTX_Z_PRESENT );
+			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
+				   RADEON_PRIM_WALK_RING |
+				   RADEON_MAOS_ENABLE |
+				   RADEON_VTX_FMT_RADEON_MODE |
+				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
 
-				val.f = dx;          OUT_RING( val.u );
-				val.f = dy;          OUT_RING( val.u );
-				val.f = clear_depth; OUT_RING( val.u );
+			OUT_RING( clear->rect.ui[CLEAR_X1] );
+			OUT_RING( clear->rect.ui[CLEAR_Y1] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
 
-				val.f = dx;          OUT_RING( val.u );
-				val.f = dy + h;      OUT_RING( val.u );
-				val.f = clear_depth; OUT_RING( val.u );
+			OUT_RING( clear->rect.ui[CLEAR_X1] );
+			OUT_RING( clear->rect.ui[CLEAR_Y2] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
 
-				val.f = dx + w;      OUT_RING( val.u );
-				val.f = dy + h;      OUT_RING( val.u );
-				val.f = clear_depth; OUT_RING( val.u );
-			}
-
-			OUT_RING( CP_PACKET0( RADEON_RB3D_CNTL, 0 ) );
-			OUT_RING( ctx->rb3d_cntl );
-
-			OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
-			OUT_RING( ctx->rb3d_zstencilcntl );
-
-			OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
-			OUT_RING( ctx->rb3d_planemask );
-
-			OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
-			OUT_RING( ctx->se_cntl );
+			OUT_RING( clear->rect.ui[CLEAR_X2] );
+			OUT_RING( clear->rect.ui[CLEAR_Y2] );
+			OUT_RING( clear->rect.ui[CLEAR_DEPTH] );
 
 			ADVANCE_RING();
-#endif
 		}
 	}
 
@@ -767,8 +703,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
 	 */
 	dev_priv->sarea_priv->last_clear++;
 
+	BEGIN_RING( 4 );
+
 	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
 	RADEON_WAIT_UNTIL_2D_IDLE();
+
+	ADVANCE_RING();
 }
 
 static void radeon_cp_dispatch_swap( drm_device_t *dev )
@@ -803,8 +743,12 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 		break;
 	}
 
+	BEGIN_RING( 2 );
+
 	RADEON_WAIT_UNTIL_3D_IDLE();
 
+	ADVANCE_RING();
+
 	for ( i = 0 ; i < nbox ; i++ ) {
 		int x = pbox[i].x1;
 		int y = pbox[i].y1;
@@ -840,8 +784,12 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 
+	BEGIN_RING( 4 );
+
 	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
 	RADEON_WAIT_UNTIL_2D_IDLE();
+
+	ADVANCE_RING();
 }
 
 static void radeon_cp_dispatch_flip( drm_device_t *dev )
@@ -858,11 +806,11 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
 	radeon_cp_performance_boxes( dev_priv );
 #endif
 
+	BEGIN_RING( 6 );
+
 	RADEON_WAIT_UNTIL_3D_IDLE();
 	RADEON_WAIT_UNTIL_PAGE_FLIPPED();
 
-	BEGIN_RING( 2 );
-
 	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
 
 	if ( dev_priv->current_page == 0 ) {
@@ -881,7 +829,11 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
 	 */
 	dev_priv->sarea_priv->last_frame++;
 
+	BEGIN_RING( 2 );
+
 	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
+
+	ADVANCE_RING();
 }
 
 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
@@ -925,10 +877,10 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 			OUT_RING( offset );
 			OUT_RING( size );
 			OUT_RING( format );
-			OUT_RING( prim | RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
-				  RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
-				  RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
-				  (size << RADEON_CP_VC_CNTL_NUM_SHIFT) );
+			OUT_RING( prim | RADEON_PRIM_WALK_LIST |
+				  RADEON_COLOR_ORDER_RGBA |
+				  RADEON_VTX_FMT_RADEON_MODE |
+				  (size << RADEON_NUM_VERTICES_SHIFT) );
 
 			ADVANCE_RING();
 
@@ -940,7 +892,9 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
 		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
 
 		buf->pending = 1;
 		buf->used = 0;
@@ -999,7 +953,9 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the indirect buffer age */
+		BEGIN_RING( 2 );
 		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
 
 		buf->pending = 1;
 		buf->used = 0;
@@ -1049,10 +1005,10 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 		data[1] = offset;
 		data[2] = RADEON_MAX_VB_VERTS;
 		data[3] = format;
-		data[4] = (prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND |
-			   RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
-			   RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
-			   (count << RADEON_CP_VC_CNTL_NUM_SHIFT) );
+		data[4] = (prim | RADEON_PRIM_WALK_IND |
+			   RADEON_COLOR_ORDER_RGBA |
+			   RADEON_VTX_FMT_RADEON_MODE |
+			   (count << RADEON_NUM_VERTICES_SHIFT) );
 
 		if ( count & 0x1 ) {
 			data[dwords-1] &= 0x0000ffff;
@@ -1076,7 +1032,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 
 		/* Emit the vertex buffer age */
+		BEGIN_RING( 2 );
 		RADEON_DISPATCH_AGE( buf_priv->age );
+		ADVANCE_RING();
 
 		buf->pending = 1;
 		/* FIXME: Check dispatched field */
@@ -1137,8 +1095,12 @@ static int radeon_cp_dispatch_blit( drm_device_t *dev,
 	 * up with the texture data from the host data blit, otherwise
 	 * part of the texture image may be corrupted.
 	 */
-	RADEON_WAIT_UNTIL_3D_IDLE();
+	BEGIN_RING( 4 );
+
 	RADEON_FLUSH_CACHE();
+	RADEON_WAIT_UNTIL_3D_IDLE();
+
+	ADVANCE_RING();
 
 	/* Dispatch the indirect buffer.
 	 */
@@ -1187,8 +1149,12 @@ static int radeon_cp_dispatch_blit( drm_device_t *dev,
 	 * the texture data is written out to memory before rendering
 	 * continues.
 	 */
-	RADEON_WAIT_UNTIL_2D_IDLE();
+	BEGIN_RING( 4 );
+
 	RADEON_FLUSH_CACHE();
+	RADEON_WAIT_UNTIL_2D_IDLE();
+
+	ADVANCE_RING();
 
 	return 0;
 }
@@ -1221,9 +1187,7 @@ int radeon_cp_clear( struct inode *inode, struct file *filp,
 	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
-	radeon_cp_dispatch_clear( dev, clear.flags,
-				  clear.x, clear.y, clear.w, clear.h,
-				  clear.clear_color, clear.clear_depth );
+	radeon_cp_dispatch_clear( dev, &clear );
 
 	/* Make sure we restore the 3D state next time.
 	 */
@@ -1297,7 +1261,7 @@ int radeon_cp_vertex( struct inode *inode, struct file *filp,
 		return -EINVAL;
 	}
 	if ( vertex.prim < 0 ||
-	     vertex.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST ) {
+	     vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
 		DRM_ERROR( "buffer prim %d\n", vertex.prim );
 		return -EINVAL;
 	}
@@ -1362,7 +1326,7 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
 		return -EINVAL;
 	}
 	if ( elts.prim < 0 ||
-	     elts.prim > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST ) {
+	     elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
 		DRM_ERROR( "buffer prim %d\n", elts.prim );
 		return -EINVAL;
 	}
@@ -1512,8 +1476,19 @@ int radeon_cp_indirect( struct inode *inode, struct file *filp,
 	buf->used = indirect.end;
 	buf_priv->discard = indirect.discard;
 
+	/* Wait for the 3D stream to idle before the indirect buffer
+	 * containing 2D acceleration commands is processed.
+	 */
+	BEGIN_RING( 2 );
+
 	RADEON_WAIT_UNTIL_3D_IDLE();
 
+	ADVANCE_RING();
+
+	/* Dispatch the indirect buffer full of commands from the
+	 * X server.  This is insecure and is thus only available to
+	 * privileged clients.
+	 */
 	radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
 
 	return 0;