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path: root/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
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Diffstat (limited to 'xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c')
-rw-r--r--xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
index cdd6c4f15..1d777ce00 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c
@@ -730,6 +730,17 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
LOCK_HARDWARE( rmesa );
+ /* Need to do this for the perf box placement:
+ */
+ if (rmesa->dri.drawable->numClipRects)
+ {
+ XF86DRIClipRectPtr box = rmesa->dri.drawable->pClipRects;
+ XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ b[0] = box[0];
+ rmesa->sarea->nbox = 1;
+ }
+
+
/* Throttle the frame rate -- only allow one pending swap buffers
* request at a time.
*/
@@ -913,7 +924,8 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1;
depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2;
depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[RADEON_CLEAR_DEPTH] = ctx->Depth.Clear;
+ depth_boxes[n].f[RADEON_CLEAR_DEPTH] =
+ (float)rmesa->state.depth.clear;
}
ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,