diff options
| author | keithw <keithw> | 2002-08-26 22:16:00 +0000 |
|---|---|---|
| committer | keithw <keithw> | 2002-08-26 22:16:00 +0000 |
| commit | aab518de01935ef2757eb57067ea2cf999713ceb (patch) | |
| tree | 279b7b62a3b13b0e564c1bf7ce15d1243cb3da15 /xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c | |
| parent | 5e93eabda6a447e62c14d827ad370b84bcb89f52 (diff) | |
merged r200-0-1-branchr200-0-1-20020822-merge
Diffstat (limited to 'xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c')
| -rw-r--r-- | xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c index cdd6c4f15..1d777ce00 100644 --- a/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c +++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c @@ -730,6 +730,17 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv ) LOCK_HARDWARE( rmesa ); + /* Need to do this for the perf box placement: + */ + if (rmesa->dri.drawable->numClipRects) + { + XF86DRIClipRectPtr box = rmesa->dri.drawable->pClipRects; + XF86DRIClipRectPtr b = rmesa->sarea->boxes; + b[0] = box[0]; + rmesa->sarea->nbox = 1; + } + + /* Throttle the frame rate -- only allow one pending swap buffers * request at a time. */ @@ -913,7 +924,8 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all, depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1; depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2; depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2; - depth_boxes[n].f[RADEON_CLEAR_DEPTH] = ctx->Depth.Clear; + depth_boxes[n].f[RADEON_CLEAR_DEPTH] = + (float)rmesa->state.depth.clear; } ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR, |