- Added texture support (not yet working; also texblits not implemented yet)ati-5-0-0-20001223-freeze

- Added workaround for overwriting VB problem (does not completely solve the
  problem -- Q3A, gloss among others will still demonstrate the problem)
- Added window offsets support
- Fixed depth offset initialization
- Changed visuals to support 24bpp instead of 32bpp depth buffers to match
  Mesa's depth buffer support

12 files changed, 292 insertions, 239 deletions

diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h b/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
index 80536c88c..e429818a6 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_context.h
@@ -82,6 +82,10 @@ typedef struct radeon_context *radeonContextPtr;
 #define RADEON_FALLBACK_MULTIDRAW	0x0020
 #define RADEON_FALLBACK_LOGICOP		0x0040
 
+/* Subpixel offsets for window coordinates: */
+#define SUBPIXEL_X		(-0.125F)
+#define SUBPIXEL_Y		( 0.375F)
+
 typedef void (*radeon_interp_func)( GLfloat t,
 				    GLfloat *result,
 				    const GLfloat *in,
@@ -106,8 +110,7 @@ struct radeon_elt_tab {
 struct radeon_context {
    GLcontext		*glCtx;		/* Mesa context */
 
-   /* Driver and hardware state management
-    */
+   /* Driver and hardware state management */
    GLuint		new_state;
    GLuint		dirty;		/* Hardware state to be updated */
    radeon_context_regs_t setup;
@@ -121,8 +124,7 @@ struct radeon_context {
    CARD32		ClearDepth;	/* Value used to clear depth buffer */
    CARD32		ClearStencil;	/* Value used to clear stencil */
 
-   /* Map GL texture units onto hardware
-    */
+   /* Map GL texture units onto hardware */
    GLint		multitex;
    GLint		tmu_source[2];
    GLint		tex_dest[2];
@@ -130,8 +132,7 @@ struct radeon_context {
    GLuint		envcolor;
    GLint		lod_bias;
 
-   /* Texture object bookkeeping
-    */
+   /* Texture object bookkeeping */
    radeonTexObjPtr	CurrentTexObj[2];
    radeonTexObj		TexObjList[RADEON_NR_TEX_HEAPS];
    radeonTexObj		SwappedOut;
@@ -139,8 +140,7 @@ struct radeon_context {
    GLint		lastTexAge[RADEON_NR_TEX_HEAPS];
    GLint		lastTexHeap;
 
-   /* Current rendering state, fallbacks
-    */
+   /* Current rendering state, fallbacks */
    points_func		PointsFunc;
    line_func		LineFunc;
    triangle_func	TriangleFunc;
@@ -149,21 +149,18 @@ struct radeon_context {
    CARD32		IndirectTriangles;
    CARD32		Fallback;
 
-   /* Fast path
-    */
+   /* Fast path */
    GLuint		useFastPath;
    GLuint		SetupIndex;
    GLuint		SetupDone;
    GLuint		RenderIndex;
    radeon_interp_func	interp;
 
-   /* Vertex buffers
-    */
+   /* Vertex buffers */
    GLuint		num_verts;
    drmBufPtr		vert_buf;
 
-   /* Elt path
-    */
+   /* Elt path */
    drmBufPtr		elt_buf, retained_buf;
    GLushort		*first_elt, *next_elt;
    GLfloat		*next_vert;
@@ -172,21 +169,18 @@ struct radeon_context {
    struct radeon_elt_tab *elt_tab;
    GLfloat		device_matrix[16];
 
-   /* Texture blit buffers
-    */
+   /* Texture blit buffers */
    drmRadeonBlitRectPtr	BlitRects;
    drmBufPtr		*BlitBuffers;
    GLint		numBlitBuffers;
 
-   /* CP command packets
-    */
+   /* CP command packets */
    CARD32		*CPbuf;		/* buffer to submit to CP */
    GLuint		CPcount;	/* number of dwords in CPbuf */
    GLint		CPtimeout;	/* number of times to loop
 					   before exiting */
 
-   /* Visual, drawable, cliprect and scissor information
-    */
+   /* Visual, drawable, cliprect and scissor information */
    GLint		BufferSize;	/* Bits in color buffer */
    GLint		DepthSize;	/* Bits in depth buffer */
    GLint		StencilSize;	/* Bits in stencil buffer */
@@ -203,8 +197,7 @@ struct radeon_context {
    GLuint		scissor;
    XF86DRIClipRectRec	ScissorRect;	/* Current software scissor */
 
-   /* Mirrors of some DRI state
-    */
+   /* Mirrors of some DRI state */
    Display		*display;	/* X server display */
 
    __DRIcontextPrivate	*driContext;	/* DRI context */
@@ -218,8 +211,7 @@ struct radeon_context {
    radeonScreenPtr	radeonScreen;	/* Screen private DRI data */
    RADEONSAREAPriv	*sarea;		/* Private SAREA data */
 
-   /* Performance counters
-     */
+   /* Performance counters */
    GLuint		boxes;		/* Draw performance boxes */
    GLuint		hardwareWentIdle;
    GLuint		c_clears;
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
index 07928e8ca..b5cf56da3 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_state.c
@@ -502,15 +502,6 @@ static void radeonUpdateRenderAttrib( GLcontext *ctx )
     CARD32 p = radeon_ctx->setup.pp_cntl;
     CARD32 r = radeon_ctx->setup.rb3d_cntl;
 
-#if 0
-    /* This is stored in the PP_TEXFILTER_# register and should go in
-       radeon_tex.c */
-    CARD32 bias = radeon_ctx->lod_bias & 0xff;;
-
-    p &= ~RADEON_LOD_BIAS_MASK;
-    p |= (bias << RADEON_LOD_BIAS_SHIFT);
-#endif
-
     if ( ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR ) {
 	p |=  RADEON_SPECULAR_ENABLE;
     } else {
@@ -1153,7 +1144,8 @@ void radeonDDInitState( radeonContextPtr radeon_ctx )
     radeon_ctx->setup.rb3d_blendcntl    =
 	RADEON_SRC_BLEND_GL_ONE  |
 	RADEON_DST_BLEND_GL_ZERO;
-    radeon_ctx->setup.rb3d_depthoffset  = 0x00000000;
+    radeon_ctx->setup.rb3d_depthoffset  =
+	radeon_ctx->radeonScreen->depthOffset;
     radeon_ctx->setup.rb3d_depthpitch   =
 	(radeon_ctx->radeonScreen->depthPitch & RADEON_DEPTHPITCH_MASK) |
 	RADEON_DEPTH_ENDIAN_NO_SWAP;
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
index 055811073..302c0ffe3 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c
@@ -59,9 +59,10 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr radeon_ctx,
 {
    radeonTexObjPtr t;
    struct gl_texture_image *image;
-   int log2Pitch, log2Height, log2Size, log2MinSize;
+   int log2Width, log2Height, log2Size, log2MinSize;
    int totalSize;
    int i;
+   int txformat;
 
    image = tObj->Image[0];
    if ( !image )
@@ -81,51 +82,37 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr radeon_ctx,
    case GL_INTENSITY:
       if ( radeon_ctx->radeonScreen->bpp == 32 ) {
 	 t->texelBytes = 4;
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_ARGB8888;
-#endif
+	 txformat = RADEON_TXF_32BPP_ARGB8888;
       } else {
 	 t->texelBytes = 2;
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_ARGB4444;
-#endif
+	 txformat = RADEON_TXF_16BPP_ARGB4444;
       }
       break;
 
    case GL_RGB:
       if ( radeon_ctx->radeonScreen->bpp == 32 ) {
 	 t->texelBytes = 4;
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_ARGB8888;
-#endif
+	 txformat = RADEON_TXF_32BPP_ARGB8888;
       } else {
 	 t->texelBytes = 2;
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_RGB565;
-#endif
+	 txformat = RADEON_TXF_16BPP_RGB565;
       }
       break;
 
    case GL_LUMINANCE:
       if ( radeon_ctx->radeonScreen->bpp == 32 ) {
 	 t->texelBytes = 4;
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_ARGB8888;
-#endif
+	 txformat = RADEON_TXF_32BPP_ARGB8888;
       } else {
 	 t->texelBytes = 2;
 	 /* Use this to get true greys */
-#if 0
-	 t->textureFormat = RADEON_DATATYPE_ARGB1555;
-#endif
+	 txformat = RADEON_TXF_16BPP_ARGB1555;
       }
       break;
 
    case GL_COLOR_INDEX:
       t->texelBytes = 1;
-#if 0
-      t->textureFormat = RADEON_DATATYPE_CI8;
-#endif
+      txformat = RADEON_TXF_8BPP_I;
       break;
 
    default:
@@ -138,11 +125,11 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr radeon_ctx,
    for ( i = 1, log2Height = 0 ; i < image->Height ; i *= 2 ) {
       log2Height++;
    }
-   for ( i = 1, log2Pitch = 0 ;  i < image->Width ;  i *= 2 ) {
-      log2Pitch++;
+   for ( i = 1, log2Width = 0 ;  i < image->Width ;  i *= 2 ) {
+      log2Width++;
    }
    if ( image->Width > image->Height ) {
-      log2Size = log2Pitch;
+      log2Size = log2Width;
    } else {
       log2Size = log2Height;
    }
@@ -168,7 +155,6 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr radeon_ctx,
    log2MinSize = log2Size - i + 1;
 
    t->totalSize = totalSize;
-   t->internFormat = image->IntFormat;
 
    t->bound = 0;
    t->heap = 0;
@@ -177,31 +163,35 @@ static radeonTexObjPtr radeonCreateTexObj( radeonContextPtr radeon_ctx,
    t->memBlock = NULL;
    t->bufAddr = NULL;
 
-   /* Hardware state:
-    */
-#if 0
-   t->setup.tex_cntl = (RADEON_MIN_BLEND_NEAREST |
-			RADEON_MAG_BLEND_NEAREST |
-			RADEON_TEX_CLAMP_S_WRAP |
-			RADEON_TEX_CLAMP_T_WRAP |
-			t->textureFormat);
-
-   t->setup.tex_combine_cntl = 0x00000000;
-
-   t->setup.tex_size_pitch = ((log2Pitch   << RADEON_TEX_PITCH_SHIFT) |
-			      (log2Size    << RADEON_TEX_SIZE_SHIFT) |
-			      (log2Height  << RADEON_TEX_HEIGHT_SHIFT) |
-			      (log2MinSize << RADEON_TEX_MIN_SIZE_SHIFT));
-
-   for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-      t->setup.tex_offset[i]  = 0x00000000;
-   }
-   t->setup.tex_border_color = 0x00000000;
-
-   if ( ( log2MinSize == log2Size ) || ( log2MinSize != 0 ) ) {
-      t->setup.tex_cntl |= RADEON_MIP_MAP_DISABLE;
-   }
-#endif
+   /* Hardware state: */
+   t->setup.pp_txfilter =
+       RADEON_MAG_FILTER_NEAREST |
+       RADEON_MIN_FILTER_NEAREST |
+       (radeon_ctx->lod_bias << RADEON_LOD_BIAS_SHIFT) |
+       (log2Size << RADEON_MAX_MIP_LEVEL_SHIFT) |
+       RADEON_CLAMP_S_WRAP |
+       RADEON_CLAMP_T_WRAP |
+       RADEON_BORDER_MODE_OGL;
+
+   t->setup.pp_txformat =
+       txformat |
+       ((txformat == RADEON_TXF_16BPP_RGB565) ? 0 : RADEON_TXF_ALPHA_IN_MAP) |
+       (log2Width << RADEON_TXF_WIDTH_SHIFT) |
+       (log2Height << RADEON_TXF_HEIGHT_SHIFT) |
+       RADEON_TXF_ST_ROUTE_STQ0 |
+       RADEON_TXF_ENDIAN_NO_SWAP |
+       RADEON_TXF_PERSPECTIVE_ENABLE;
+
+   t->setup.pp_txoffset =
+       RADEON_TXO_ENDIAN_NO_SWAP |
+       RADEON_TXO_MACRO_LINEAR |
+       RADEON_TXO_MICRO_LINEAR |
+       (0x00000000 & RADEON_TXO_OFFSET_MASK);
+
+   t->setup.pp_txcblend = 0x00000000;
+   t->setup.pp_txablend = 0x00000000;
+   t->setup.pp_tfactor = 0x00000000;
+   t->setup.pp_border_color = 0x00000000;
 
    radeonSetTexWrap( t, tObj->WrapS, tObj->WrapT );
    radeonSetTexFilter( t, tObj->MinFilter, tObj->MagFilter );
@@ -684,7 +674,8 @@ static void radeonUploadSubImage( radeonContextPtr radeon_ctx,
    imageWidth  = image->Width;
    imageHeight = image->Height;
 
-   format = t->textureFormat >> 16;
+   format = (t->setup.pp_txformat
+	     & RADEON_TXF_FORMAT_MASK) >> RADEON_TXF_FORMAT_SHIFT;
 
    /* The texel upload routines have a minimum width, so force the size
     * if needed.
@@ -768,7 +759,7 @@ static void radeonUploadSubImage( radeonContextPtr radeon_ctx,
 	       width, height, image->Width, image->Height, x, y );
       fprintf( stderr, "          blit ofs: 0x%07x pitch: 0x%x dwords: %d "
 	       "level: %d format: %x\n",
-	       (int)offset, pitch, dwords, level, format );
+	       (int)offset, (unsigned int)pitch, dwords, level, format );
    }
 
    /* Subdivide the texture if required */
@@ -831,8 +822,6 @@ static void radeonUploadSubImage( radeonContextPtr radeon_ctx,
 int radeonUploadTexImages( radeonContextPtr radeon_ctx, radeonTexObjPtr t )
 {
    int i;
-   int minLevel;
-   int maxLevel;
    int heap;
 
    if ( RADEON_DEBUG & DEBUG_VERBOSE_API ) {
@@ -844,10 +833,12 @@ int radeonUploadTexImages( radeonContextPtr radeon_ctx, radeonTexObjPtr t )
 
    /* Choose the heap appropriately */
    heap = t->heap = RADEON_LOCAL_TEX_HEAP;
+#if 0
    if ( !radeon_ctx->radeonScreen->IsPCI &&
 	t->totalSize > radeon_ctx->radeonScreen->texSize[heap] ) {
       heap = t->heap = RADEON_AGP_TEX_HEAP;
    }
+#endif
 
    /* Do we need to eject LRU texture objects? */
    if ( !t->memBlock ) {
@@ -900,29 +891,12 @@ int radeonUploadTexImages( radeonContextPtr radeon_ctx, radeonTexObjPtr t )
       t->bufAddr = (unsigned char *)radeon_ctx->radeonScreen->texOffset[heap];
       t->bufAddr += t->memBlock->ofs;
 
+      t->setup.pp_txoffset = (CARD32)t->bufAddr;
 #if 0
-      maxLevel = ((t->setup.tex_size_pitch & RADEON_TEX_SIZE_MASK) >>
-		  RADEON_TEX_SIZE_SHIFT);
-      minLevel = ((t->setup.tex_size_pitch & RADEON_TEX_MIN_SIZE_MASK) >>
-		  RADEON_TEX_MIN_SIZE_SHIFT);
-
-      /* Set texture offsets */
-      if ( t->setup.tex_cntl & RADEON_MIP_MAP_DISABLE ) {
-	 for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-	    t->setup.tex_offset[i] = (CARD32)t->bufAddr;
-	 }
-      } else {
-	 for ( i = maxLevel ; i >= minLevel ; i-- ) {
-	    t->setup.tex_offset[i] =
-	       t->image[maxLevel-i].offset + (CARD32)t->bufAddr;
-	 }
-      }
       /* Fix AGP texture offsets */
       if ( heap == RADEON_AGP_TEX_HEAP ) {
-	 for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-	    t->setup.tex_offset[i] += RADEON_AGP_TEX_OFFSET +
-	       radeon_ctx->radeonScreen->agpTexOffset;
-	 }
+	  t->setup.pp_tx_offset += RADEON_AGP_TEX_OFFSET +
+	      radeon_ctx->radeonScreen->agpTexOffset;
       }
 #endif
 
@@ -946,11 +920,8 @@ int radeonUploadTexImages( radeonContextPtr radeon_ctx, radeonTexObjPtr t )
 
    /* Upload any images that are new */
    if ( t->dirty_images ) {
-#if 0
-      int num_levels = (((t->setup.tex_size_pitch & RADEON_TEX_SIZE_MASK) >>
-			 RADEON_TEX_SIZE_SHIFT) -
-			((t->setup.tex_size_pitch & RADEON_TEX_MIN_SIZE_MASK) >>
-			 RADEON_TEX_MIN_SIZE_SHIFT));
+      int num_levels = ((t->setup.pp_txfilter & RADEON_MAX_MIP_LEVEL_MASK) >>
+			RADEON_MAX_MIP_LEVEL_SHIFT);
 
       for ( i = 0 ; i <= num_levels ; i++ ) {
 	 if ( t->dirty_images & (1 << i) ) {
@@ -959,9 +930,6 @@ int radeonUploadTexImages( radeonContextPtr radeon_ctx, radeonTexObjPtr t )
 	 }
       }
 
-      radeon_ctx->setup.tex_cntl_c |= RADEON_TEX_CACHE_FLUSH;
-#endif
-
       radeon_ctx->dirty |= RADEON_UPLOAD_CONTEXT;
    }
 
@@ -1023,7 +991,7 @@ static void radeonUpdateTextureStage( GLcontext *ctx, int unit )
    struct gl_texture_object *tObj;
    radeonTexObjPtr t;
    GLuint enabled;
-   CARD32 combine;
+   CARD32 color_combine, alpha_combine;
 
    if ( RADEON_DEBUG & DEBUG_VERBOSE_API ) {
       fprintf( stderr, "%s( %p, %d )\n",
@@ -1048,6 +1016,16 @@ static void radeonUpdateTextureStage( GLcontext *ctx, int unit )
    /* We definately have a valid texture now */
    t = tObj->DriverData;
 
+#if 1
+   /* FIXME: forced to replace */
+   if ( unit == 0 ) {
+      color_combine = 0x00802800;
+      alpha_combine = 0x00800500;
+   } else {
+      color_combine = 0x00803000;
+      alpha_combine = 0x00800600;
+   }
+#else
    if ( unit == 0 ) {
       combine = INPUT_INTERP;
    } else {
@@ -1208,10 +1186,10 @@ static void radeonUpdateTextureStage( GLcontext *ctx, int unit )
    default:
       return;
    }
-
-#if 0
-   t->setup.tex_combine_cntl = combine;
 #endif
+
+   t->setup.pp_txcblend = color_combine;
+   t->setup.pp_txablend = alpha_combine;
 }
 
 static void radeonUpdateTextureObject( GLcontext *ctx, int unit )
@@ -1228,10 +1206,10 @@ static void radeonUpdateTextureObject( GLcontext *ctx, int unit )
    }
 
    /* Disable all texturing until it is known to be good */
-#if 0
-   radeon_ctx->setup.tex_cntl_c &= ~(RADEON_TEXMAP_ENABLE |
-				  RADEON_SEC_TEXMAP_ENABLE);
-#endif
+   radeon_ctx->setup.pp_cntl &= ~(RADEON_TEX_0_ENABLE |
+				  RADEON_TEX_1_ENABLE |
+				  RADEON_TEX_2_ENABLE |
+				  RADEON_TEX_3_ENABLE);
 
    enabled = (ctx->Texture.ReallyEnabled >> (source * 4)) & TEXTURE0_ANY;
    if ( enabled != TEXTURE0_2D && enabled != TEXTURE0_1D ) {
@@ -1283,22 +1261,9 @@ static void radeonUpdateTextureObject( GLcontext *ctx, int unit )
    if ( t->memBlock )
       radeonUpdateTexLRU( radeon_ctx, t );
 
-#if 0
-   if ( unit == 0 ) {
-      radeon_ctx->setup.tex_cntl_c       |= RADEON_TEXMAP_ENABLE;
-      radeon_ctx->setup.tex_size_pitch_c |= t->setup.tex_size_pitch << 0;
-      radeon_ctx->setup.scale_3d_cntl    &= ~RADEON_TEX_CACHE_SPLIT;
-
-      t->setup.tex_cntl &= ~RADEON_SEC_SELECT_SEC_ST;
-   } else {
-      t->setup.tex_cntl |=  RADEON_SEC_SELECT_SEC_ST;
-
-      radeon_ctx->setup.tex_cntl_c       |= (RADEON_TEXMAP_ENABLE |
-					  RADEON_SEC_TEXMAP_ENABLE) ;
-      radeon_ctx->setup.tex_size_pitch_c |= t->setup.tex_size_pitch << 16;
-      radeon_ctx->setup.scale_3d_cntl    |= RADEON_TEX_CACHE_SPLIT;
-   }
-#endif
+   radeon_ctx->setup.pp_cntl |= RADEON_TEX_0_ENABLE;
+   if ( unit == 1 )
+      radeon_ctx->setup.pp_cntl |= RADEON_TEX_1_ENABLE;
 }
 
 /* Update the hardware texture state */
@@ -1323,10 +1288,6 @@ void radeonUpdateTextureState( GLcontext *ctx )
    if ( ctx->Enabled & (TEXTURE0_3D|TEXTURE1_3D) )
       radeon_ctx->Fallback |= RADEON_FALLBACK_TEXTURE;
 
-#if 0
-   radeon_ctx->setup.tex_size_pitch_c = 0x00000000;
-#endif
-
    radeonUpdateTextureObject( ctx, 0 );
    radeonUpdateTextureStage( ctx, 0 );
 
@@ -1340,73 +1301,67 @@ void radeonUpdateTextureState( GLcontext *ctx )
 /* Set the texture wrap mode */
 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
 {
-#if 0
-   t->setup.tex_cntl &= ~(RADEON_TEX_CLAMP_S_MASK | RADEON_TEX_CLAMP_T_MASK);
+   t->setup.pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK);
 
    switch ( swrap ) {
    case GL_CLAMP:
-      t->setup.tex_cntl |= RADEON_TEX_CLAMP_S_CLAMP;
+      t->setup.pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
       break;
    case GL_REPEAT:
-      t->setup.tex_cntl |= RADEON_TEX_CLAMP_S_WRAP;
+      t->setup.pp_txfilter |= RADEON_CLAMP_S_WRAP;
       break;
    }
 
    switch ( twrap ) {
    case GL_CLAMP:
-      t->setup.tex_cntl |= RADEON_TEX_CLAMP_T_CLAMP;
+      t->setup.pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
       break;
    case GL_REPEAT:
-      t->setup.tex_cntl |= RADEON_TEX_CLAMP_T_WRAP;
+      t->setup.pp_txfilter |= RADEON_CLAMP_T_WRAP;
       break;
    }
-#endif
 }
 
 /* Set the texture filter mode */
 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
 {
-#if 0
-   t->setup.tex_cntl &= ~(RADEON_MIN_BLEND_MASK | RADEON_MAG_BLEND_MASK);
+   t->setup.pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
 
    switch ( minf ) {
    case GL_NEAREST:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_NEAREST;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
       break;
    case GL_LINEAR:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_LINEAR;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
       break;
    case GL_NEAREST_MIPMAP_NEAREST:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_MIPNEAREST;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
       break;
    case GL_LINEAR_MIPMAP_NEAREST:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_LINEARMIPNEAREST;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
       break;
    case GL_NEAREST_MIPMAP_LINEAR:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_MIPLINEAR;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
       break;
    case GL_LINEAR_MIPMAP_LINEAR:
-      t->setup.tex_cntl |= RADEON_MIN_BLEND_LINEARMIPLINEAR;
+      t->setup.pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
       break;
    }
 
    switch ( magf ) {
    case GL_NEAREST:
-      t->setup.tex_cntl |= RADEON_MAG_BLEND_NEAREST;
+      t->setup.pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
       break;
    case GL_LINEAR:
-      t->setup.tex_cntl |= RADEON_MAG_BLEND_LINEAR;
+      t->setup.pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
       break;
    }
-#endif
 }
 
 /* Set the texture border color */
 static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
 {
-#if 0
-   t->setup.tex_border_color = radeonPackColor( 32, c[0], c[1], c[2], c[3] );
-#endif
+   t->setup.pp_border_color = radeonPackColor( 32, c[0], c[1], c[2], c[3] );
 }
 
 
@@ -1424,6 +1379,7 @@ static void radeonDDTexEnv( GLcontext *ctx, GLenum target,
 			  GLenum pname, const GLfloat *param )
 {
    radeonContextPtr radeon_ctx = RADEON_CONTEXT( ctx );
+   radeonTexObjPtr t;
    struct gl_texture_unit *texUnit;
    GLubyte c[4];
    CARD32 col;
@@ -1445,14 +1401,13 @@ static void radeonDDTexEnv( GLcontext *ctx, GLenum target,
       texUnit = &ctx->Texture.Unit[ctx->Texture.CurrentUnit];
       FLOAT_RGBA_TO_UBYTE_RGBA( texUnit->EnvColor, c );
       col = radeonPackColor( 32, c[0], c[1], c[2], c[3] );
-#if 0
-      if ( radeon_ctx->setup.constant_color_c != col ) {
+      t = radeon_ctx->CurrentTexObj[ctx->Texture.CurrentUnit];
+      if ( t->setup.pp_tfactor != col ) {
 	 FLUSH_BATCH( radeon_ctx );
-	 radeon_ctx->setup.constant_color_c = col;
+	 t->setup.pp_tfactor = col;
 
 	 radeon_ctx->new_state |= RADEON_NEW_TEXTURE;
       }
-#endif
       break;
 
    case GL_TEXTURE_LOD_BIAS_EXT:
@@ -1475,6 +1430,7 @@ static void radeonDDTexEnv( GLcontext *ctx, GLenum target,
       }
       if ( radeon_ctx->lod_bias != bias ) {
 	 FLUSH_BATCH( radeon_ctx );
+	 /* FIXME: Add support for setting the LOD bias to pp_txfilter */
 	 radeon_ctx->lod_bias = bias;
 
 	 radeon_ctx->new_state |= RADEON_NEW_RENDER;
@@ -1544,10 +1500,6 @@ static void radeonDDTexSubImage( GLcontext *ctx, GLenum target,
       UNLOCK_HARDWARE( radeon_ctx );
 
       /* Update the context state */
-#if 0
-      radeon_ctx->setup.tex_cntl_c |= RADEON_TEX_CACHE_FLUSH;
-#endif
-
       radeon_ctx->new_state |= RADEON_NEW_TEXTURE;
    }
 }
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_texobj.h b/xc/lib/GL/mesa/src/drv/radeon/radeon_texobj.h
index 200c86848..b7565bec2 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_texobj.h
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_texobj.h
@@ -71,9 +71,6 @@ struct radeon_tex_obj {
 
    GLint		totalSize;	/* Total size of the texture
 					   including all mipmap levels */
-   GLuint		internFormat;	/* Internal GL format used to store
-					   texture on card */
-   CARD32		textureFormat;	/* Actual hardware format */
    GLint		texelBytes;	/* Number of bytes per texel */
 
    radeon_texture_regs_t setup;		/* Setup regs for texture */
diff --git a/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c b/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
index bf7446e87..96997d886 100644
--- a/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
+++ b/xc/lib/GL/mesa/src/drv/radeon/radeon_vb.c
@@ -110,10 +110,10 @@ do {									\
 #define COORD								\
 do {									\
    GLfloat *win = VB->Win.data[i];					\
-   v->v.x =               win[0];					\
-   v->v.y =  radeon_height - win[1];					\
-   v->v.z =       scale * win[2];					\
-   v->v.rhw = v->v.rhw2 = win[3];					\
+   v->v.x =                   win[0] + x_offset;			\
+   v->v.y =   radeon_height - win[1] + y_offset;			\
+   v->v.z =           scale * win[2];					\
+   v->v.rhw =     v->v.rhw2 = win[3];					\
 } while (0)
 
 #else /* USE_RHW2 */
@@ -123,10 +123,10 @@ do {									\
 #define COORD								\
 do {									\
     GLfloat *win = VB->Win.data[i];					\
-    v->v.x =                win[0];					\
-    v->v.y =   radeon_height - win[1];					\
-    v->v.z =        scale * win[2];					\
-    v->v.rhw =              win[3];					\
+    v->v.x =                   win[0] + x_offset;			\
+    v->v.y =   radeon_height - win[1] + y_offset;			\
+    v->v.z =           scale * win[2];					\
+    v->v.rhw =                 win[3];					\
 } while (0)								\
 
 #endif /* USE_RHW2 */
@@ -137,16 +137,19 @@ do {									\
 #define SETUPFUNC(name,win,col,tex0,tex1,tex0_4,tex1_4,spec,fog)	\
 static void name(struct vertex_buffer *VB, GLuint start, GLuint end)	\
 {									\
-   radeonContextPtr        radeon_ctx    = RADEON_CONTEXT(VB->ctx);		\
+   radeonContextPtr      radeon_ctx = RADEON_CONTEXT(VB->ctx);		\
    __DRIdrawablePrivate *dPriv      = radeon_ctx->driDrawable;		\
-   radeonVertexPtr         v;						\
+   radeonVertexPtr       v;						\
    GLfloat               (*tc0)[4];					\
    GLfloat               (*tc1)[4];					\
    GLfloat               radeon_height = dPriv->h;			\
    GLfloat               scale = radeon_ctx->depth_scale;		\
+   GLfloat               x_offset = dPriv->x + SUBPIXEL_X;		\
+   GLfloat               y_offset = dPriv->y + SUBPIXEL_Y;		\
    int                   i;						\
 									\
    (void) radeon_height; (void) radeon_ctx; (void) scale;		\
+   (void) x_offset; (void) y_offset;					\
 									\
    gl_import_client_data(VB, VB->ctx->RenderFlags,			\
 			 (VB->ClipOrMask				\
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c
index ee501790c..16f67273b 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c
+++ b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c
@@ -217,7 +217,7 @@ static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
 		    pConfigs[i].depthSize      = 24;
 		    pConfigs[i].stencilSize    = 8;
 		} else {
-		    pConfigs[i].depthSize      = 32;
+		    pConfigs[i].depthSize      = 24;
 		    pConfigs[i].stencilSize    = 0;
 		}
 		pConfigs[i].auxBuffers         = 0;
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
index 0dae54ff4..4bff2dd8b 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
+++ b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
@@ -933,6 +933,9 @@
 #define RADEON_XPLL_CNTL                    0x000b /* PLL */
 
 				/* Registers for 3D/TCL */
+#define RADEON_PP_BORDER_COLOR_0            0x1d40
+#define RADEON_PP_BORDER_COLOR_1            0x1d44
+#define RADEON_PP_BORDER_COLOR_2            0x1d48
 #define RADEON_PP_CNTL                      0x1c38
 #       define RADEON_STIPPLE_ENABLE        (1 <<  0)
 #       define RADEON_SCISSOR_ENABLE        (1 <<  1)
@@ -995,6 +998,94 @@
 #       define RADEON_RIGHT_HAND_CUBE_OGL   (1 << 24)
 #define RADEON_PP_ROT_MATRIX_0              0x1d58
 #define RADEON_PP_ROT_MATRIX_1              0x1d5c
+#define RADEON_PP_TXFILTER_0                0x1c54
+#define RADEON_PP_TXFILTER_1                0x1c6c
+#define RADEON_PP_TXFILTER_2                0x1c84
+#       define RADEON_MAG_FILTER_NEAREST                   (0  <<  0)
+#       define RADEON_MAG_FILTER_LINEAR                    (1  <<  0)
+#       define RADEON_MAG_FILTER_MASK                      (1  <<  0)
+#       define RADEON_MIN_FILTER_NEAREST                   (0  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR                    (1  <<  1)
+#       define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST       (2  <<  1)
+#       define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR        (3  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST        (6  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR         (7  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST             (8  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_LINEAR              (9  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR  (11 <<  1)
+#       define RADEON_MIN_FILTER_MASK                      (15 <<  1)
+#       define RADEON_LOD_BIAS_MASK                        (0xffff <<  8)
+#       define RADEON_LOD_BIAS_SHIFT                       8
+#       define RADEON_MAX_MIP_LEVEL_MASK                   (0x0f << 16)
+#       define RADEON_MAX_MIP_LEVEL_SHIFT                  16
+#       define RADEON_WRAPEN_S                             (1  << 22)
+#       define RADEON_CLAMP_S_WRAP                         (0  << 23)
+#       define RADEON_CLAMP_S_MIRROR                       (1  << 23)
+#       define RADEON_CLAMP_S_CLAMP_LAST                   (2  << 23)
+#       define RADEON_CLAMP_S_MIRROR_CLAMP_LAST            (3  << 23)
+#       define RADEON_CLAMP_S_CLAMP_BORDER                 (4  << 23)
+#       define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER          (5  << 23)
+#       define RADEON_CLAMP_S_MASK                         (7  << 23)
+#       define RADEON_WRAPEN_T                             (1  << 26)
+#       define RADEON_CLAMP_T_WRAP                         (0  << 27)
+#       define RADEON_CLAMP_T_MIRROR                       (1  << 27)
+#       define RADEON_CLAMP_T_CLAMP_LAST                   (2  << 27)
+#       define RADEON_CLAMP_T_MIRROR_CLAMP_LAST            (3  << 27)
+#       define RADEON_CLAMP_T_CLAMP_BORDER                 (4  << 27)
+#       define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER          (5  << 27)
+#       define RADEON_CLAMP_T_MASK                         (7  << 27)
+#       define RADEON_BORDER_MODE_OGL                      (0  << 31)
+#       define RADEON_BORDER_MODE_D3D                      (1  << 31)
+#define RADEON_PP_TXFORMAT_0                0x1c58
+#define RADEON_PP_TXFORMAT_1                0x1c70
+#define RADEON_PP_TXFORMAT_2                0x1c88
+#       define RADEON_TXF_8BPP_I             (0  <<  0)
+#       define RADEON_TXF_16BPP_AI           (1  <<  0)
+#       define RADEON_TXF_8BPP_RGB332        (2  <<  0)
+#       define RADEON_TXF_16BPP_ARGB1555     (3  <<  0)
+#       define RADEON_TXF_16BPP_RGB565       (4  <<  0)
+#       define RADEON_TXF_16BPP_ARGB4444     (5  <<  0)
+#       define RADEON_TXF_32BPP_ARGB8888     (6  <<  0)
+#       define RADEON_TXF_32BPP_RGBA8888     (7  <<  0)
+#       define RADEON_TXF_8BPP_Y             (8  <<  0)
+#       define RADEON_TXF_FORMAT_MASK        (31 <<  0)
+#       define RADEON_TXF_FORMAT_SHIFT       0
+#       define RADEON_TXF_APPLE_YUV_MODE     (1  <<  5)
+#       define RADEON_TXF_ALPHA_IN_MAP       (1  <<  6)
+#       define RADEON_TXF_NON_POWER2         (1  <<  7)
+#       define RADEON_TXF_WIDTH_MASK         (15 <<  8)
+#       define RADEON_TXF_WIDTH_SHIFT        8
+#       define RADEON_TXF_HEIGHT_MASK        (15 << 12)
+#       define RADEON_TXF_HEIGHT_SHIFT       12
+#       define RADEON_TXF_ST_ROUTE_STQ0      (0  << 24)
+#       define RADEON_TXF_ST_ROUTE_STQ1      (1  << 24)
+#       define RADEON_TXF_ST_ROUTE_STQ2      (2  << 24)
+#       define RADEON_TXF_ENDIAN_NO_SWAP     (0  << 26)
+#       define RADEON_TXF_ENDIAN_16BPP_SWAP  (1  << 26)
+#       define RADEON_TXF_ENDIAN_32BPP_SWAP  (2  << 26)
+#       define RADEON_TXF_ENDIAN_HALFDW_SWAP (3  << 26)
+#       define RADEON_TXF_ALPHA_MASK_ENABLE  (1  << 28)
+#       define RADEON_TXF_CHROMA_KEY_ENABLE  (1  << 29)
+#       define RADEON_TXF_CUBIC_MAP_ENABLE   (1  << 30)
+#       define RADEON_TXF_PERSPECTIVE_ENABLE (1  << 31)
+#define RADEON_PP_TXOFFSET_0                0x1c5c
+#define RADEON_PP_TXOFFSET_1                0x1c74
+#define RADEON_PP_TXOFFSET_2                0x1c8c
+#       define RADEON_TXO_ENDIAN_NO_SWAP     (0 << 0)
+#       define RADEON_TXO_ENDIAN_BYTE_SWAP   (1 << 0)
+#       define RADEON_TXO_ENDIAN_WORD_SWAP   (2 << 0)
+#       define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
+#       define RADEON_TXO_MACRO_LINEAR       (0 << 2)
+#       define RADEON_TXO_MACRO_TILE         (1 << 2)
+#       define RADEON_TXO_MICRO_LINEAR       (0 << 3)
+#       define RADEON_TXO_MICRO_TILE_X2      (1 << 3)
+#       define RADEON_TXO_MICRO_TILE_OPT     (2 << 3)
+#       define RADEON_TXO_OFFSET_MASK        0xffffffe0
+#       define RADEON_TXO_OFFSET_SHIFT       5
+#define RADEON_PP_TFACTOR_0                 0x1c68
+#define RADEON_PP_TFACTOR_1                 0x1c80
+#define RADEON_PP_TFACTOR_2                 0x1c98
 
 #define RADEON_RB3D_BLENDCNTL               0x1c20
 #       define RADEON_COMB_FCN_ADD_CLAMP               (0  << 12)
diff --git a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h
index 8ca507355..8cfa3d33d 100644
--- a/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h
+++ b/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h
@@ -188,11 +188,12 @@ typedef struct {
     unsigned int pp_txablend;
     unsigned int pp_tfactor;
 
-    unsigned int pp_cubic_faces;
-
     unsigned int pp_border_color;
 
+#ifdef CUBIC_ENABLE
+    unsigned int pp_cubic_faces;
     unsigned int pp_cubic_offset[5];
+#endif
 } radeon_texture_regs_t;
 
 typedef struct {
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
index 3c31f65d3..087996c15 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_cp.c
@@ -709,6 +709,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 	radeon_cp_init_ring_buffer( dev );
 	radeon_do_engine_reset( dev );
 
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
+
 	return 0;
 }
 
@@ -952,6 +956,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 	drm_radeon_buf_priv_t *buf_priv;
 	drm_buf_t *buf;
 	int i, t;
+#if ROTATE_BUFS
+	int start;
+#endif
 
 	/* FIXME: Optimize -- use freelist code */
 
@@ -962,10 +969,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 			return buf;
 	}
 
+#if ROTATE_BUFS
+	if (++dev_priv->last_buf >= dma->buf_count)
+		dev_priv->last_buf = 0;
+	start = dev_priv->last_buf;
+#endif
 	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
 		u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
-
+#if ROTATE_BUFS
+		for ( i = start ; i < dma->buf_count ; i++ ) {
+#else
 		for ( i = 0 ; i < dma->buf_count ; i++ ) {
+#endif
 			buf = dma->buflist[i];
 			buf_priv = buf->dev_private;
 			if ( buf->pending && buf_priv->age <= done_age ) {
@@ -975,6 +990,9 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 				buf->pending = 0;
 				return buf;
 			}
+#if ROTATE_BUFS
+			start = 0;
+#endif
 		}
 		udelay( 1 );
 	}
@@ -986,8 +1004,14 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
 void radeon_freelist_reset( drm_device_t *dev )
 {
 	drm_device_dma_t *dma = dev->dma;
+#if ROTATE_BUFS
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+#endif
 	int i;
 
+#if ROTATE_BUFS
+	dev_priv->last_buf = 0;
+#endif
 	for ( i = 0 ; i < dma->buf_count ; i++ ) {
 		drm_buf_t *buf = dma->buflist[i];
 		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drm.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drm.h
index b758660f1..3f890661b 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drm.h
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drm.h
@@ -187,11 +187,12 @@ typedef struct {
 	unsigned int pp_txablend;
 	unsigned int pp_tfactor;
 
-	unsigned int pp_cubic_faces;
-
 	unsigned int pp_border_color;
 
+#ifdef CUBIC_ENABLE
+	unsigned int pp_cubic_faces;
 	unsigned int pp_cubic_offset[5];
+#endif
 } drm_radeon_texture_regs_t;
 
 typedef struct {
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
index 2e27398b3..016e24de6 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_drv.h
@@ -65,6 +65,14 @@ typedef struct drm_radeon_private {
 
    	drm_radeon_freelist_t *head;
    	drm_radeon_freelist_t *tail;
+/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
+   code is used.  Note this hides a problem with the scratch register
+   (used to keep track of last buffer completed) being written to before
+   the last buffer has actually completed rendering. */
+#define ROTATE_BUFS 1
+#if ROTATE_BUFS
+	int last_buf;
+#endif
 
 	int usec_timeout;
 	int is_pci;
@@ -220,10 +228,16 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_MC_FB_LOCATION		0x0148
 #define RADEON_MCLK_CNTL		0x0012
 
+#define RADEON_PP_BORDER_COLOR_0	0x1d40
+#define RADEON_PP_BORDER_COLOR_1	0x1d44
+#define RADEON_PP_BORDER_COLOR_2	0x1d48
 #define RADEON_PP_CNTL			0x1c38
 #define RADEON_PP_LUM_MATRIX		0x1d00
 #define RADEON_PP_MISC			0x1c14
 #define RADEON_PP_ROT_MATRIX_0		0x1d58
+#define RADEON_PP_TXFILTER_0		0x1c54
+#define RADEON_PP_TXFILTER_1		0x1c6c
+#define RADEON_PP_TXFILTER_2		0x1c84
 
 #define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
 #	define RADEON_RB2D_DC_FLUSH_ALL		0xf
diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
index 30949ee27..8253e9f29 100644
--- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
+++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/radeon_state.c
@@ -299,83 +299,71 @@ static inline void radeon_emit_misc( drm_radeon_private_t *dev_priv )
 
 static inline void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 7 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_PRIM_TEX_CNTL_C,
-			       2 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	OUT_RING( ctx->tex_size_pitch_c );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_CONSTANT_COLOR_C, 1 ) );
-	OUT_RING( ctx->constant_color_c );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
-			       1 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
 {
-#if 0
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 	drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
-	int i;
 	RING_LOCALS;
 	DRM_DEBUG( "    %s\n", __FUNCTION__ );
 
-	BEGIN_RING( 5 + RADEON_TEX_MAXLEVELS );
+	BEGIN_RING( 9 );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEX_CNTL_C,
-			       1 + RADEON_TEX_MAXLEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < RADEON_TEX_MAXLEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
+	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
+	OUT_RING( tex->pp_txfilter );
+	OUT_RING( tex->pp_txformat );
+	OUT_RING( tex->pp_txoffset );
+	OUT_RING( tex->pp_txcblend );
+	OUT_RING( tex->pp_txablend );
+	OUT_RING( tex->pp_tfactor );
 
-	OUT_RING( CP_PACKET0( RADEON_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
+	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
+	OUT_RING( tex->pp_border_color );
 
 	ADVANCE_RING();
-#endif
 }
 
 static inline void radeon_emit_state( drm_radeon_private_t *dev_priv )
@@ -1083,10 +1071,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-
-	int vertsize = sarea_priv->vertsize;
 	int format = sarea_priv->vc_format;
-	int index = buf->idx;
 	int offset = dev_priv->buffers->offset - dev->agp->base;
 	int prim = buf_priv->prim;
 
@@ -1477,7 +1462,8 @@ int radeon_cp_indices( struct inode *inode, struct file *filp,
 		return -EINVAL;
 	}
 	if ( (buf->offset + elts.start) & 0x3 ) {
-		DRM_ERROR( "buffer start 0x%x\n", buf->offset + elts.start );
+		DRM_ERROR( "buffer start 0x%x\n",
+			   (u32)(buf->offset + elts.start) );
 		return -EINVAL;
 	}