diff options
| author | kem <kem> | 2000-03-21 03:15:03 +0000 |
|---|---|---|
| committer | kem <kem> | 2000-03-21 03:15:03 +0000 |
| commit | 557403d05de964924b5b0e96679c2e969371a4b5 (patch) | |
| tree | 37f7fa6b99618c84c19ab2a7490c2a6856de5fc4 | |
| parent | 13f3c1ec07fedec0ff2e1e5912e8aa8fc854d189 (diff) | |
Updated r128 driver to XFree86 4.0
Included kernel code from mga branch plus modifications for r128
Fixed compilation problem with DDC support and static X server
91 files changed, 15083 insertions, 1891 deletions
diff --git a/xc/config/cf/host.def b/xc/config/cf/host.def new file mode 100644 index 000000000..cd4c54e03 --- /dev/null +++ b/xc/config/cf/host.def @@ -0,0 +1,19 @@ +#define ProjectRoot /usr/XF39-r128 +#define XF86CardDrivers vga r128 +#define GlxBuiltInR128 YES +#define NormalLibGlx NO +#define BuildServersOnly YES + +#define DoLoadableServer NO +#define SharedLibFont NO +#define DefaultGcc2i386Opt -O -pipe -g +#define XnestServer NO +#define XVirtualFramebufferServer NO +#define XprtServer NO + +/* #define BuildXF86DRI YES */ +/* #define DefaultCCOptions -Wall */ +/* #define DefaultGcc2i386Opt -O2 */ +/* #define LibraryCDebugFlags -O2 */ +/* #define LinuxDistribution LinuxRedHat */ +/* #define DefaultCCOptions -ansi GccWarningOptions -pipe */ diff --git a/xc/config/cf/xfree86.cf b/xc/config/cf/xfree86.cf index 77e5e454d..e90ba8e4c 100644 --- a/xc/config/cf/xfree86.cf +++ b/xc/config/cf/xfree86.cf @@ -512,12 +512,15 @@ IPLAN2P8_DEFS = -DUSE_IPLAN2P8 # ifndef GlxBuiltInTdfx # define GlxBuiltInTdfx NO # endif +# ifndef GlxBuiltInR128 +# define GlxBuiltInR128 NO +# endif -# if GlxBuiltInTdfx +# if GlxBuiltInTdfx || GlxBuiltInR128 # define GlxDriverUsesMesa YES # endif -# if GlxBuiltInGamma || GlxBuiltInMesa || GlxBuiltInTdfx +# if GlxBuiltInGamma || GlxBuiltInMesa || GlxBuiltInTdfx || GlxBuiltInR128 # define GlxUseBuiltInDRIDriver YES # define DRIDynLoadDefines /**/ # else diff --git a/xc/lib/GL/Imakefile b/xc/lib/GL/Imakefile index a185089e4..f6b31fde4 100644 --- a/xc/lib/GL/Imakefile +++ b/xc/lib/GL/Imakefile @@ -98,6 +98,36 @@ DRIMESADONES = mesa/dri/DONE DRVDONES = $(TDFXDONES) $(MESADONES) $(DRIMESADONES) $(DRMDONES) REQUIREDLIBS += -lglide3x +#elif GlxBuiltInR128 + DRMOBJS = dri/drm/?*.o + DRMUOBJS = dri/drm/unshared/?*.o + DRMDOBJS = dri/drm/debugger/?*.o + DRMPOBJS = dri/drm/profiled/?*.o + DRMDONES = dri/drm/DONE + + R128OBJS = mesa/src/drv/r128/?*.o + R128UOBJS = mesa/src/drv/r128/unshared/?*.o + R128DOBJS = mesa/src/drv/r128/debugger/?*.o + R128POBJS = mesa/src/drv/r128/profiled/?*.o + R128DONES = mesa/src/drv/r128/DONE + + MESAOBJS = mesa/src/?*.o mesa/src/X86/?*.o + MESAUOBJS = mesa/src/unshared/?*.o mesa/src/X86/unshared/?*.o + MESADOBJS = mesa/src/debugger/?*.o mesa/src/X86/debugger/?*.o + MESAPOBJS = mesa/src/profiled/?*.o mesa/src/X86/profiled/?*.o + MESADONES = mesa/src/DONE mesa/src/X86/DONE + + DRIMESAOBJS = mesa/dri/?*.o +DRIMESAUOBJS = mesa/dri/unshared/?*.o +DRIMESADOBJS = mesa/dri/debugger/?*.o +DRIMESAPOBJS = mesa/dri/profiled/?*.o +DRIMESADONES = mesa/dri/DONE + + DRVOBJS = $(R128OBJS) $(MESAOBJS) $(DRIMESAOBJS) $(DRMOBJS) + DRVUOBJS = $(R128UOBJS) $(MESAUOBJS) $(DRIMESAUOBJS) $(DRMUOBJS) + DRVDOBJS = $(R128DOBJS) $(MESADOBJS) $(DRIMESADOBJS) $(DRMDOBJS) + DRVPOBJS = $(R128POBJS) $(MESAPOBJS) $(DRIMESAPOBJS) $(DRMPOBJS) + DRVDONES = $(R128DONES) $(MESADONES) $(DRIMESADONES) $(DRMDONES) #elif GlxBuiltInMesa #ifndef GlxDriverUsesMesa DRVOBJS = mesa/src/?*.o mesa/src/X/?*.o diff --git a/xc/lib/GL/mesa/src/drv/Imakefile b/xc/lib/GL/mesa/src/drv/Imakefile index fadb29bb2..d1f68e7d4 100644 --- a/xc/lib/GL/mesa/src/drv/Imakefile +++ b/xc/lib/GL/mesa/src/drv/Imakefile @@ -16,6 +16,9 @@ DRIVER += gamma #if GlxBuiltInTdfx DRIVER += tdfx #endif +#if GlxBuiltInR128 +DRIVER += r128 +#endif SUBDIRS = $(DRIVER) #else @@ -23,6 +26,7 @@ SUBDIRS += gamma #if HasGlide3 SUBDIRS += tdfx #endif +SUBDIRS += r128 #endif MakeSubdirs($(SUBDIRS)) diff --git a/xc/lib/GL/mesa/src/drv/r128/Imakefile b/xc/lib/GL/mesa/src/drv/r128/Imakefile new file mode 100644 index 000000000..95d0f7d56 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/Imakefile @@ -0,0 +1,312 @@ +XCOMM $XFree86$ + +#include <Threads.tmpl> + +#define DoNormalLib NormalLibGlx +#define DoSharedLib SharedLibGlx +#define DoExtraLib SharedLibGlx +#define DoDebugLib DebugLibGlx +#define DoProfileLib ProfileLibGlx + +#if Malloc0ReturnsNull +ALLOC_DEFINES = -DMALLOC_0_RETURNS_NULL +#endif + +#if BuildXF86DRI + DRI_DEFINES = GlxDefines -DDRIVERTS + DRI_INCLUDES = -I../../../../dri \ + -I../../../../glx \ + -I../../../dri \ + -I$(TOP)/include \ + -I$(TOP)/include/GL \ + -I$(XF86OSSRC) \ + -I$(XF86COMSRC) \ + -I$(SERVERSRC)/GL/dri \ + -I$(XF86DRIVERSRC)/r128 \ + -I../../../include \ + -I../.. \ + -I../../X \ + -I../common +#endif + +LinkSourceFile(mm.c, ../common) +LinkSourceFile(mm.h, ../common) +LinkSourceFile(hwlog.c, ../common) +LinkSourceFile(hwlog.h, ../common) + +MESA_INCLUDES = -I. -I.. -I../../include + + DEFINES = $(ALLOC_DEFINES) $(DRI_DEFINES) + INCLUDES = -I$(XLIBSRC) -I$(EXTINCSRC) $(MESA_INCLUDES) $(DRI_INCLUDES) + + DRISRCS = ../../../dri/dri_mesa.c \ + ../../../../dri/dri_tmm.c + + DRIOBJS = ../../../dri/dri_mesa.o \ + ../../../../dri/dri_tmm.o + + DRMSRCS = ../../../../dri/drm/xf86drm.c \ + ../../../../dri/drm/xf86drmHash.c \ + ../../../../dri/drm/xf86drmRandom.c \ + ../../../../dri/drm/xf86drmSL.c + + DRMOBJS = ../../../../dri/drm/xf86drm.o \ + ../../../../dri/drm/xf86drmHash.o \ + ../../../../dri/drm/xf86drmRandom.o \ + ../../../../dri/drm/xf86drmSL.o + + R128SRCS = r128_cce.c \ + r128_clear.c \ + r128_context.c \ + r128_dd.c \ + r128_depth.c \ + r128_fastpath.c \ + r128_pipeline.c \ + r128_screen.c \ + r128_span.c \ + r128_state.c \ + r128_swap.c \ + r128_tex.c \ + r128_tris.c \ + r128_vb.c \ + r128_xmesa.c + + R128OBJS = r128_cce.o \ + r128_clear.o \ + r128_context.o \ + r128_dd.o \ + r128_depth.o \ + r128_fastpath.o \ + r128_pipeline.o \ + r128_screen.o \ + r128_span.o \ + r128_state.o \ + r128_swap.o \ + r128_tex.o \ + r128_tris.o \ + r128_vb.o \ + r128_xmesa.o + + MESASRCS = ../../accum.c \ + ../../alpha.c \ + ../../alphabuf.c \ + ../../attrib.c \ + ../../bbox.c \ + ../../bitmap.c \ + ../../blend.c \ + ../../buffers.c \ + ../../clip.c \ + ../../colortab.c \ + ../../config.c \ + ../../context.c \ + ../../copypix.c \ + ../../cva.c \ + ../../debug_xform.c \ + ../../depth.c \ + ../../dlist.c \ + ../../drawpix.c \ + ../../enable.c \ + ../../enums.c \ + ../../eval.c \ + ../../extensions.c \ + ../../feedback.c \ + ../../fog.c \ + ../../get.c \ + ../../glapi.c \ + ../../glapinoop.c \ + ../../glthread.c \ + ../../hash.c \ + ../../image.c \ + ../../imaging.o \ + ../../light.c \ + ../../lines.c \ + ../../logic.c \ + ../../masking.c \ + ../../matrix.c \ + ../../mem.c \ + ../../mmath.c \ + ../../pb.c \ + ../../pipeline.c \ + ../../pixel.c \ + ../../points.c \ + ../../polygon.c \ + ../../quads.c \ + ../../rastpos.c \ + ../../readpix.c \ + ../../rect.c \ + ../../scissor.c \ + ../../shade.c \ + ../../span.c \ + ../../stages.c \ + ../../state.c \ + ../../stencil.c \ + ../../teximage.c \ + ../../texobj.c \ + ../../texstate.c \ + ../../texture.c \ + ../../translate.c \ + ../../triangle.c \ + ../../varray.c \ + ../../vb.c \ + ../../vbcull.c \ + ../../vbfill.c \ + ../../vbindirect.c \ + ../../vbrender.c \ + ../../vbxform.c \ + ../../vector.c \ + ../../vertices.c \ + ../../winpos.c \ + ../../xform.c \ + ../../zoom.c \ + ../../X86/common_x86.c + + MESAOBJS = ../../accum.o \ + ../../alpha.o \ + ../../alphabuf.o \ + ../../attrib.o \ + ../../bbox.o \ + ../../bitmap.o \ + ../../blend.o \ + ../../buffers.o \ + ../../clip.o \ + ../../colortab.o \ + ../../config.o \ + ../../context.o \ + ../../copypix.o \ + ../../cva.o \ + ../../debug_xform.o \ + ../../depth.o \ + ../../dlist.o \ + ../../drawpix.o \ + ../../enable.o \ + ../../enums.o \ + ../../eval.o \ + ../../extensions.o \ + ../../feedback.o \ + ../../fog.o \ + ../../get.o \ + ../../hash.o \ + ../../hint.o \ + ../../image.o \ + ../../imaging.o \ + ../../light.o \ + ../../lines.o \ + ../../logic.o \ + ../../masking.o \ + ../../matrix.o \ + ../../mem.o \ + ../../mmath.o \ + ../../pb.o \ + ../../pipeline.o \ + ../../pixel.o \ + ../../points.o \ + ../../polygon.o \ + ../../quads.o \ + ../../rastpos.o \ + ../../readpix.o \ + ../../rect.o \ + ../../scissor.o \ + ../../shade.o \ + ../../span.o \ + ../../stages.o \ + ../../state.o \ + ../../stencil.o \ + ../../teximage.o \ + ../../texobj.o \ + ../../texstate.o \ + ../../texture.o \ + ../../translate.o \ + ../../triangle.o \ + ../../varray.o \ + ../../vb.o \ + ../../vbcull.o \ + ../../vbfill.o \ + ../../vbindirect.o \ + ../../vbrender.o \ + ../../vbxform.o \ + ../../vector.o \ + ../../vertices.o \ + ../../winpos.o \ + ../../xform.o \ + ../../zoom.o + +#ifdef i386Architecture + X86_SRCS = ../../X86/x86.c \ + ../../X86/x86a.S \ + ../../X86/common_x86.c \ + ../../X86/common_x86asm.S \ + ../../X86/vertex.S + + X86_OBJS = ../../X86/x86.o \ + ../../X86/x86a.o \ + ../../X86/common_x86.o \ + ../../X86/common_x86asm.o \ + ../../X86/vertex.o + + MMX_SRCS = ../../X86/mmx_blend.S + + MMX_OBJS = ../../X86/mmx_blend.o + +XCOMM Disabling 3Dnow code for the time being. +#if 0 + 3DNOW_SRCS = ../../X86/3dnow.c \ + ../../X86/3dnow_norm_raw.S \ + ../../X86/3dnow_xform_masked1.S \ + ../../X86/3dnow_xform_masked2.S \ + ../../X86/3dnow_xform_masked3.S \ + ../../X86/3dnow_xform_masked4.S \ + ../../X86/3dnow_xform_raw1.S \ + ../../X86/3dnow_xform_raw2.S \ + ../../X86/3dnow_xform_raw3.S \ + ../../X86/3dnow_xform_raw4.S \ + ../../X86/vertex_3dnow.S + + 3DNOW_OBJS = ../../X86/3dnow.o \ + ../../X86/3dnow_norm_raw.o \ + ../../X86/3dnow_xform_masked1.o \ + ../../X86/3dnow_xform_masked2.o \ + ../../X86/3dnow_xform_masked3.o \ + ../../X86/3dnow_xform_masked4.o \ + ../../X86/3dnow_xform_raw1.o \ + ../../X86/3dnow_xform_raw2.o \ + ../../X86/3dnow_xform_raw3.o \ + ../../X86/3dnow_xform_raw4.o \ + ../../X86/vertex_3dnow.o +#endif + +#endif + + ASMSRCS = $(X86_SRCS) $(MMX_SRCS) $(3DNOW_SRCS) + ASMOBJS = $(X86_OBJS) $(MMX_OBJS) $(3DNOW_OBJS) + + COMMONSRCS = mm.c hwlog.c + COMMONOBJS = mm.o hwlog.o + + SRCS = $(DRISRCS) $(DRMSRCS) $(MESASRCS) $(ASMSRCS) \ + $(COMMONSRCS) $(R128SRCS) + OBJS = $(DRIOBJS) $(DRMOBJS) $(MESAOBJS) $(ASMOBJS) \ + $(COMMONOBJS) $(R128OBJS) + +#if !GlxUseBuiltInDRIDriver +#undef DoNormalLib NormalLibGlx +#undef DoExtraLib SharedLibGlx +#undef DoDebugLib DebugLibGlx +#undef DoProfileLib ProfileLibGlx +#endif + +#include <Library.tmpl> + +LibraryObjectRule() + +SubdirLibraryRule($(OBJS)) +NormalLintTarget($(SRCS)) + +#if !GlxUseBuiltInDRIDriver +LIBNAME = r128_dri.so +ALL_OBJS = $(OBJS) +ALL_DEPS = DONE +SharedDepModuleTarget($(LIBNAME),$(ALL_DEPS),$(ALL_OBJS)) +InstallDynamicModule($(LIBNAME),$(MODULEDIR)/dri,.) +#endif + +DependTarget() diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_cce.c b/xc/lib/GL/mesa/src/drv/r128/r128_cce.c new file mode 100644 index 000000000..63742fe78 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_cce.c @@ -0,0 +1,191 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_state.h" +#include "r128_reg.h" +#include "r128_cce.h" + +/* FIXME: Requires access to secure registers */ +static int INPLL(r128ScreenPtr pScrn, int addr) +{ + unsigned char *R128MMIO = pScrn->mmio; + + OUTREG8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); + return INREG(R128_CLOCK_CNTL_DATA); +} + +/* FIXME: Requires access to secure registers */ +void R128EngineFlush(r128ScreenPtr pScrn) +{ + unsigned char *R128MMIO = pScrn->mmio; + int i; + + OUTREGP(R128_PC_NGUI_CTLSTAT, R128_PC_FLUSH_ALL, ~R128_PC_FLUSH_ALL); + for (i = 0; i < R128_TIMEOUT; i++) { + if (!(INREG(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) break; + } +} + +/* FIXME: Requires access to secure registers */ +void R128EngineReset(r128ScreenPtr pScrn) +{ + unsigned char *R128MMIO = pScrn->mmio; + CARD32 clock_cntl_index; + CARD32 mclk_cntl; + CARD32 gen_reset_cntl; + + R128EngineFlush(pScrn); + + clock_cntl_index = INREG(R128_CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(pScrn, R128_MCLK_CNTL); + + OUTPLL(R128_MCLK_CNTL, mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CPP); + + gen_reset_cntl = INREG(R128_GEN_RESET_CNTL); + + OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); + INREG(R128_GEN_RESET_CNTL); + OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); + INREG(R128_GEN_RESET_CNTL); + + OUTPLL(R128_MCLK_CNTL, mclk_cntl); + OUTREG(R128_CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl); +} + +/* The FIFO has 64 slots. This routines waits until at least `entries' + of these slots are empty. */ +void R128WaitForFifoFunction(r128ScreenPtr pScrn, int entries) +{ + unsigned char *R128MMIO = pScrn->mmio; + int i; + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + pScrn->MMIOFifoSlots = (INREG(R128_GUI_STAT) + & R128_GUI_FIFOCNT_MASK); + if (pScrn->MMIOFifoSlots >= entries) return; + } + R128_DEBUG(("Reseting Engine: GUI_STAT = 0x%08x\n", + (unsigned int)INREG(R128_GUI_STAT))); + R128EngineReset(pScrn); + } +} + +/* Wait for the graphics engine to be completely idle: the FIFO has + drained, the Pixel Cache is flushed, and the engine is idle. This is + a standard "sync" function that will make the hardware quiescent. */ +void R128WaitForIdle(r128ScreenPtr pScrn) +{ + unsigned char *R128MMIO = pScrn->mmio; + int i; + + R128WaitForFifoFunction(pScrn, 64); + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + if (!(INREG(R128_GUI_STAT) & R128_GUI_ACTIVE)) { + R128EngineFlush(pScrn); + return; + } + } + R128_DEBUG(("Reseting Engine: GUI_STAT = 0x%08x\n", + (unsigned int)INREG(R128_GUI_STAT))); + R128EngineReset(pScrn); + } +} + +/* Wait for at least `entries' slots are free. The actual number of + slots available is stored in info->CCEFifoSize. */ +void R128CCEWaitForFifoFunction(r128ScreenPtr pScrn, int entries) +{ + unsigned char *R128MMIO = pScrn->mmio; + int i; + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + pScrn->CCEFifoSlots = INREG(R128_PM4_STAT) & R128_PM4_FIFOCNT_MASK; + if (pScrn->CCEFifoSlots >= entries) return; + } + R128_DEBUG(("Reseting Engine: PM4_STAT = 0x%08x\n", + (unsigned int)INREG(R128_PM4_STAT))); + R128EngineReset(pScrn); + } +} + +/* Wait until the CCE is completely idle: the FIFO has drained and the + CCE is idle. */ +void R128CCEWaitForIdle(r128ScreenPtr pScrn) +{ + unsigned char *R128MMIO = pScrn->mmio; + int i; + + R128CCEWaitForFifoFunction(pScrn, pScrn->CCEFifoSize); + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + if (!(INREG(R128_PM4_STAT) + & (R128_PM4_BUSY | R128_PM4_GUI_ACTIVE))) { + R128EngineFlush(pScrn); + return; + } + } + R128_DEBUG(("Reseting Engine: PM4_STAT = 0x%08x\n", + (unsigned int)INREG(R128_PM4_STAT))); + R128EngineReset(pScrn); + } +} + +/* Flush the CPU's write-combining cache */ +void R128FlushWCMemory(void) +{ + int xchangeDummy; + + /* FIXME: This should be in standard XFree86 assembly format */ + __asm__ volatile("push %%eax ;" + "xchg %%eax, %0 ;" + "pop %%eax" : : "m" (xchangeDummy)); + __asm__ volatile("push %%eax ;" + "push %%ebx ;" + "push %%ecx ;" + "push %%edx ;" + "movl $0,%%eax ;" + "cpuid ;" + "pop %%edx ;" + "pop %%ecx ;" + "pop %%ebx ;" + "pop %%eax" : /* no outputs */ : /* no inputs */); +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_cce.h b/xc/lib/GL/mesa/src/drv/r128/r128_cce.h new file mode 100644 index 000000000..5da4fd348 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_cce.h @@ -0,0 +1,165 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_CCE_H_ +#define _R128_CCE_H_ + +#ifdef GLX_DIRECT_RENDERING + +#include "r128_dri.h" +#include "r128_reg.h" + +typedef union { + float f; + int i; +} floatTOint; + +#if (R128_CCE_MODE == R128_PM4_192PIO) || \ + (R128_CCE_MODE == R128_PM4_128PIO_64INDBM) || \ + (R128_CCE_MODE == R128_PM4_64PIO_128INDBM) || \ + (R128_CCE_MODE == R128_PM4_64PIO_64VCBM_64INDBM) || \ + (R128_CCE_MODE == R128_PM4_64PIO_64VCPIO_64INDPIO) + +/* The ring buffer is in PIO mode */ + +/* Start a sequence of CCE commands. This grabs the lock, and wait for + `n' entries to be free in the ring buffer. */ +#define R128CCE_BEGIN(n) \ + do { \ + LOCK_HARDWARE(r128ctx); \ + R128WaitForFifo(r128ctx->r128Screen, (n)); \ + } while (0) + +/* End a sequence of CCE commands. This also releases the lock. */ +#define R128CCE_END() \ + do { \ + if (r128ctx->r128Screen->CCEFifoAddr != R128_PM4_FIFO_DATA_EVEN) { \ + OUTREG(r128ctx->r128Screen->CCEFifoAddr, R128_CCE_PACKET2); \ + r128ctx->r128Screen->CCEFifoAddr ^= 0x0004; \ + } \ + UNLOCK_HARDWARE(r128ctx); \ + } while (0) + +/* Insert an integer value into the CCE ring buffer. */ +#define R128CCE(v) \ + do { \ + OUTREG(r128ctx->r128Screen->CCEFifoAddr, (v)); \ + r128ctx->r128Screen->CCEFifoAddr ^= 0x0004; \ + } while (0) + +/* Insert an floating point value into the CCE ring buffer. */ +#define R128CCEF(v) \ + do { \ + floatTOint fTi; \ + fTi.f = (v); \ + OUTREG(r128ctx->r128Screen->CCEFifoAddr, fTi.i); \ + r128ctx->r128Screen->CCEFifoAddr ^= 0x0004; \ + } while (0) + +/* Wait for `n' entries to be free in the ring buffer, while locked. */ +#define R128CCE_WAIT_LOCKED(n) \ + do { \ + R128WaitForFifo(r128ctx->r128Screen, (n)); \ + } while (0) + +/* End a sequence of CCE commands, but do not releases the lock. */ +#define R128CCE_END_LOCKED() \ + do { \ + if (r128ctx->r128Screen->CCEFifoAddr != R128_PM4_FIFO_DATA_EVEN) { \ + OUTREG(r128ctx->r128Screen->CCEFifoAddr, R128_CCE_PACKET2); \ + r128ctx->r128Screen->CCEFifoAddr ^= 0x0004; \ + } \ + } while (0) + +#else + +/* The ring buffer is in BM mode */ +/* FIXME: Implement support for the ring buffer */ + +/* Start a sequence of CCE commands. This grabs the lock, and wait for + `n' entries to be free in the ring buffer. */ +#define R128CCE_BEGIN(n) + +/* End a sequence of CCE commands. This also releases the lock. */ +#define R128CCE_END() + +/* Insert an integer value into the CCE ring buffer. */ +#define R128CCE(v) + +/* Insert an floating point value into the CCE ring buffer. */ +#define R128CCEF(v) + +/* Wait for `n' entries to be free in the ring buffer, while locked. */ +#define R128CCE_WAIT_LOCKED(n) + +/* End a sequence of CCE commands, but do not releases the lock. */ +#define R128CCE_END_LOCKED() + +#endif + +/* Insert a type-[0123] packet header into the ring buffer */ +#define R128CCE0(p,r,n) R128CCE((p) | ((n) << 16) | ((r) >> 2)) +#define R128CCE1(p,r1,r2) R128CCE((p) | (((r2) >> 2) << 11) | ((r1) >> 2)) +#define R128CCE2(p) R128CCE((p)) +#define R128CCE3(p,n) R128CCE((p) | ((n) << 16)) + +#define R128_TIMEOUT 2000000 + +#define R128WaitForFifo(pScrn, entries) \ +do { \ + if (pScrn->MMIOFifoSlots < entries) \ + R128WaitForFifoFunction(pScrn, entries); \ + pScrn->MMIOFifoSlots -= entries; \ +} while (0) + +#define R128CCEWaitForFifo(pScrn, entries) \ +do { \ + if (pScrn->CCEFifoSlots < entries) \ + R128CCEWaitForFifoFunction(pScrn, entries); \ + pScrn->CCEFifoSlots -= entries; \ +} while (0) + +extern void R128EngineFlush(r128ScreenPtr pScrn); +extern void R128EngineReset(r128ScreenPtr pScrn); + +extern void R128WaitForFifoFunction(r128ScreenPtr pScrn, int entries); +extern void R128WaitForIdle(r128ScreenPtr pScrn); + +extern void R128CCEWaitForFifoFunction(r128ScreenPtr pScrn, int entries); +extern void R128CCEWaitForIdle(r128ScreenPtr pScrn); + +extern void R128FlushWCMemory(void); + +#endif +#endif /* _R128_CCE_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_ccevb.h b/xc/lib/GL/mesa/src/drv/r128/r128_ccevb.h new file mode 100644 index 000000000..2a1d4e590 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_ccevb.h @@ -0,0 +1,48 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_CCEVB_H_ +#define _R128_CCEVB_H_ + +#ifdef GLX_DIRECT_RENDERING + +typedef struct { + int start; /* in bytes from the beginning of AGP memory */ + int count; /* in vertices */ + int size; /* in vertices */ + int done; /* VB has been sent to ring (FIXME) */ +} r128CCEVertBuf, *r128CCEVertBufPtr; + +#endif +#endif /* _R128_CCEVB_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_clear.c b/xc/lib/GL/mesa/src/drv/r128/r128_clear.c new file mode 100644 index 000000000..853cab870 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_clear.c @@ -0,0 +1,249 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_vb.h" +#include "r128_clear.h" + +/* Clear the depth buffer */ +void r128ClearDepthBuffer(r128ContextPtr r128ctx, GLboolean all, + GLint cx, GLint cy, GLint cw, GLint ch) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; + int nc = dPriv->numClipRects; + XF86DRIClipRectPtr c = dPriv->pClipRects; + int dst_bpp; + CARD32 write_mask; + + if (!(r128ctx->regs.tex_cntl_c & R128_Z_WRITE_ENABLE)) return; + + switch (r128ctx->regs.z_sten_cntl_c & R128_Z_PIX_WIDTH_MASK) { + case R128_Z_PIX_WIDTH_16: + write_mask = 0x0000ffff; + dst_bpp = R128_GMC_DST_16BPP; + break; + case R128_Z_PIX_WIDTH_24: + write_mask = 0x00ffffff; + dst_bpp = R128_GMC_DST_24BPP; + break; + case R128_Z_PIX_WIDTH_32: + write_mask = 0xffffffff; + dst_bpp = R128_GMC_DST_32BPP; + break; + default: return; + } + + cx += dPriv->x; + cy = dPriv->y + dPriv->h - cy - ch; + + /* Flush any outstanding vertex buffers */ + R128_FLUSH_VB(r128ctx); + + LOCK_HARDWARE(r128ctx); + + /* Set the write mask so that we _only_ clear the Z buffer */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_DP_WRITE_MASK, 0); + R128CCE(write_mask); + + /* Temporarily disable Z and stencil buffer and texture mapping modes */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_CNTL_C, 0); + R128CCE(r128ctx->regs.tex_cntl_c & ~(R128_Z_ENABLE | + R128_STENCIL_ENABLE | + R128_TEXMAP_ENABLE)); + + /* Cycle through the clip rects */ + while (nc--) { + int x = c[nc].x1; + int y = c[nc].y1; + int w = c[nc].x2 - x; + int h = c[nc].y2 - y; + + if (!all) { + if (x < cx) w -= cx - x, x = cx; + if (y < cy) h -= cy - y, y = cy; + + if (x + w > cx + cw) w = cx + cw - x; + if (y + h > cy + ch) h = cy + ch - y; + + if (w <= 0 || h <= 0) continue; + } + + x += r128ctx->r128Screen->depthX; + y += r128ctx->r128Screen->depthY; + + R128CCE_WAIT_LOCKED(5); + R128CCE3(R128_CCE_PACKET3_CNTL_PAINT_MULTI, 3); + R128CCE(R128_GMC_BRUSH_SOLID_COLOR + | dst_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_3D_FCN_EN /* FIXME?? */ + | R128_GMC_CLR_CMP_CNTL_DIS /* FIXME?? */ + | R128_AUX_CLIP_DIS /* FIXME?? */ + | R128_GMC_WR_MSK_DIS); /* FIXME?? */ + R128CCE(r128ctx->ClearDepth); + R128CCE((x << 16) | y); + R128CCE((w << 16) | h); + } + +#if 0 + /* Set the write mask so that we _only_ clear the Z buffer */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_DP_WRITE_MASK, 0); + R128CCE(0xffffffff); + + /* Restore Z and stencil buffer and texture mapping modes */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_CNTL_C, 0); + R128CCE(r128ctx->regs.tex_cntl_c); +#else + /* FIXME: We should be able to optimize this by restoring only the + registers that change (above) */ + /* NOTE: The restore of TEX_CNTL_C and R128_DP_WRITE_MASK is handled by + vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv */ + r128ctx->dirty = R128_UPDATE_CONTEXT; +#endif + + R128CCE_END_LOCKED(); + + UNLOCK_HARDWARE(r128ctx); +} + +/* Clear a color buffer */ +void r128ClearColorBuffer(r128ContextPtr r128ctx, GLboolean all, + GLint cx, GLint cy, GLint cw, GLint ch, + GLint drawX, GLint drawY) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; + int nc = dPriv->numClipRects; + XF86DRIClipRectPtr c = dPriv->pClipRects; + int dst_bpp; + + switch (r128ctx->r128Screen->bpp) { + case 8: + dst_bpp = R128_GMC_DST_8BPP_CI; + break; + case 16: + if (r128ctx->r128Screen->depth == 15) dst_bpp = R128_GMC_DST_15BPP; + else dst_bpp = R128_GMC_DST_16BPP; + break; + case 24: + dst_bpp = R128_GMC_DST_24BPP; + break; + case 32: + default: + dst_bpp = R128_GMC_DST_32BPP; + break; + } + + cx += dPriv->x; + cy = dPriv->y + dPriv->h - cy - ch; + + /* FIXME: use R128_GMC_DST_PITCH_OFFSET_CNTL to set to the back + buffer when we should be draing to the back buffer? */ + + /* Flush any outstanding vertex buffers */ + R128_FLUSH_VB(r128ctx); + + LOCK_HARDWARE(r128ctx); + + /* Temporarily disable Z and stencil buffer and texture mapping modes */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_CNTL_C, 0); + R128CCE(r128ctx->regs.tex_cntl_c & ~(R128_Z_ENABLE | + R128_STENCIL_ENABLE | + R128_TEXMAP_ENABLE)); + + /* Cycle through the clip rects */ + while (nc--) { + int x = c[nc].x1; + int y = c[nc].y1; + int w = c[nc].x2 - x; + int h = c[nc].y2 - y; + + if (!all) { + if (x < cx) w -= cx - x, x = cx; + if (y < cy) h -= cy - y, y = cy; + + if (x + w > cx + cw) w = cx + cw - x; + if (y + h > cy + ch) h = cy + ch - h; + + if (w <= 0 || h <= 0) continue; + } + + x += drawX; + y += drawY; + + R128CCE_WAIT_LOCKED(5); + R128CCE3(R128_CCE_PACKET3_CNTL_PAINT_MULTI, 3); + R128CCE(R128_GMC_BRUSH_SOLID_COLOR + | dst_bpp + | R128_GMC_SRC_DATATYPE_COLOR + | R128_ROP3_P + | R128_GMC_3D_FCN_EN /* FIXME?? */ + | R128_GMC_CLR_CMP_CNTL_DIS /* FIXME?? */ + | R128_AUX_CLIP_DIS); /* FIXME?? */ + R128CCE(r128ctx->ClearColor); + R128CCE((x << 16) | y); + R128CCE((w << 16) | h); + } + +#if 0 + /* Restore Z and stencil buffer and texture mapping modes */ + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_CNTL_C, 0); + R128CCE(r128ctx->regs.tex_cntl_c); +#else + /* FIXME: We should be able to optimize this by restoring only the + registers that change (above) */ + /* NOTE: The restore of TEX_CNTL_C is handled by + vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ALL_DIRTY; +#endif + + R128CCE_END_LOCKED(); + + UNLOCK_HARDWARE(r128ctx); +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_clear.h b/xc/lib/GL/mesa/src/drv/r128/r128_clear.h new file mode 100644 index 000000000..7018b05b4 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_clear.h @@ -0,0 +1,47 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_CLEAR_H_ +#define _R128_CLEAR_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128ClearDepthBuffer(r128ContextPtr r128ctx, GLboolean all, + GLint x, GLint y, GLint width, GLint height); +extern void r128ClearColorBuffer(r128ContextPtr r128ctx, GLboolean all, + GLint x, GLint y, GLint width, GLint height, + GLint drawX, GLint drawY); + +#endif +#endif /* _R128_CLEAR_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_context.c b/xc/lib/GL/mesa/src/drv/r128/r128_context.c new file mode 100644 index 000000000..0dd76cc2f --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_context.c @@ -0,0 +1,185 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_dd.h" +#include "r128_state.h" +#include "r128_span.h" +#include "r128_depth.h" +#include "r128_tex.h" +#include "r128_vb.h" +#include "r128_pipeline.h" + +#include "context.h" +#include "simple_list.h" + +/* Create the device specific context */ +r128ContextPtr r128CreateContext(GLvisual *glVisual, + XMesaContext c, + XMesaContext share_list) +{ + r128ContextPtr r128ctx; + GLcontext *shareCtx, *glCtx; + + r128ctx = (r128ContextPtr)Xmalloc(sizeof(*r128ctx)); + if (!r128ctx) return NULL; + + if (share_list) + shareCtx = ((r128ContextPtr)(share_list->private))->glCtx; + else + shareCtx = NULL; + + /* Initialize r128Context */ + r128ctx->xmCtx = c; + r128ctx->glCtx = gl_create_context(glVisual, + shareCtx, + (void *)r128ctx, + GL_TRUE); + r128ctx->display = c->display; + r128ctx->driContext = c->driContextPriv; + r128ctx->driDrawable = NULL; /* Set by XMesaMakeCurrent */ + r128ctx->dirty = R128_ALL_DIRTY; + r128ctx->dirty_context = R128_CTX_ALL_DIRTY; + r128ctx->needClip = GL_TRUE; + if (getenv("LIBGL_SOFTWARE_RENDERING")) + r128ctx->SWonly = GL_TRUE; + else + r128ctx->SWonly = GL_FALSE; + if (getenv("LIBGL_NO_SOFTWARE_FALLBACKS")) + r128ctx->SWfallbackDisable = GL_TRUE; + else + r128ctx->SWfallbackDisable = GL_FALSE; + r128ctx->r128Screen = + (r128ScreenPtr)(c->driContextPriv->driScreenPriv->private); + r128ctx->SAREA = + (R128SAREAPrivPtr)((char *)c->driContextPriv->driScreenPriv->pSAREA + + sizeof(XF86DRISAREARec)); + + r128ctx->CurrentTexObj[0] = NULL; + r128ctx->CurrentTexObj[1] = NULL; + make_empty_list(&r128ctx->TexObjList); + make_empty_list(&r128ctx->SwappedOut); +#if USE_AGP_TEXTURES + r128ctx->texHeap = mmInit(0, r128ctx->r128Screen->agpTexSize); +#else + r128ctx->texHeap = mmInit(0, r128ctx->r128Screen->textureSize); +#endif + r128ctx->lastTexAge = -1; + + r128ctx->useFastPath = GL_FALSE; + + r128ctx->vb = NULL; + + /* Initialize GLcontext */ + glCtx = r128ctx->glCtx; + + r128DDInitExtensions(glCtx); + + r128DDInitDriverFuncs(glCtx); + r128DDInitStateFuncs(glCtx); + r128DDInitSpanFuncs(glCtx); + r128DDInitDepthFuncs(glCtx); + r128DDInitTextureFuncs(glCtx); + + glCtx->Driver.TriangleCaps = (DD_TRI_CULL + | DD_TRI_LIGHT_TWOSIDE + | DD_TRI_OFFSET); +#if 0 + /* FIXME */ + glCtx->TriangleCaps |= DD_CLIP_FOG_COORD; +#endif + + /* Reset Mesa's current 2D texture pointers to the driver's textures */ + glCtx->Shared->DefaultD[2][0].DriverData = NULL; + glCtx->Shared->DefaultD[2][1].DriverData = NULL; + + /* If Mesa has current a vertex buffer, make sure the driver's VB + data is up to date */ + if (glCtx->VB) r128DDRegisterVB(glCtx->VB); + + /* Register the fast path */ + if (glCtx->NrPipelineStages) + glCtx->NrPipelineStages = + r128RegisterPipelineStages(glCtx->PipelineStage, + glCtx->PipelineStage, + glCtx->NrPipelineStages); + + r128DDInitState(r128ctx); + + return r128ctx; +} + +/* Destroy the device specific context */ +void r128DestroyContext(r128ContextPtr r128ctx) +{ + if (r128ctx) { + r128TexObjPtr t, next_t; + + foreach_s (t, next_t, &r128ctx->TexObjList) + r128DestroyTexObj(r128ctx, t); + + foreach_s (t, next_t, &r128ctx->SwappedOut) + r128DestroyTexObj(r128ctx, t); + + gl_destroy_context(r128ctx->glCtx); + Xfree(r128ctx); + } +} + +/* Load the device specific context into the hardware. The actual + setting of the hardware state is done in the r128UpdateHWState(). */ +r128ContextPtr r128MakeCurrent(r128ContextPtr oldCtx, + r128ContextPtr newCtx, + __DRIdrawablePrivate *dPriv) +{ + if (oldCtx) { + newCtx->dirty = R128_REQUIRE_QUIESCENCE; + if (oldCtx != newCtx) { + newCtx->dirty |= R128_UPDATE_CONTEXT; + newCtx->dirty_context = R128_CTX_ALL_DIRTY; + } + if (oldCtx->driDrawable != dPriv) + newCtx->dirty |= R128_UPDATE_WINPOS; + } else { + newCtx->dirty = R128_ALL_DIRTY; + newCtx->dirty_context = R128_CTX_ALL_DIRTY; + } + + newCtx->driDrawable = dPriv; + + return newCtx; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_context.h b/xc/lib/GL/mesa/src/drv/r128/r128_context.h new file mode 100644 index 000000000..c33c82874 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_context.h @@ -0,0 +1,197 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_CONTEXT_H_ +#define _R128_CONTEXT_H_ + +#ifdef GLX_DIRECT_RENDERING + +#include "r128_sarea.h" +#include "r128_texobj.h" +#include "r128_fastpath.h" +#include "r128_ccevb.h" + +/* Flags for what needs to be updated before a new primitive is rendered */ +#define R128_CLEAN 0x0000 +#define R128_REQUIRE_QUIESCENCE 0x0001 +#define R128_UPDATE_CONTEXT 0x0002 +#define R128_UPDATE_WINPOS 0x0004 +#define R128_UPDATE_TEX0IMAGES 0x0008 +#define R128_UPDATE_TEX1IMAGES 0x0010 +#define R128_UPDATE_TEXSTATE 0x0020 +#define R128_ALL_DIRTY 0xffff + +/* Flags for what context state needs to be updated */ +#define R128_CTX_CLEAN 0x0000 +#define R128_CTX_MISC 0x0001 +#define R128_CTX_ENGINESTATE 0x0002 +#define R128_CTX_TEX0STATE 0x0004 +#define R128_CTX_TEX1STATE 0x0008 +#define R128_CTX_TEXENVSTATE 0x0010 +#define R128_CTX_FOGSTATE 0x0020 +#define R128_CTX_ZSTENSTATE 0x0040 +#define R128_CTX_SCISSORS 0x0080 +#define R128_CTX_ALPHASTATE 0x0100 +#define R128_CTX_SETUPSTATE 0x0200 +#define R128_CTX_WIN_Z_POS 0x0400 +#define R128_CTX_FLUSH_PIX_CACHE 0x0800 +#define R128_CTX_ALL_DIRTY 0xffff + +/* Flags for software fallback cases */ +#define R128_FALLBACK_TEXTURE 0x0001 +#define R128_FALLBACK_DRAW_BUFFER 0x0002 +#define R128_FALLBACK_READ_BUFFER 0x0004 +#define R128_FALLBACK_COLORMASK 0x0008 +#define R128_FALLBACK_STIPPLE 0x0010 + +/* NOTE: The groups below need to be kept together so that a single + memcpy can be used to transfer data to the ring buffer */ +typedef struct { + CARD32 scale_3d_cntl; /* 0x1a00 */ + + CARD32 dst_pitch_offset_c; /* 0x1c80 */ + CARD32 dp_gui_master_cntl; + CARD32 sc_top_left_c; + CARD32 sc_bottom_right_c; + CARD32 z_offset_c; + CARD32 z_pitch_c; + CARD32 z_sten_cntl_c; + CARD32 tex_cntl_c; + CARD32 misc_3d_state_cntl_reg; + CARD32 texture_clr_cmp_clr_c; + CARD32 texture_clr_cmp_msk_c; + CARD32 fog_color_c; + CARD32 prim_tex_cntl_c; + CARD32 prim_texture_combine_cntl_c; + CARD32 tex_size_pitch_c; + CARD32 prim_tex_offset[R128_TEX_MAXLEVELS]; /* 0x1ce4 */ + + CARD32 sec_tex_cntl_c; /* 0x1d00 */ + CARD32 sec_tex_combine_cntl_c; + CARD32 sec_tex_offset[R128_TEX_MAXLEVELS]; + CARD32 constant_color_c; + CARD32 prim_texture_border_color_c; + CARD32 sec_texture_border_color_c; + CARD32 sten_ref_mask_c; + CARD32 plane_3d_mask_c; /* 0x1d44 */ + + CARD32 setup_cntl; /* 0x1bc4 */ + + CARD32 pm4_vc_fpu_setup; /* 0x071c */ + + CARD32 fog_3d_table_start; /* 0x1810 */ + CARD32 fog_3d_table_end; + CARD32 fog_3d_table_density; /* 0x181c */ + + CARD32 window_xy_offset; /* 0x1bcc */ + + CARD32 dp_write_mask; /* 0x16cc */ + + CARD32 pc_gui_ctlstat; /* 0x1748 */ +} r128ContextRegs; + +typedef struct { + XMesaContext xmCtx; /* XMesa context */ + GLcontext *glCtx; /* Mesa context */ + int dirty; /* Hardware state to be updated */ + int dirty_context; /* Context state to be updated */ + + int needClip; /* Primitives need to be clipped + to the window */ + + int SWonly; /* Force software-only rendering */ + int SWfallbackDisable; /* Disable software fallbacks */ + + + r128TexObjPtr CurrentTexObj[2]; /* Ptr to current texture + object associated with + each texture unit */ + r128TexObj TexObjList; /* List of textures swapped in */ + r128TexObj SwappedOut; /* List of textures swapped out */ + memHeap_t *texHeap; /* Global heap of textures */ + int lastTexAge; /* Last known global texture age */ + + int useFastPath; /* Currently using Fast Path code */ + int SetupIndex; /* Raster setup function index */ + int SetupDone; /* Partial raster setup done? */ + int RenderIndex; /* Render state function index */ + r128InterpFunc interp; /* Current vert interp function */ + + r128CCEVertBufPtr vb; /* VB currently being filled */ + + points_func PointsFunc; /* Current Points, Line, Triangle */ + line_func LineFunc; /* and Quad rendering functions */ + triangle_func TriangleFunc; + quad_func QuadFunc; + + CARD32 IndirectTriangles; /* Flags for point, line, + tri and quad software + fallbacks */ + CARD32 Fallback; /* Need software fallback */ + + r128ContextRegs regs; /* Hardware state */ + CARD32 Color; /* Current draw color */ + CARD32 ClearColor; /* Color used to clear color buffer */ + CARD32 ClearDepth; /* Value used to clear depth buffer */ + + int drawX; /* x-offset to current draw buffer */ + int drawY; /* y-offset to current draw buffer */ + + int readX; /* x-offset to current read buffer */ + int readY; /* y-offset to current read buffer */ + + R128SAREAPrivPtr SAREA; /* Pointer to SAREA private data */ + + Display *display; /* X server display */ + + __DRIcontextPrivate *driContext; /* DRI context */ + __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */ + + r128ScreenPtr r128Screen; /* Screen private DRI data */ +} r128ContextRec, *r128ContextPtr; + +#define R128_MESACTX(r128ctx) ((r128ctx)->glCtx) +#define R128_DRIDRAWABLE(r128ctx) ((r128ctx)->driDrawable) +#define R128_DRISCREEN(r128ctx) ((r128ctx)->r128Screen->driScreen) + +extern r128ContextPtr r128CreateContext(GLvisual *glVisual, + XMesaContext c, + XMesaContext share_list); +extern void r128DestroyContext(r128ContextPtr r128ctx); +extern r128ContextPtr r128MakeCurrent(r128ContextPtr oldCtx, + r128ContextPtr newCtx, + __DRIdrawablePrivate *dPriv); + +#endif +#endif /* _R128_CONTEXT_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_dd.c b/xc/lib/GL/mesa/src/drv/r128/r128_dd.c new file mode 100644 index 000000000..2e076ac31 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_dd.c @@ -0,0 +1,176 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_cce.h" +#include "r128_clear.h" +#include "r128_vb.h" +#include "r128_pipeline.h" +#include "r128_dd.h" + +/* Driver entry point for clearing color and ancillary buffers */ +static GLbitfield r128DDClear(GLcontext *ctx, GLbitfield mask, GLboolean all, + GLint x, GLint y, GLint width, GLint height) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + if (r128ctx->SWonly) { + /* FIXME: Provide software fallback for this case?? */ + } + + if (mask & DD_FRONT_LEFT_BIT) { + r128ClearColorBuffer(r128ctx, all, x, y, width, height, + r128ctx->r128Screen->fbX, + r128ctx->r128Screen->fbY); + mask &= ~DD_FRONT_LEFT_BIT; + } + + if (mask & DD_BACK_LEFT_BIT) { + r128ClearColorBuffer(r128ctx, all, x, y, width, height, + r128ctx->r128Screen->backX, + r128ctx->r128Screen->backY); + mask &= ~DD_BACK_LEFT_BIT; + } + + if (mask & DD_DEPTH_BIT) { + r128ClearDepthBuffer(r128ctx, all, x, y, width, height); + mask &= ~DD_DEPTH_BIT; + } + +#if 0 + /* FIXME: Add stencil support */ + if (mask & DD_STENCIL_BIT) { + r128ClearStencilBuffer(r128ctx, all, x, y, width, height); + mask &= ~DD_STENCIL_BIT; + } +#endif + + return mask; +} + +/* Return the current color buffer size */ +static void r128DDGetBufferSize(GLcontext *ctx, GLuint *width, GLuint *height) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + *width = r128ctx->driDrawable->w; + *height = r128ctx->driDrawable->h; +} + +/* Return various strings for glGetString() */ +static const GLubyte *r128DDGetString(GLcontext *ctx, GLenum name) +{ + switch (name) { + case GL_VENDOR: + return (GLubyte *)"Precision Insight, Inc."; + case GL_RENDERER: + return (GLubyte *)"Mesa DRI Rage128 20000320"; + default: + return NULL; + } +} + +/* Send all commands to the hardware. If vertex buffers or indirect + buffers are in use, then we need to make sure they are sent to the + hardware. All commands that are normally sent to the ring are + already considered `flushed'. */ +static void r128DDFlush(GLcontext *ctx) +{ + R128_FLUSH_VB(R128_CONTEXT(ctx)); +} + +/* Make sure all commands have been sent to the hardware and have + completed processing. */ +static void r128DDFinish(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + r128DDFlush(ctx); + R128CCEWaitForIdle(r128ctx->r128Screen); +} + +/* Return various parameters requested by Mesa */ +static GLint r128DDGetParameteri(const GLcontext *ctx, GLint param) +{ + switch (param) { +#if 0 + /* FIXME: Support for these needs to be added to Mesa */ + case DD_MAX_TEXTURE_SIZE: return 1024; + case DD_MAX_TEXTURES: return 2; +#endif +#if 0 + case DD_HAVE_HARDWARE_FOG: return 1; /* FIXME: Add HW fog support */ +#endif + default: return 0; + } +} + +/* Initialize the extensions supported by this driver */ +void r128DDInitExtensions(GLcontext *ctx) +{ + /* FIXME: Are there other extensions to enable/disable??? */ + gl_extensions_disable(ctx, "GL_EXT_shared_texture_palette"); + gl_extensions_disable(ctx, "GL_EXT_paletted_texture"); + gl_extensions_disable(ctx, "GL_EXT_point_parameters"); + gl_extensions_disable(ctx, "ARB_imaging"); + gl_extensions_disable(ctx, "GL_EXT_blend_minmax"); + gl_extensions_disable(ctx, "GL_EXT_blend_logic_op"); + gl_extensions_disable(ctx, "GL_EXT_blend_subtract"); + gl_extensions_disable(ctx, "GL_INGR_blend_func_separate"); + + if (getenv("LIBGL_NO_MULTITEXTURE")) + gl_extensions_disable(ctx, "GL_ARB_multitexture"); +} + +/* Initialize the driver's misc functions */ +void r128DDInitDriverFuncs(GLcontext *ctx) +{ + ctx->Driver.Clear = r128DDClear; + + ctx->Driver.GetBufferSize = r128DDGetBufferSize; + ctx->Driver.GetString = r128DDGetString; + ctx->Driver.Finish = r128DDFinish; + ctx->Driver.Flush = r128DDFlush; + + ctx->Driver.Error = NULL; + ctx->Driver.GetParameteri = r128DDGetParameteri; + + ctx->Driver.DrawPixels = NULL; + ctx->Driver.Bitmap = NULL; + + ctx->Driver.RegisterVB = r128DDRegisterVB; + ctx->Driver.UnregisterVB = r128DDUnregisterVB; + ctx->Driver.BuildPrecalcPipeline = r128DDBuildPrecalcPipeline; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_dd.h b/xc/lib/GL/mesa/src/drv/r128/r128_dd.h new file mode 100644 index 000000000..91aa02586 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_dd.h @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_DD_H_ +#define _R128_DD_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128DDInitExtensions(GLcontext *ctx); +extern void r128DDInitDriverFuncs(GLcontext *ctx); + +#endif +#endif /* _R128_DD_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_depth.c b/xc/lib/GL/mesa/src/drv/r128/r128_depth.c new file mode 100644 index 000000000..d389212d4 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_depth.c @@ -0,0 +1,158 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_state.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_depth.h" + +/* FIXME: only handles 16bpp depth buffer for now */ + +#define DEPTH_DECLS \ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); \ + r128ScreenPtr r128scrn = r128ctx->r128Screen; \ + int xoff = (r128ctx->driDrawable->x + \ + r128scrn->depthX); \ + int yoff = (r128ctx->driDrawable->y + \ + r128scrn->depthY); \ + int height = r128ctx->driDrawable->h; \ + unsigned char *zbase = (r128scrn->fb + \ + xoff * (r128scrn->bpp/8) + \ + yoff * r128scrn->fbStride); \ + volatile GLdepth *zptr; \ + int i; \ + (void)i + +/* Return a pointer to the offset in the depth buffer at (x,y) */ +#define DEPTH_ADDR(base, _x, _y) \ + (GLdepth*)(zbase + _x * (r128scrn->bpp/8) + \ + (height - _y) * r128scrn->fbStride) + +/* Update the depth buffer for a given span. This is only used for + software fallbacks. */ +static void r128DDWriteDepthSpan(GLcontext *ctx, + GLuint n, GLint x, GLint y, + const GLdepth z[], + const GLubyte mask[]) +{ + DEPTH_DECLS; + + zptr = DEPTH_ADDR(zbase, x, y); + + LOCK_HARDWARE(r128ctx); + R128WaitForIdle(r128scrn); + + for (i = 0; i < n; i++, zptr++) + if (mask[i]) { + *zptr = z[i]; + } + + UNLOCK_HARDWARE(r128ctx); +} + +/* Update the depth buffer for a given array of pixels. This is only + used for software fallbacks. */ +static void r128DDWriteDepthPixels(GLcontext *ctx, + GLuint n, + const GLint x[], + const GLint y[], + const GLdepth z[], + const GLubyte mask[]) +{ + DEPTH_DECLS; + + LOCK_HARDWARE(r128ctx); + R128WaitForIdle(r128scrn); + + for (i = 0; i < n; i++) + if (mask[i]) { + zptr = DEPTH_ADDR(zbase, x[i], y[i]); + *zptr = z[i]; + } + + UNLOCK_HARDWARE(r128ctx); +} + +/* Return a span in the depth buffer as ints. This is only used for + software fallbacks. */ +static void r128DDReadDepthSpan(GLcontext *ctx, + GLuint n, + GLint x, GLint y, GLdepth depth[]) +{ + DEPTH_DECLS; + + zptr = DEPTH_ADDR(zbase, x, y); + + LOCK_HARDWARE(r128ctx); + R128WaitForIdle(r128scrn); + + memcpy(depth, (void *)zptr, n*sizeof(*depth)); + + UNLOCK_HARDWARE(r128ctx); +} + +/* Return a span in the depth buffer as floats. This is only used for + software fallbacks. */ +static void r128DDReadDepthPixels(GLcontext *ctx, + GLuint n, + const GLint x[], const GLint y[], + GLdepth depth[]) +{ + DEPTH_DECLS; + + LOCK_HARDWARE(r128ctx); + R128WaitForIdle(r128scrn); + + for (i = 0; i < n; i++) { + zptr = DEPTH_ADDR(zbase, x[i], y[i]); + depth[i] = zptr[i]; + } + + UNLOCK_HARDWARE(r128ctx); +} + + +/* Initialize the driver's depth functions */ +void r128DDInitDepthFuncs(GLcontext *ctx) +{ + ctx->Driver.WriteDepthSpan = r128DDWriteDepthSpan; + ctx->Driver.WriteDepthPixels = r128DDWriteDepthPixels; + ctx->Driver.ReadDepthSpan = r128DDReadDepthSpan; + ctx->Driver.ReadDepthPixels = r128DDReadDepthPixels; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_depth.h b/xc/lib/GL/mesa/src/drv/r128/r128_depth.h new file mode 100644 index 000000000..fa35afc16 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_depth.h @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_DEPTH_H_ +#define _R128_DEPTH_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128DDInitDepthFuncs(GLcontext *ctx); + +#endif +#endif /* _R128_DEPTH_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.c b/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.c new file mode 100644 index 000000000..953f9d9a6 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.c @@ -0,0 +1,537 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_state.h" +#include "r128_vb.h" +#include "r128_tris.h" +#include "r128_fastpath.h" + +#include "mmath.h" +#include "cva.h" +#include "vertices.h" + +/* FIXME: These routines were copied from the i810 driver, and were only + slightly modified for the Rage 128. They still need to be optmizied + and cleaned up. Also, support for USE_RHW2 needs to be added. */ + +typedef struct r128_fast_table { + r128BuildVerticesFunc build_vertices; + r128InterpFunc interp; +} r128FastPathTable; + +#define POINT(x) r128DrawPoint(r128ctx, &vert[x].v, psize) +#define LINE(x,y) r128DrawLine(r128ctx, &vert[x].v, &vert[y].v, lwidth) +#define TRI(x,y,z) r128DrawTriangle(r128ctx, &vert[x].v, &vert[y].v, &vert[z].v) + +/* Direct, and no clipping required. The clip funcs have not been + written yet, so this is only useful for the fast path. */ +#define RENDER_POINTS(start, count) \ +do { \ + GLuint e; \ + for (e = start; e <= count; e++) \ + POINT(elt[e]); \ +} while (0) + +#define RENDER_LINE(i1, i) \ +do { \ + GLuint e1 = elt[i1], e = elt[i]; \ + LINE(e1, e); \ +} while (0) + +#define RENDER_TRI(i2, i1, i, pv, parity) \ +do { \ + GLuint e2 = elt[i2], e1 = elt[i1], e = elt[i]; \ + if (parity) { \ + GLuint tmp = e2; \ + e2 = e1; \ + e1 = tmp; \ + } \ + TRI(e2, e1, e); \ +} while (0) + +#define RENDER_QUAD(i3, i2, i1, i, pv) \ +do { \ + GLuint e3 = elt[i3], e2 = elt[i2], e1 = elt[i1], e = elt[i]; \ + TRI(e3, e2, e); \ + TRI(e2, e1, e); \ +} while (0) + +#define LOCAL_VARS \ + r128VertexPtr vert = R128_DRIVER_DATA(VB)->verts; \ + const GLuint *elt = VB->EltPtr->data; \ + GLcontext *ctx = VB->ctx; \ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); \ + const GLfloat lwidth = ctx->Line.Width; \ + const GLfloat psize = ctx->Point.Size; \ + (void) lwidth; (void)psize; (void) vert; + +#define TAG(x) x##_r128_smooth_indirect +#include "render_tmp.h" + + + +#define NEGATIVE(f) (f < 0) +#define DIFFERENT_SIGNS(a,b) ((a*b) < 0) +#define LINTERP(T, A, B) ((A) + (T) * ((B) - (A))) + + +#define INTERP_RGBA(t, out, a, b) \ +do { \ + int i; \ + for (i = 0; i < 4; i++) { \ + GLfloat fa = UBYTE_COLOR_TO_FLOAT_COLOR(a[i]); \ + GLfloat fb = UBYTE_COLOR_TO_FLOAT_COLOR(b[i]); \ + GLfloat fo = LINTERP(t, fa, fb); \ + FLOAT_COLOR_TO_UBYTE_COLOR(out[i], fo); \ + } \ +} while (0) + + +#define CLIP(SGN, V, PLANE) \ +do { \ + if (mask & PLANE) { \ + GLuint *indata = inlist[in]; \ + GLuint *outdata = inlist[in ^= 1]; \ + GLuint nr = n; \ + GLfloat *J = verts[indata[nr-1]].f; \ + GLfloat dpJ = (SGN J[V]) + J[3]; \ + \ + inlist[0] = vlist1; \ + for (i = n = 0 ; i < nr ; i++) { \ + GLuint elt_i = indata[i]; \ + GLfloat *I = verts[elt_i].f; \ + GLfloat dpI = (SGN I[V]) + I[3]; \ + \ + if (DIFFERENT_SIGNS(dpI, dpJ)) { \ + GLfloat *O = verts[next_vert].f; \ + GLfloat t, *in, *out; \ + \ + if (NEGATIVE(dpI)) { \ + t = dpI / (dpI - dpJ); \ + in = I; \ + out = J; \ + } else { \ + t = dpJ / (dpJ - dpI); \ + in = J; \ + out = I; \ + } \ + \ + interp(t, O, in, out); \ + \ + clipmask[next_vert] = 0; \ + outdata[n++] = next_vert++; \ + } \ + \ + clipmask[elt_i] |= PLANE; /* don't set up */ \ + \ + if (!NEGATIVE(dpI)) { \ + outdata[n++] = elt_i; \ + clipmask[elt_i] &= ~PLANE; /* set up after all */ \ + } \ + \ + J = I; \ + dpJ = dpI; \ + } \ + \ + if (n < 3) return; \ + } \ +} while (0) + +#define LINE_CLIP(x,y,z,w,PLANE) \ +do { \ + if (mask & PLANE) { \ + GLfloat dpI = DOT4V(I,x,y,z,w); \ + GLfloat dpJ = DOT4V(J,x,y,z,w); \ + \ + if (DIFFERENT_SIGNS(dpI, dpJ)) { \ + GLfloat *O = verts[next_vert].f; \ + GLfloat t = dpI / (dpI - dpJ); \ + \ + interp(t, O, I, J); \ + \ + clipmask[next_vert] = 0; \ + \ + if (NEGATIVE(dpI)) { \ + clipmask[elts[0]] |= PLANE; \ + I = O; \ + elts[0] = next_vert++; \ + } else { \ + clipmask[elts[1]] |= PLANE; \ + J = O; \ + elts[1] = next_vert++; \ + } \ + } else if (NEGATIVE(dpI)) return; \ + } \ +} while (0) + + +static void r128TriClip(GLuint **p_elts, + r128Vertex *verts, + GLubyte *clipmask, + GLuint *p_next_vert, + GLubyte mask, + r128InterpFunc interp) +{ + GLuint *elts = *p_elts; + GLuint next_vert = *p_next_vert; + GLuint in = 0; + GLuint n = 3; + GLuint vlist1[VB_MAX_CLIPPED_VERTS]; + GLuint vlist2[VB_MAX_CLIPPED_VERTS]; + GLuint *inlist[2]; + GLuint *out; + GLuint i; + + inlist[0] = elts; + inlist[1] = vlist2; + + CLIP(-,0,CLIP_RIGHT_BIT); + CLIP(+,0,CLIP_LEFT_BIT); + CLIP(-,1,CLIP_TOP_BIT); + CLIP(+,1,CLIP_BOTTOM_BIT); + CLIP(-,2,CLIP_FAR_BIT); + CLIP(+,2,CLIP_NEAR_BIT); + + /* Convert the planar polygon to a list of triangles */ + out = inlist[in]; + + for (i = 2 ; i < n ; i++) { + elts[0] = out[0]; + elts[1] = out[i-1]; + elts[2] = out[i]; + elts += 3; + } + + *p_next_vert = next_vert; + *p_elts = elts; +} + + +static void r128LineClip(GLuint **p_elts, + r128Vertex *verts, + GLubyte *clipmask, + GLuint *p_next_vert, + GLubyte mask, + r128InterpFunc interp) +{ + GLuint *elts = *p_elts; + GLfloat *I = verts[elts[0]].f; + GLfloat *J = verts[elts[1]].f; + GLuint next_vert = *p_next_vert; + + LINE_CLIP(1,0,0,-1,CLIP_LEFT_BIT); + LINE_CLIP(-1,0,0,1,CLIP_RIGHT_BIT); + LINE_CLIP(0,1,0,-1,CLIP_TOP_BIT); + LINE_CLIP(0,-1,0,1,CLIP_BOTTOM_BIT); + LINE_CLIP(0,0,1,-1,CLIP_FAR_BIT); + LINE_CLIP(0,0,-1,1,CLIP_NEAR_BIT); + + *p_next_vert = next_vert; + *p_elts += 2; +} + + + +#define CLIP_POINT(e) \ +do { \ + if (mask[e]) *out++ = e; \ +} while (0) + +#define CLIP_LINE(e1, e0) \ +do { \ + GLubyte ormask = mask[e0] | mask[e1]; \ + out[0] = e1; \ + out[1] = e0; \ + out += 2; \ + if (ormask) { \ + out-=2; \ + if (!(mask[e0] & mask[e1])) { \ + r128LineClip(&out, verts, mask, &next_vert, ormask, interp); \ + } \ + } \ +} while (0) + +#define CLIP_TRIANGLE(e2, e1, e0) \ +do { \ + GLubyte ormask; \ + out[0] = e2; \ + out[1] = e1; \ + out[2] = e0; \ + out += 3; \ + ormask = mask[e2] | mask[e1] | mask[e0]; \ + if (ormask) { \ + out -= 3; \ + if (!(mask[e2] & mask[e1] & mask[e0])) { \ + r128TriClip(&out, verts, mask, &next_vert, ormask, interp); \ + } \ + } \ +} while (0) + + + +/* Build a table of functions to clip each primitive type. These + * produce a list of elements in the appropriate 'reduced' primitive, + * ie (points, lines, triangles) containing all the clipped and + * unclipped primitives from the original list. + */ +#define LOCAL_VARS \ + r128ContextPtr r128ctx = R128_CONTEXT(VB->ctx); \ + r128VertexBufferPtr r128VB = R128_DRIVER_DATA(VB); \ + GLuint *elt = VB->EltPtr->data; \ + r128Vertex *verts = r128VB->verts; \ + GLuint next_vert = r128VB->last_vert; \ + GLuint *out = r128VB->clipped_elements.data; \ + GLubyte *mask = VB->ClipMask; \ + r128InterpFunc interp = r128ctx->interp; \ + (void) interp; (void) verts; + +#define POSTFIX \ + r128VB->clipped_elements.count = out - r128VB->clipped_elements.data; \ + r128VB->last_vert = next_vert; + + +#define INIT(x) + +#define RENDER_POINTS(start, count) \ +do { \ + GLuint i; \ + for (i = start; i < count; i++) \ + CLIP_POINT(elt[i]); \ +} while (0) + +#define RENDER_LINE(i1, i0) \ +do { \ + CLIP_LINE(elt[i1], elt[i0]); \ +} while (0) + +#define RENDER_TRI(i2, i1, i0, pv, parity) \ +do { \ + GLuint e2 = elt[i2], e1 = elt[i1], e0 = elt[i0]; \ + if (parity) e2 = elt[i1], e1 = elt[i2]; \ + CLIP_TRIANGLE(e2, e1, e0); \ +} while (0) + +#define RENDER_QUAD(i3, i2, i1, i0, pv) \ +do { \ + CLIP_TRIANGLE(elt[i3], elt[i2], elt[i0]); \ + CLIP_TRIANGLE(elt[i2], elt[i1], elt[i0]); \ +} while (0) + +#define TAG(x) r128_clip_##x##_elt +#include "render_tmp.h" + + +/* Pack rgba and/or texture into the remaining half of a 32 byte vertex. + */ +#define CLIP_UBYTE_COLOR 4 +#define CLIP_UBYTE_B 0 +#define CLIP_UBYTE_G 1 +#define CLIP_UBYTE_R 2 +#define CLIP_UBYTE_A 3 +#define CLIP_S0 6 +#define CLIP_T0 7 +#define CLIP_S1 8 +#define CLIP_T1 9 + +#define TYPE (0) +#define TAG(x) x +#include "r128_fasttmp.h" + +#define TYPE (R128_RGBA_BIT) +#define TAG(x) x##_RGBA +#include "r128_fasttmp.h" + +#define TYPE (R128_TEX0_BIT) +#define TAG(x) x##_TEX0 +#include "r128_fasttmp.h" + +#define TYPE (R128_RGBA_BIT | R128_TEX0_BIT) +#define TAG(x) x##_RGBA_TEX0 +#include "r128_fasttmp.h" + +#define TYPE (R128_RGBA_BIT | R128_TEX0_BIT | R128_TEX1_BIT) +#define TAG(x) x##_RGBA_TEX0_TEX1 +#include "r128_fasttmp.h" + +/* This one *could* get away with sneaking TEX1 into the color and + * specular slots, thus fitting inside a cache line. Would be even + * better to switch to a smaller vertex. + */ +#define TYPE (R128_TEX0_BIT | R128_TEX1_BIT) +#define TAG(x) x##_TEX0_TEX1 +#include "r128_fasttmp.h" + + + +/* Render elements directly from original list of vertices. */ +static void r128RenderElementsDirect(struct vertex_buffer *VB) +{ + GLcontext *ctx = VB->ctx; + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + GLenum prim = ctx->CVA.elt_mode; + GLuint nr = VB->EltPtr->count; + render_func func = render_tab_r128_smooth_indirect[prim]; + GLuint p = 0; + + if (r128ctx->dirty) r128UpdateHWState(r128ctx); + + do { + func(VB, 0, nr, 0); + } while (ctx->Driver.MultipassFunc && + ctx->Driver.MultipassFunc(VB, ++p)); +} + +/* Project vertices from clip to device space */ +static void r128ProjectVertices(struct vertex_buffer *VB) +{ + GLcontext *ctx = VB->ctx; + GLmatrix *mat = &ctx->Viewport.WindowMap; + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128VertexBufferPtr r128VB = R128_DRIVER_DATA(VB); + GLfloat m[16]; + + m[MAT_SX] = mat->m[MAT_SX]; + m[MAT_TX] = mat->m[MAT_TX]; + m[MAT_SY] = -mat->m[MAT_SY]; + m[MAT_TY] = -mat->m[MAT_TY] + r128ctx->driDrawable->h; + m[MAT_SZ] = mat->m[MAT_SZ] * (1.0 / 0x10000); + m[MAT_TZ] = mat->m[MAT_TZ] * (1.0 / 0x10000); + +#if USE_RHW2 + /* FIXME: Handle RHW2?? */ + gl_project_v16(r128VB->verts[VB->CopyStart].f, + r128VB->verts[r128VB->last_vert].f, + m, + 16 * 4); +#else + gl_project_v16(r128VB->verts[VB->CopyStart].f, + r128VB->verts[r128VB->last_vert].f, + m, + 16 * 4); +#endif +} + +/* Project clipped vertices from clip to device space */ +static void r128ProjectClippedVertices(struct vertex_buffer *VB) +{ + GLcontext *ctx = VB->ctx; + GLmatrix *mat = &ctx->Viewport.WindowMap; + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128VertexBufferPtr r128VB = R128_DRIVER_DATA(VB); + GLfloat m[16]; + + m[MAT_SX] = mat->m[MAT_SX]; + m[MAT_TX] = mat->m[MAT_TX]; + m[MAT_SY] = -mat->m[MAT_SY]; + m[MAT_TY] = -mat->m[MAT_TY] + r128ctx->driDrawable->h; + m[MAT_SZ] = mat->m[MAT_SZ] * (1.0 / 0x10000); + m[MAT_TZ] = mat->m[MAT_TZ] * (1.0 / 0x10000); + +#if USE_RHW2 + /* FIXME: Handle RHW2?? */ + gl_project_clipped_v16(r128VB->verts[VB->CopyStart].f, + r128VB->verts[r128VB->last_vert].f, + m, + 16 * 4, + VB->ClipMask + VB->CopyStart); +#else + gl_project_clipped_v16(r128VB->verts[VB->CopyStart].f, + r128VB->verts[r128VB->last_vert].f, + m, + 16 * 4, + VB->ClipMask + VB->CopyStart); +#endif +} + +static r128FastPathTable r128FastTab[0x80]; + +/* Initialize the table of fast path support functions */ +void r128FastPathInit(void) +{ + r128_clip_render_init_elt(); + render_init_r128_smooth_indirect(); + + r128_init_fastpath(&r128FastTab[0]); + r128_init_fastpath_RGBA(&r128FastTab[R128_RGBA_BIT]); + r128_init_fastpath_TEX0(&r128FastTab[R128_TEX0_BIT]); + r128_init_fastpath_RGBA_TEX0(&r128FastTab[R128_RGBA_BIT|R128_TEX0_BIT]); + r128_init_fastpath_TEX0_TEX1(&r128FastTab[R128_TEX0_BIT|R128_TEX1_BIT]); + r128_init_fastpath_RGBA_TEX0_TEX1(&r128FastTab[R128_RGBA_BIT|R128_TEX0_BIT| + R128_TEX1_BIT]); +} + +#define VALID_SETUP (R128_RGBA_BIT | R128_TEX0_BIT | R128_TEX1_BIT) + +void r128FastPath(struct vertex_buffer *VB) +{ + GLcontext *ctx = VB->ctx; + GLenum prim = ctx->CVA.elt_mode; + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128FastPathTable *tab = &r128FastTab[r128ctx->SetupIndex & VALID_SETUP]; + GLuint do_cliptest = 1; + + gl_prepare_arrays_cva(VB); /* still need this */ + + /* Reserve enough space for the pathological case */ + if (VB->EltPtr->count * 12 > R128_DRIVER_DATA(VB)->size) { + r128ResizeVB(VB, VB->EltPtr->count * 12); + do_cliptest = 1; + } + + tab->build_vertices(VB, do_cliptest); /* object->clip space */ + + if (r128ctx->dirty) r128UpdateHWState(r128ctx); + + if (VB->ClipOrMask) { + if (!VB->ClipAndMask) { + render_func *clip = r128_clip_render_tab_elt; + + r128ctx->interp = tab->interp; + clip[prim](VB, 0, VB->EltPtr->count, 0); /* build new elts */ + ctx->CVA.elt_mode = gl_reduce_prim[prim]; + VB->EltPtr = &(R128_DRIVER_DATA(VB)->clipped_elements); + r128ProjectClippedVertices(VB); /* clip->device space */ + r128RenderElementsDirect(VB); /* render using new list */ + } + } else { + r128ProjectVertices(VB); /* clip->device space */ + r128RenderElementsDirect(VB); /* render using orig list */ + } + + /* This indicates that there is no cached data to reuse */ + VB->pipeline->data_valid = 0; + VB->pipeline->new_state = 0; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.h b/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.h new file mode 100644 index 000000000..47bb92049 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_fastpath.h @@ -0,0 +1,48 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_FASTPATH_H_ +#define _R128_FASTPATH_H_ + +typedef void (*r128BuildVerticesFunc)(struct vertex_buffer *VB, + GLuint do_cliptest); +typedef void (*r128InterpFunc)(GLfloat t, + GLfloat *result, + const GLfloat *in, + const GLfloat *out); + +extern void r128FastPathInit(void); +extern void r128FastPath(struct vertex_buffer *VB); + +#endif /* _R128_FASTPATH_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_fasttmp.h b/xc/lib/GL/mesa/src/drv/r128/r128_fasttmp.h new file mode 100644 index 000000000..e76dd52b4 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_fasttmp.h @@ -0,0 +1,155 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +/* FIXME: These routines were copied from the i810 driver, and were only + slightly modified for the Rage 128. They still need to be optmizied + and cleaned up. Also, support for USE_RHW2 needs to be added. */ + +/* The first part of setup is applied to all vertices, clipped or + * unclipped. This data w!ill be used for clipping, and then all + * vertices with a zero clipmask will be projected to device space. + * + * This could be split into several loops, but - it seems that the + * large stride of the fxVertices makes cache issues the big + * performance factor, and that multiple loops mean multiple cache + * misses.... + */ +static void TAG(r128_setup_full)(struct vertex_buffer *VB, GLuint do_cliptest) +{ + GLcontext *ctx = VB->ctx; + r128VertexBufferPtr r128VB = R128_DRIVER_DATA(VB); + const GLfloat *m = ctx->ModelProjectMatrix.m; + GLuint start = VB->CopyStart; + GLuint count = VB->Count; + GLuint i; + + gl_xform_points3_v16_general(r128VB->verts[start].f, + m, + VB->ObjPtr->start, + VB->ObjPtr->stride, + count - start); + + if (do_cliptest) { + VB->ClipAndMask = ~0; + VB->ClipOrMask = 0; + gl_cliptest_points4_v16(r128VB->verts[start].f, + r128VB->verts[count].f, + &(VB->ClipOrMask), + &(VB->ClipAndMask), + VB->ClipMask + start); + } + + /* These branches are all resolved at compile time. Hopefully all + * the pointers are valid addresses even when not enabled. + */ + if (TYPE) { + GLubyte *color = VB->ColorPtr->start; + GLfloat *tex0_data = VB->TexCoordPtr[0]->start; + GLfloat *tex1_data = VB->TexCoordPtr[1]->start; + + GLuint color_stride = VB->ColorPtr->stride; + GLuint tex0_stride = VB->TexCoordPtr[0]->stride; + GLuint tex1_stride = VB->TexCoordPtr[1]->stride; + + GLfloat *f = r128VB->verts[start].f; + + for (i = start ; i < count ; i++, f += 16) { + if (TYPE & R128_RGBA_BIT) { + GLubyte *b = (GLubyte *)&f[CLIP_UBYTE_COLOR]; + GLubyte *col = color; color += color_stride; + b[CLIP_UBYTE_R] = col[0]; + b[CLIP_UBYTE_G] = col[1]; + b[CLIP_UBYTE_B] = col[2]; + b[CLIP_UBYTE_A] = col[3]; + } + if (TYPE & R128_TEX0_BIT) { + f[CLIP_S0] = tex0_data[0]; + f[CLIP_T0] = tex0_data[1]; + STRIDE_F(tex0_data, tex0_stride); + } + if (TYPE & R128_TEX1_BIT) { + f[CLIP_S1] = tex1_data[0]; + f[CLIP_T1] = tex1_data[1]; + STRIDE_F(tex1_data, tex1_stride); + } + } + } + + r128VB->clipped_elements.count = start; + r128VB->last_vert = count; +} + + +/* Changed to just put the interp func instead of the whole clip + * routine into the header. Less code and better chance of doing some + * of this stuff in assembly. + */ +static void TAG(r128_interp_vert)(GLfloat t, + GLfloat *O, + const GLfloat *I, + const GLfloat *J) +{ + O[0] = LINTERP(t, I[0], J[0]); + O[1] = LINTERP(t, I[1], J[1]); + O[2] = LINTERP(t, I[2], J[2]); + O[3] = LINTERP(t, I[3], J[3]); + + if (TYPE & R128_RGBA_BIT) { + INTERP_RGBA(t, + ((GLubyte *)&(O[4])), + ((GLubyte *)&(I[4])), + ((GLubyte *)&(J[4]))); + } + + if (TYPE & R128_TEX0_BIT) { + O[6] = LINTERP(t, I[6], J[6]); + O[7] = LINTERP(t, I[7], J[7]); + } + + if (TYPE & R128_TEX1_BIT) { + O[8] = LINTERP(t, I[8], J[8]); + O[9] = LINTERP(t, I[9], J[9]); + } +} + + +static void TAG(r128_init_fastpath)(r128FastPathTable *tab) +{ + tab->build_vertices = TAG(r128_setup_full); + tab->interp = TAG(r128_interp_vert); +} + +#undef TYPE +#undef TAG +#undef SIZE diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_init.h b/xc/lib/GL/mesa/src/drv/r128/r128_init.h new file mode 100644 index 000000000..2140a7525 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_init.h @@ -0,0 +1,70 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_INIT_H_ +#define _R128_INIT_H_ + +#ifdef GLX_DIRECT_RENDERING + +#include <X11/Xlibint.h> + +#include "types.h" +#include "xmesaP.h" +#include "xf86drm.h" +#include "dri_tmm.h" +#include "dri_mesaint.h" + +#include "r128_screen.h" +#include "r128_context.h" + +/* NOTE: The vertex buffer code is currently unstable because of the + switches between CCE and MMIO mode in the X server. Fixing the X + server to use the CCE should fix this problem. So, for now, it is + recommended that you do not use it. */ + +#define DEBUG 1 +#define USE_FAST_PATH 1 +#define USE_VERTEX_BUFFERS 0 +#define USE_AGP_TEXTURES 0 +#define USE_RGB8_TEXTURES 0 +#define FLUSH_VB_ON_STATE_CHANGE 1 + + +#if DEBUG +#include <stdio.h> +#define R128_DEBUG(p) printf p +#endif + +#endif +#endif /* _R128_INIT_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_lock.h b/xc/lib/GL/mesa/src/drv/r128/r128_lock.h new file mode 100644 index 000000000..58bb33f47 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_lock.h @@ -0,0 +1,146 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_LOCK_H_ +#define _R128_LOCK_H_ + +#ifdef GLX_DIRECT_RENDERING + +/* + * You can turn this on to find locking conflicts. +#define DEBUG_LOCKING +*/ +#ifdef DEBUG_LOCKING +extern char *prevLockFile; +extern int prevLockLine; + +#define DEBUG_LOCK() \ + do { \ + prevLockFile = (__FILE__); \ + prevLockLine = (__LINE__); \ + } while (0) + +#define DEBUG_RESET() \ + do { \ + prevLockFile = 0; \ + prevLockLine = 0; \ + } while (0) + +#define DEBUG_CHECK_LOCK() \ + do { \ + if (prevLockFile) { \ + fprintf(stderr, \ + "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \ + prevLockFile, prevLockLine, __FILE__, __LINE__); \ + exit(1); \ + } \ + } while (0) + +#else + +#define DEBUG_LOCK() +#define DEBUG_RESET() +#define DEBUG_CHECK_LOCK() + +#endif + +/* + * !!! We may want to separate locks from locks with validation. This + * could be used to improve performance for those things commands that + * do not do any drawing !!! + */ + +/* Lock the hardware using the current context */ +#define LOCK_HARDWARE(CC) \ + do { \ + char __ret = 0; \ + __DRIcontextPrivate *cPriv = CC->driContext; \ + __DRIscreenPrivate *sPriv = CC->r128Screen->driScreen; \ + \ + DEBUG_CHECK_LOCK(); \ + DRM_CAS(&sPriv->pSAREA->lock, cPriv->hHWContext, \ + DRM_LOCK_HELD|cPriv->hHWContext, __ret); \ + if (__ret) { \ + /* We lost the context, so we need to request the lock from \ + the kernel and update our state. */ \ + drmGetLock(sPriv->fd, cPriv->hHWContext, 0); \ + XMesaUpdateState(CC->xmCtx); \ + } \ + DEBUG_LOCK(); \ + } while (0) + +/* Unlock the hardware using the current context */ +#define UNLOCK_HARDWARE(CC) \ + do { \ + __DRIcontextPrivate *cPriv = CC->driContext; \ + __DRIscreenPrivate *sPriv = CC->r128Screen->driScreen; \ + \ + DRM_UNLOCK(sPriv->fd, &sPriv->pSAREA->lock, cPriv->hHWContext); \ + DEBUG_RESET(); \ + } while (0) + +/* + * This pair of macros makes a loop over the drawing operations, so it + * is not self contained and does not have the nice single statement + * semantics of most macros. + */ +/* FIXME: The Rage128 has multiple clip rects -- optimize! */ +#define BEGIN_CLIP_LOOP(CC) \ + do { \ + __DRIdrawablePrivate *_dPriv = CC->driDrawable; \ + int _nc = _dPriv->numClipRects; \ + \ + LOCK_HARDWARE(CC); \ + while (_nc--) { \ + if (CC->needClip) { \ + r128SetClipRect(CC, &_dPriv->pClipRects[_nc]); \ + } + +/* FIXME: Have the X server save/restore its own clip rect */ +#define END_CLIP_LOOP(CC) \ + if (CC->needClip) { \ + /* FIXME: Move this to r128_state.c ?? */ \ + unsigned char *R128MMIO = CC->r128Screen->mmio; \ + R128CCE_WAIT_LOCKED(3); \ + R128CCE0(R128_CCE_PACKET0, R128_SC_TOP_LEFT_C, 1); \ + R128CCE(0x00000000); \ + R128CCE(0x1fff1fff); \ + R128CCE_END_LOCKED(); \ + } \ + } \ + UNLOCK_HARDWARE(CC); \ + } while (0) + +#endif +#endif /* _R128_LOCK_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_mesa.h b/xc/lib/GL/mesa/src/drv/r128/r128_mesa.h new file mode 100644 index 000000000..3a697b466 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_mesa.h @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_MESA_H_ +#define _R128_MESA_H_ + +#ifdef GLX_DIRECT_RENDERING + +#define R128_CONTEXT(ctx) ((r128ContextPtr)(ctx->DriverCtx)) + +#endif +#endif /* _R128_MESA_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.c b/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.c new file mode 100644 index 000000000..55487ffcd --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.c @@ -0,0 +1,126 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_vb.h" +#include "r128_fastpath.h" +#include "r128_pipeline.h" + +#include "types.h" + +static struct gl_pipeline_stage r128FastStage = { + "R128 Fast Path", + (PIPE_OP_VERT_XFORM | + PIPE_OP_RAST_SETUP_0 | + PIPE_OP_RAST_SETUP_1 | + PIPE_OP_RENDER), + PIPE_PRECALC, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + r128FastPath +}; + +/* Build the PRECALC pipeline with our stage, if possible. Otherwise, + return GL_FALSE */ +GLboolean r128DDBuildPrecalcPipeline(GLcontext *ctx) +{ +#if USE_FAST_PATH + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + struct gl_pipeline *pipe = &ctx->CVA.pre; + + if (r128ctx->RenderIndex == 0 && + !(ctx->Enabled & (TEXTURE0_3D | + TEXTURE1_3D | + ENABLE_TEXMAT0 | + ENABLE_TEXMAT1 | + ENABLE_TEXGEN0 | + ENABLE_TEXGEN1 | + ENABLE_USERCLIP | + ENABLE_LIGHT | + ENABLE_FOG)) && + (ctx->Array.Flags & (VERT_OBJ_234 | + VERT_TEX0_4 | + VERT_TEX1_4 | + VERT_ELT)) == (VERT_OBJ_23 | + VERT_ELT)) { + pipe->stages[0] = &r128FastStage; + pipe->stages[1] = 0; + pipe->new_inputs = ctx->RenderFlags & VERT_DATA; + pipe->ops = pipe->stages[0]->ops; + + r128ctx->useFastPath = GL_TRUE; + return GL_TRUE; + } + + if (r128ctx->useFastPath) { + r128ctx->useFastPath = GL_FALSE; + + ctx->CVA.VB->ClipOrMask = 0; + ctx->CVA.VB->ClipAndMask = CLIP_ALL_BITS; + ctx->Array.NewArrayState |= ctx->Array.Summary; + } +#endif + + return GL_FALSE; +} + +/* Register the pipeline with our stages included */ +GLuint r128RegisterPipelineStages(struct gl_pipeline_stage *out, + const struct gl_pipeline_stage *in, + GLuint nr) +{ +#if USE_FAST_PATH + int i; + + for (i = 0; i < nr; i++) { + out[i] = in[i]; + switch (in[i].ops) { + case PIPE_OP_RAST_SETUP_0: + out[i].cva_state_change = (NEW_LIGHTING | + NEW_TEXTURING | + NEW_RASTER_OPS); + out[i].state_change = ~0; + out[i].check = r128CheckPartialRasterSetup; + out[i].run = r128PartialRasterSetup; + break; + + case PIPE_OP_RAST_SETUP_0|PIPE_OP_RAST_SETUP_1: + out[i].run = r128DoRasterSetup; + break; + } + } +#endif + + return nr; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.h b/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.h new file mode 100644 index 000000000..280e6b943 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_pipeline.h @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_PIPELINE_H_ +#define _R128_PIPELINE_H_ + +extern GLboolean r128DDBuildPrecalcPipeline(GLcontext *ctx); +extern GLuint r128RegisterPipelineStages(struct gl_pipeline_stage *out, + const struct gl_pipeline_stage *in, + GLuint nr); + +#endif /* _R128_PIPELINE_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_screen.c b/xc/lib/GL/mesa/src/drv/r128/r128_screen.c new file mode 100644 index 000000000..32e72e97d --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_screen.c @@ -0,0 +1,160 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_dri.h" +#include "r128_reg.h" + +#include "r128_init.h" +#include "r128_context.h" +#include "r128_xmesa.h" +#include "r128_tris.h" +#include "r128_vb.h" +#include "r128_fastpath.h" + +/* Create the device specific screen private data struct */ +r128ScreenPtr r128CreateScreen(__DRIscreenPrivate *sPriv) +{ + r128ScreenPtr r128Screen; + R128DRIPtr r128DRIPriv = (R128DRIPtr)sPriv->pDevPriv; + + /* Allocate the private area */ + r128Screen = (r128ScreenPtr)Xmalloc(sizeof(*r128Screen)); + if (!r128Screen) return NULL; + + r128Screen->mmioRgn.handle = r128DRIPriv->registerHandle; + r128Screen->mmioRgn.size = r128DRIPriv->registerSize; + if (drmMap(sPriv->fd, + r128Screen->mmioRgn.handle, + r128Screen->mmioRgn.size, + (drmAddressPtr)&r128Screen->mmio)) { + Xfree(r128Screen); + return NULL; + } + + r128Screen->agpRgn.handle = r128DRIPriv->agpHandle; + r128Screen->agpRgn.size = r128DRIPriv->agpSize; + if (drmMap(sPriv->fd, + r128Screen->agpRgn.handle, + r128Screen->agpRgn.size, + (drmAddressPtr)&r128Screen->agp)) { + drmUnmap((drmAddress)r128Screen->mmio, r128Screen->mmioRgn.size); + Xfree(r128Screen); + return NULL; + } + + r128Screen->deviceID = r128DRIPriv->deviceID; + + r128Screen->width = r128DRIPriv->width; + r128Screen->height = r128DRIPriv->height; + r128Screen->depth = r128DRIPriv->depth; + r128Screen->bpp = r128DRIPriv->bpp; + + r128Screen->fb = sPriv->pFB; + r128Screen->fbOffset = sPriv->fbOrigin; + r128Screen->fbStride = sPriv->fbStride; + r128Screen->fbSize = sPriv->fbSize; + + r128Screen->fbX = r128DRIPriv->fbX; + r128Screen->fbY = r128DRIPriv->fbY; + r128Screen->backX = r128DRIPriv->backX; + r128Screen->backY = r128DRIPriv->backY; + r128Screen->depthX = r128DRIPriv->depthX; + r128Screen->depthY = r128DRIPriv->depthY; + r128Screen->textureX = r128DRIPriv->textureX; + r128Screen->textureY = r128DRIPriv->textureY; + r128Screen->textureSize = r128DRIPriv->textureSize; + r128Screen->log2TexGran = r128DRIPriv->log2TexGran; + +#if 0 + /* FIXME: For testing only */ + r128Screen->textureX = 0; + r128Screen->textureY = 8192; + r128Screen->textureSize = 4*1024*1024; + r128Screen->log2TexGran = 15; +#endif + +#if 1 + /* FIXME: For testing only */ + if (getenv("LIBGL_SHOW_BUFFERS")) { + r128Screen->backX = 0; + r128Screen->backY = r128DRIPriv->height/2; + r128Screen->depthX = r128DRIPriv->width/2; + r128Screen->depthY = r128DRIPriv->height/2; + } +#endif + + r128Screen->CCEMode = r128DRIPriv->CCEMode; + r128Screen->CCEFifoSize = r128DRIPriv->CCEFifoSize; + + r128Screen->ringStart = r128DRIPriv->ringStart; + r128Screen->ringSize = r128DRIPriv->ringSize; + r128Screen->ringWritePtr = &r128DRIPriv->ringWrite; + r128Screen->ringReadPtr = (int *)(r128Screen->agp + + r128DRIPriv->ringReadOffset); + + r128Screen->vbStart = r128DRIPriv->vbStart; + r128Screen->vbSize = r128DRIPriv->vbSize; + + r128Screen->indStart = r128DRIPriv->indStart; + r128Screen->indSize = r128DRIPriv->indSize; + + r128Screen->agpTexStart = r128DRIPriv->agpTexStart; + r128Screen->agpTexSize = r128DRIPriv->agpTexSize; + r128Screen->log2AGPTexGran = r128DRIPriv->log2AGPTexGran; + + r128Screen->MMIOFifoSlots = 0; + r128Screen->CCEFifoSlots = 0; + + r128Screen->CCEFifoAddr = R128_PM4_FIFO_DATA_EVEN; + + r128Screen->driScreen = sPriv; + + r128FastPathInit(); + r128TriangleFuncsInit(); + r128SetupInit(); + + return r128Screen; +} + +/* Destroy the device specific screen private data struct */ +void r128DestroyScreen(__DRIscreenPrivate *sPriv) +{ + r128ScreenPtr r128Screen = (r128ScreenPtr)sPriv->private; + + drmUnmap((drmAddress)r128Screen->mmio, r128Screen->mmioRgn.size); + drmUnmap((drmAddress)r128Screen->agp, r128Screen->agpRgn.size); + + Xfree(r128Screen); + sPriv->private = NULL; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_screen.h b/xc/lib/GL/mesa/src/drv/r128/r128_screen.h new file mode 100644 index 000000000..07670331e --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_screen.h @@ -0,0 +1,122 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_SCREEN_H_ +#define _R128_SCREEN_H_ + +#ifdef GLX_DIRECT_RENDERING + +typedef struct { + drmHandle handle; /* Handle to the DRM region */ + drmSize size; /* Size of the DRM region */ +} r128RegionRec, *r128RegionPtr; + +typedef struct { + /* FIXME: There needs to be two register regions. One to allow + read-only access to the block of non-FIFO'd GUI registers + (0x0000-0x0FFC), and one to allow read/write acces to the block + of FIFO'd GUI registers (0x1000-0x1FFC) */ + + /* MMIO register data */ + r128RegionRec mmioRgn; + unsigned char *mmio; + + /* AGP data */ + r128RegionRec agpRgn; + unsigned char *agp; + + /* Frame buffer data */ + unsigned char *fb; + unsigned long fbOffset; + int fbStride; + int fbSize; + + int CCEMode; /* CCE mode that server/clients use */ + int CCEFifoSize; /* Size of the CCE command FIFO */ + + /* CCE ring buffer data */ + unsigned long ringStart; + int ringSize; + /* FIXME: These should be in the + SAREA so that they can be + shared with other clients. */ + int *ringWritePtr; /* Pointer to current write addr */ + int *ringReadPtr; /* Pointer to current read addr */ + + /* CCE vertex buffer data */ + unsigned long vbStart; + int vbSize; + + /* CCE indirect buffer data */ + unsigned long indStart; + int indSize; + + /* CCE AGP Texture data */ + unsigned long agpTexStart; + int agpTexSize; + int log2AGPTexGran; + + /* DRI screen private data */ + int deviceID; /* PCI device ID */ + int width; /* Width in pixels of display */ + int height; /* Height in scanlines of display */ + int depth; /* Depth of display (8, 15, 16, 24) */ + int bpp; /* Bit depth of disp (8, 16, 24, 32) */ + + int fbX; /* Start of frame buffer */ + int fbY; + int backX; /* Start of shared back buffer */ + int backY; + int depthX; /* Start of shared depth buffer */ + int depthY; + int textureX; /* Start of textures in frame buffer */ + int textureY; + int textureSize; + int log2TexGran; + + int MMIOFifoSlots; /* Free slots in the FIFO (64 max) */ + int CCEFifoSlots; /* Free slots in the CCE FIFO */ + + int CCEFifoAddr; /* MMIO offset to write next CCE + value (only used when CCE is + in PIO mode). */ + + __DRIscreenPrivate *driScreen; +} r128ScreenRec, *r128ScreenPtr; + +r128ScreenPtr r128CreateScreen(__DRIscreenPrivate *sPriv); +void r128DestroyScreen(__DRIscreenPrivate *sPriv); + +#endif +#endif /* _R128_SCREEN_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_span.c b/xc/lib/GL/mesa/src/drv/r128/r128_span.c new file mode 100644 index 000000000..2bd8db1cf --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_span.c @@ -0,0 +1,186 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_state.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_span.h" + +/* Null functions for span functions not yet implemented */ + +static void r128DDWriteRGBASpan(const GLcontext *ctx, + GLuint n, + GLint x, GLint y, + const GLubyte rgba[][4], + const GLubyte mask[]) {} +static void r128DDWriteRGBSpan(const GLcontext *ctx, + GLuint n, + GLint x, GLint y, + const GLubyte rgb[][3], + const GLubyte mask[]) {} +static void r128DDWriteMonoRGBASpan(const GLcontext *ctx, + GLuint n, + GLint x, GLint y, + const GLubyte mask[]) {} +static void r128DDWriteRGBAPixels(const GLcontext *ctx, + GLuint n, + const GLint x[], const GLint y[], + const GLubyte rgba[][4], + const GLubyte mask[]) {} +static void r128DDWriteMonoRGBAPixels(const GLcontext *ctx, + GLuint n, + const GLint x[], const GLint y[], + const GLubyte mask[]) {} +static void r128DDReadRGBASpan(const GLcontext *ctx, + GLuint n, + GLint x, GLint y, + GLubyte rgba[][4]) {} +static void r128DDReadRGBAPixels(const GLcontext *ctx, + GLuint n, + const GLint x[], const GLint y[], + GLubyte rgba[][4], + const GLubyte mask[]) {} + +/* 16bpp-specific span functions */ + +#define DBG 0 + +#define LOCAL_VARS \ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); \ + r128ScreenPtr r128scrn = r128ctx->r128Screen; \ + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; \ + GLuint pitch = r128scrn->fbStride; \ + GLuint height = dPriv->h; \ + char *buf = (char *)(r128scrn->fb + \ + (r128ctx->readX + dPriv->x) * (r128scrn->bpp/8) + \ + (r128ctx->readY + dPriv->y) * pitch) + +#define INIT_MONO_PIXEL(p) \ + GLushort p = R128_CONTEXT(ctx)->Color; + +#define CLIPPIXEL(_x,_y) (_x >= minx && _x <= maxx && \ + _y >= miny && _y <= maxy) + +#define CLIPSPAN(_x,_y,_n,_x1,_n1,_i) \ + if (_y < miny || _y >= maxy) _n1 = 0, _x1 = x; \ + else { \ + _n1 = _n; \ + _x1 = _x; \ + if (_x1 < minx) _i += (minx - _x1), _x1 = minx; \ + if (_x1 + _n1 > maxx) n1 -= (_x1 + n1 - maxx); \ + } + +#define HW_CLIPLOOP() \ + do { \ + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; \ + int _nc = dPriv->numClipRects; \ + \ + LOCK_HARDWARE(r128ctx); \ + R128WaitForIdle(r128scrn); \ + while (_nc--) { \ + int minx = dPriv->pClipRects[_nc].x1 - dPriv->x; \ + int miny = dPriv->pClipRects[_nc].y1 - dPriv->y; \ + int maxx = dPriv->pClipRects[_nc].x2 - dPriv->x; \ + int maxy = dPriv->pClipRects[_nc].y2 - dPriv->y; + +#define HW_ENDCLIPLOOP() \ + } \ + UNLOCK_HARDWARE(r128ctx); \ + } while (0) + + +#define Y_FLIP(_y) (height - _y) +#define WRITE_RGBA(_x, _y, r, g, b, a) \ + *(GLushort *)(buf + (_x)*2 + (_y)*pitch) = ((((int)r & 0xf8) << 8) | \ + (((int)g & 0xfc) << 3) | \ + (((int)b & 0xf8) >> 3)) +#define WRITE_PIXEL(_x, _y, p) \ + *(GLushort *)(buf + (_x)*2 + (_y)*pitch) = p + +#define READ_RGBA(rgba, _x, _y) \ + do { \ + GLushort p = *(GLushort *)(buf + (_x)*2 + (_y)*pitch); \ + rgba[0] = (p >> 8) & 0xf8; \ + rgba[1] = (p >> 3) & 0xfc; \ + rgba[2] = (p << 3) & 0xf8; \ + rgba[3] = 255; /* or 0? */ \ + } while(0) + +#define TAG(x) r128DD##x##565 +#include "spantmp.h" + + +/* Initialize the driver's span functions */ +void r128DDInitSpanFuncs(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + switch (r128ctx->r128Screen->depth) { + case 8: /* Color Index mode not supported */ + break; + case 16: + ctx->Driver.WriteRGBASpan = r128DDWriteRGBASpan565; + ctx->Driver.WriteRGBSpan = r128DDWriteRGBSpan565; + ctx->Driver.WriteMonoRGBASpan = r128DDWriteMonoRGBASpan565; + ctx->Driver.WriteRGBAPixels = r128DDWriteRGBAPixels565; + ctx->Driver.WriteMonoRGBAPixels = r128DDWriteMonoRGBAPixels565; + ctx->Driver.ReadRGBASpan = r128DDReadRGBASpan565; + ctx->Driver.ReadRGBAPixels = r128DDReadRGBAPixels565; + break; + case 15: /* FIXME */ + case 24: /* FIXME */ + case 32: /* FIXME */ + ctx->Driver.WriteRGBASpan = r128DDWriteRGBASpan; + ctx->Driver.WriteRGBSpan = r128DDWriteRGBSpan; + ctx->Driver.WriteMonoRGBASpan = r128DDWriteMonoRGBASpan; + ctx->Driver.WriteRGBAPixels = r128DDWriteRGBAPixels; + ctx->Driver.WriteMonoRGBAPixels = r128DDWriteMonoRGBAPixels; + ctx->Driver.ReadRGBASpan = r128DDReadRGBASpan; + ctx->Driver.ReadRGBAPixels = r128DDReadRGBAPixels; + break; + } + + ctx->Driver.WriteCI32Span = NULL; + ctx->Driver.WriteCI8Span = NULL; + ctx->Driver.WriteMonoCISpan = NULL; + ctx->Driver.WriteCI32Pixels = NULL; + ctx->Driver.WriteMonoCIPixels = NULL; + ctx->Driver.ReadCI32Span = NULL; + ctx->Driver.ReadCI32Pixels = NULL; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_span.h b/xc/lib/GL/mesa/src/drv/r128/r128_span.h new file mode 100644 index 000000000..9974afb35 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_span.h @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_SPAN_H_ +#define _R128_SPAN_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128DDInitSpanFuncs(GLcontext *ctx); + +#endif +#endif /* _R128_SPAN_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_state.c b/xc/lib/GL/mesa/src/drv/r128/r128_state.c new file mode 100644 index 000000000..950082f2c --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_state.c @@ -0,0 +1,1257 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_state.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_tris.h" +#include "r128_vb.h" +#include "r128_tex.h" + +CARD32 r128PackColor(GLuint d, + GLubyte r, GLubyte g, GLubyte b, GLubyte a) +{ + switch (d) { + case 8: + return (((r & 0xe0) >> 0) | + ((g & 0xe0) >> 3) | + ((b & 0xc0) >> 6) | + ((a & 0x00) >> 0)); + case 15: + return (((r & 0xf8) << 7) | + ((g & 0xf8) << 2) | + ((b & 0xf8) >> 3) | + ((a & 0x80) << 8)); + case 16: + return (((r & 0xf8) << 8) | + ((g & 0xfc) << 3) | + ((b & 0xf8) >> 3) | + ((a & 0x00) << 0)); + case 24: + return (((r & 0xff) << 16) | + ((g & 0xff) << 8) | + ((b & 0xff) >> 0) | + ((a & 0x00) << 0)); + case 32: + return (((r & 0xff) << 16) | + ((g & 0xff) << 8) | + ((b & 0xff) >> 0) | + ((a & 0xff) << 24)); + } + + return 0; +} + +#define INTERESTED (~(NEW_MODELVIEW | \ + NEW_PROJECTION | \ + NEW_TEXTURE_MATRIX | \ + NEW_USER_CLIP | \ + NEW_CLIENT_STATE | \ + NEW_TEXTURE_ENABLE)) + +static void r128DDUpdateState(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + if (ctx->NewState & INTERESTED) { + r128ChooseRenderState(ctx); + r128ChooseRasterSetupFunc(ctx); + } + + if (!r128ctx->Fallback) { + ctx->IndirectTriangles &= ~DD_SW_RASTERIZE; + ctx->IndirectTriangles |= r128ctx->IndirectTriangles; + + ctx->Driver.PointsFunc = r128ctx->PointsFunc; + ctx->Driver.LineFunc = r128ctx->LineFunc; + ctx->Driver.TriangleFunc = r128ctx->TriangleFunc; + ctx->Driver.QuadFunc = r128ctx->QuadFunc; + ctx->Driver.RectFunc = NULL; + } +} + +static void r128DDUpdateHWState(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + /* FIXME: state is being updated too often */ + if (r128ctx->dirty) + r128UpdateHWState(r128ctx); +} + +static void r128DDReducedPrimitiveChange(GLcontext *ctx, GLenum prim) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + /* FIXME: Also need to flush between tris and tristrips/fans when we + support them directly */ + R128_FLUSH_VB(r128ctx); +} + +static void r128DDClearColor(GLcontext *ctx, + GLubyte r, GLubyte g, GLubyte b, GLubyte a) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + r128ctx->ClearColor = r128PackColor(32, r, g, b, a); +} + +static void r128DDColor(GLcontext *ctx, + GLubyte r, GLubyte g, GLubyte b, GLubyte a) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + r128ctx->Color = r128PackColor(r128ctx->r128Screen->depth, r, g, b, a); +} + +static GLboolean r128DDSetDrawBuffer(GLcontext *ctx, GLenum mode) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + int x = r128ctx->driDrawable->x; + int y = r128ctx->driDrawable->y; + int found; + + r128ctx->Fallback &= ~R128_FALLBACK_DRAW_BUFFER; + + switch (mode) { + case GL_FRONT_LEFT: + r128ctx->drawX = r128ctx->r128Screen->fbX; + r128ctx->drawY = r128ctx->r128Screen->fbY; + found = GL_TRUE; + break; + case GL_BACK_LEFT: + r128ctx->drawX = r128ctx->r128Screen->backX; + r128ctx->drawY = r128ctx->r128Screen->backY; + found = GL_TRUE; + break; + default: + r128ctx->Fallback |= R128_FALLBACK_DRAW_BUFFER; + found = GL_FALSE; + break; + } + + x += r128ctx->drawX; + y += r128ctx->drawY; + +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.window_xy_offset = ((y << R128_WINDOW_Y_SHIFT) | + (x << R128_WINDOW_X_SHIFT)); + + /* Recalculate the Z buffer offset since we might be drawing to the + back buffer and window_xy_offset affects both color buffer and + depth drawing */ + r128ctx->regs.z_offset_c = ((r128ctx->r128Screen->depthX - + r128ctx->drawX) * + (r128ctx->r128Screen->bpp/8) + + (r128ctx->r128Screen->depthY - + r128ctx->drawY) * + r128ctx->r128Screen->fbStride); + + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_WIN_Z_POS; + return found; +} + +static void r128DDSetReadBuffer(GLcontext *ctx, + GLframebuffer *colorBuffer, + GLenum mode) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + r128ctx->Fallback &= ~R128_FALLBACK_READ_BUFFER; + + switch (mode) { + case GL_FRONT_LEFT: + r128ctx->readX = r128ctx->r128Screen->fbX; + r128ctx->readY = r128ctx->r128Screen->fbY; + break; + case GL_BACK_LEFT: + r128ctx->readX = r128ctx->r128Screen->backX; + r128ctx->readY = r128ctx->r128Screen->backY; + break; + default: + r128ctx->Fallback |= R128_FALLBACK_READ_BUFFER; + break; + } +} + +static GLboolean r128DDColorMask(GLcontext *ctx, + GLboolean r, GLboolean g, + GLboolean b, GLboolean a) +{ + /* FIXME: Implement this function. Make sure the fallbacks are + covered if they do not properly handle individual color channel + masking. */ + return GL_TRUE; +} + +static void r128DDAlphaFunc(GLcontext *ctx, GLenum func, GLclampf ref) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 a = r128ctx->regs.misc_3d_state_cntl_reg; + + a &= ~(R128_ALPHA_TEST_MASK | R128_REF_ALPHA_MASK); + a |= ctx->Color.AlphaRef & R128_REF_ALPHA_MASK; + + switch (func) { + case GL_NEVER: a |= R128_ALPHA_TEST_NEVER; break; + case GL_LESS: a |= R128_ALPHA_TEST_LESS; break; + case GL_LEQUAL: a |= R128_ALPHA_TEST_LESSEQUAL; break; + case GL_EQUAL: a |= R128_ALPHA_TEST_EQUAL; break; + case GL_GEQUAL: a |= R128_ALPHA_TEST_GREATEREQUAL; break; + case GL_GREATER: a |= R128_ALPHA_TEST_GREATER; break; + case GL_NOTEQUAL: a |= R128_ALPHA_TEST_NEQUAL; break; + case GL_ALWAYS: a |= R128_ALPHA_TEST_ALWAYS; + break; + default: + /* ERROR!!! */ + return; + } + + if (r128ctx->regs.misc_3d_state_cntl_reg != a) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.misc_3d_state_cntl_reg = a; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ALPHASTATE; + } +} + +static void r128DDBlendFunc(GLcontext *ctx, GLenum sfactor, GLenum dfactor) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 b = r128ctx->regs.misc_3d_state_cntl_reg; + + b &= ~(R128_ALPHA_BLEND_SRC_MASK | R128_ALPHA_BLEND_DST_MASK); + + switch (sfactor) { + case GL_ZERO: b |= R128_ALPHA_BLEND_SRC_ZERO; + break; + case GL_ONE: b |= R128_ALPHA_BLEND_SRC_ONE; + break; + case GL_DST_COLOR: b |= R128_ALPHA_BLEND_SRC_DESTCOLOR; + break; + case GL_ONE_MINUS_DST_COLOR: b |= R128_ALPHA_BLEND_SRC_INVDESTCOLOR; + break; + case GL_SRC_ALPHA: b |= R128_ALPHA_BLEND_SRC_SRCALPHA; + break; + case GL_ONE_MINUS_SRC_ALPHA: b |= R128_ALPHA_BLEND_SRC_INVSRCALPHA; + break; + case GL_DST_ALPHA: b |= R128_ALPHA_BLEND_SRC_DESTALPHA; + break; + case GL_ONE_MINUS_DST_ALPHA: b |= R128_ALPHA_BLEND_SRC_INVDESTALPHA; + break; + case GL_SRC_ALPHA_SATURATE: b |= R128_ALPHA_BLEND_SRC_SRCALPHASAT; + break; +#if 0 + /* FIXME: These are not supported directly by the Rage 128. + They could be emulated using something like the TexEnv + modes. */ + case GL_CONSTANT_COLOR: b |= 0; + break; + case GL_ONE_MINUS_CONSTANT_COLOR: b |= 0; + break; + case GL_CONSTANT_ALPHA: b |= 0; + break; + case GL_ONE_MINUS_CONSTANT_ALPHA: b |= 0; + break; +#endif + default: + /* ERROR!!! */ + return; + } + + switch (dfactor) { + case GL_ZERO: b |= R128_ALPHA_BLEND_DST_ZERO; + break; + case GL_ONE: b |= R128_ALPHA_BLEND_DST_ONE; + break; + case GL_SRC_COLOR: b |= R128_ALPHA_BLEND_DST_SRCCOLOR; + break; + case GL_ONE_MINUS_SRC_COLOR: b |= R128_ALPHA_BLEND_DST_INVSRCCOLOR; + break; + case GL_SRC_ALPHA: b |= R128_ALPHA_BLEND_DST_SRCALPHA; + break; + case GL_ONE_MINUS_SRC_ALPHA: b |= R128_ALPHA_BLEND_DST_INVSRCALPHA; + break; + case GL_DST_ALPHA: b |= R128_ALPHA_BLEND_DST_DESTALPHA; + break; + case GL_ONE_MINUS_DST_ALPHA: b |= R128_ALPHA_BLEND_DST_INVDESTALPHA; + break; +#if 0 + /* FIXME: These are not supported directly by the Rage 128. + They could be emulated using something like the TexEnv + modes. */ + case GL_CONSTANT_COLOR: b |= 0; + break; + case GL_ONE_MINUS_CONSTANT_COLOR: b |= 0; + break; + case GL_CONSTANT_ALPHA: b |= 0; + break; + case GL_ONE_MINUS_CONSTANT_ALPHA: b |= 0; + break; +#endif + default: + /* ERROR!!! */ + return; + } + + if (r128ctx->regs.misc_3d_state_cntl_reg != b) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.misc_3d_state_cntl_reg = b; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ALPHASTATE; + } +} + +static void r128DDBlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, + GLenum dfactorRGB, GLenum sfactorA, + GLenum dfactorA) +{ + if (sfactorRGB != sfactorA || dfactorRGB != dfactorA) { + /* ERROR!!! */ + return; + } + + r128DDBlendFunc(ctx, sfactorRGB, dfactorRGB); +} + +static void r128DDClearDepth(GLcontext *ctx, GLclampd d) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + switch (r128ctx->regs.z_sten_cntl_c & R128_Z_PIX_WIDTH_MASK) { + case R128_Z_PIX_WIDTH_16: r128ctx->ClearDepth = d * 0x0000ffff; break; + case R128_Z_PIX_WIDTH_24: r128ctx->ClearDepth = d * 0x00ffffff; break; + case R128_Z_PIX_WIDTH_32: r128ctx->ClearDepth = d * 0xffffffff; break; + default: return; + } +} + +static void r128DDCullFace(GLcontext *ctx, GLenum mode) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 f = r128ctx->regs.pm4_vc_fpu_setup; + + if (!ctx->Polygon.CullFlag) return; + + f &= ~(R128_BACKFACE_MASK | R128_FRONTFACE_MASK); + + switch (mode) { + case GL_FRONT: f |= R128_BACKFACE_SOLID; break; + case GL_BACK: f |= R128_FRONTFACE_SOLID; break; + case GL_FRONT_AND_BACK: break; + default: return; + } + + if (r128ctx->regs.pm4_vc_fpu_setup != f) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.pm4_vc_fpu_setup = f; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_SETUPSTATE; + } +} + +static void r128DDFrontFace(GLcontext *ctx, GLenum mode) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 f = r128ctx->regs.pm4_vc_fpu_setup; + + f &= ~R128_FRONT_DIR_MASK; + + switch (mode) { + case GL_CW: f |= R128_FRONT_DIR_CW; break; + case GL_CCW: f |= R128_FRONT_DIR_CCW; break; + default: return; + } + + if (r128ctx->regs.pm4_vc_fpu_setup != f) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.pm4_vc_fpu_setup = f; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_SETUPSTATE; + } +} + +static void r128DDDepthFunc(GLcontext *ctx, GLenum func) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 z = r128ctx->regs.z_sten_cntl_c; + + z &= ~R128_Z_TEST_MASK; + + switch(func) { + case GL_NEVER: z |= R128_Z_TEST_NEVER; break; + case GL_LESS: z |= R128_Z_TEST_LESS; break; + case GL_LEQUAL: z |= R128_Z_TEST_LESSEQUAL; break; + case GL_EQUAL: z |= R128_Z_TEST_EQUAL; break; + case GL_GEQUAL: z |= R128_Z_TEST_GREATEREQUAL; break; + case GL_GREATER: z |= R128_Z_TEST_GREATER; break; + case GL_NOTEQUAL: z |= R128_Z_TEST_NEQUAL; break; + case GL_ALWAYS: z |= R128_Z_TEST_ALWAYS; break; + default: return; + } + + if (r128ctx->regs.z_sten_cntl_c != z) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.z_sten_cntl_c = z; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ZSTENSTATE; + } +} + +static void r128DDDepthMask(GLcontext *ctx, GLboolean flag) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 t = r128ctx->regs.tex_cntl_c; + + if (flag) t |= R128_Z_WRITE_ENABLE; + else t &= ~R128_Z_WRITE_ENABLE; + + if (r128ctx->regs.tex_cntl_c != t) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.tex_cntl_c = t; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ENGINESTATE; + } +} + +static void r128DDEnable(GLcontext *ctx, GLenum cap, GLboolean state) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + CARD32 t = r128ctx->regs.tex_cntl_c; + CARD32 f = r128ctx->regs.pm4_vc_fpu_setup; + + switch (cap) { + case GL_ALPHA_TEST: + if (state) t |= R128_ALPHA_TEST_ENABLE; + else t &= ~R128_ALPHA_TEST_ENABLE; + break; + + case GL_AUTO_NORMAL: return; + + case GL_BLEND: + if (state) t |= R128_ALPHA_ENABLE; + else t &= ~R128_ALPHA_ENABLE; + break; + + case GL_CLIP_PLANE0: + case GL_CLIP_PLANE1: + case GL_CLIP_PLANE2: + case GL_CLIP_PLANE3: + case GL_CLIP_PLANE4: + case GL_CLIP_PLANE5: + case GL_COLOR_MATERIAL: return; + + case GL_CULL_FACE: + f &= ~(R128_BACKFACE_MASK | R128_FRONTFACE_MASK); + if (state) { + switch (ctx->Polygon.CullFaceMode) { + case GL_FRONT: f |= R128_BACKFACE_SOLID; break; + case GL_BACK: f |= R128_FRONTFACE_SOLID; break; + case GL_FRONT_AND_BACK: break; + default: return; + } + } else { + f |= R128_BACKFACE_SOLID | R128_FRONTFACE_SOLID; + } + break; + + case GL_DEPTH_TEST: + if (state) t |= R128_Z_ENABLE; + else t &= ~R128_Z_ENABLE; + break; + +#if 0 + /* FIXME */ + case GL_DITHER: return; + + /* FIXME */ + case GL_FOG: + if (state) t |= R128_FOG_ENABLE; + else t &= ~R128_FOG_ENABLE; + break; +#endif + + case GL_LIGHT0: + case GL_LIGHT1: + case GL_LIGHT2: + case GL_LIGHT3: + case GL_LIGHT4: + case GL_LIGHT5: + case GL_LIGHT6: + case GL_LIGHT7: + case GL_LIGHTING: + case GL_LINE_SMOOTH: + case GL_LINE_STIPPLE: + case GL_INDEX_LOGIC_OP: + case GL_COLOR_LOGIC_OP: + case GL_MAP1_COLOR_4: + case GL_MAP1_INDEX: + case GL_MAP1_NORMAL: + case GL_MAP1_TEXTURE_COORD_1: + case GL_MAP1_TEXTURE_COORD_2: + case GL_MAP1_TEXTURE_COORD_3: + case GL_MAP1_TEXTURE_COORD_4: + case GL_MAP1_VERTEX_3: + case GL_MAP1_VERTEX_4: + case GL_MAP2_COLOR_4: + case GL_MAP2_INDEX: + case GL_MAP2_NORMAL: + case GL_MAP2_TEXTURE_COORD_1: + case GL_MAP2_TEXTURE_COORD_2: + case GL_MAP2_TEXTURE_COORD_3: + case GL_MAP2_TEXTURE_COORD_4: + case GL_MAP2_VERTEX_3: + case GL_MAP2_VERTEX_4: + case GL_NORMALIZE: + case GL_POINT_SMOOTH: + case GL_POLYGON_SMOOTH: + case GL_POLYGON_STIPPLE: + case GL_POLYGON_OFFSET_POINT: + case GL_POLYGON_OFFSET_LINE: + case GL_POLYGON_OFFSET_FILL: +#if 0 + /* FIXME: Are there others in Mesa 3.3 that we need to add? */ + case GL_RESCALE_NORMAL_EXT: +#endif + case GL_SCISSOR_TEST: +#if 0 + /* FIXME: Are there others in Mesa 3.3 that we need to add? */ + case GL_SHARED_TEXTURE_PALETTE_EXT: +#endif + case GL_STENCIL_TEST: + case GL_TEXTURE_1D: return; + + case GL_TEXTURE_2D: + switch (ctx->Texture.CurrentUnit) { + case 0: + if (state) t |= R128_TEXMAP_ENABLE; + else t &= ~R128_TEXMAP_ENABLE; + break; + case 1: + if (state) t |= R128_SEC_TEXMAP_ENABLE; + else t &= ~R128_SEC_TEXMAP_ENABLE; + break; + default: + return; + } + r128ctx->dirty |= R128_UPDATE_TEXSTATE; + break; + + case GL_TEXTURE_3D: + case GL_TEXTURE_GEN_Q: + case GL_TEXTURE_GEN_R: + case GL_TEXTURE_GEN_S: + case GL_TEXTURE_GEN_T: return; + + /* Client state */ + case GL_VERTEX_ARRAY: + case GL_NORMAL_ARRAY: + case GL_COLOR_ARRAY: + case GL_INDEX_ARRAY: + case GL_TEXTURE_COORD_ARRAY: + case GL_EDGE_FLAG_ARRAY: return; + + default: return; + } + + if (r128ctx->regs.tex_cntl_c != t) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.tex_cntl_c = t; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ENGINESTATE; + } + if (r128ctx->regs.pm4_vc_fpu_setup != f) { +#if FLUSH_VB_ON_STATE_CHANGE + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.pm4_vc_fpu_setup = f; + + /* FIXME: Load into hardware now??? */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_SETUPSTATE; + } + +} + +static void r128DDScissor(GLcontext *ctx, + GLint x, GLint y, GLsizei w, GLsizei h) +{ + /* FIXME */ +} + +/* Initialize the driver's state functions */ +void r128DDInitStateFuncs(GLcontext *ctx) +{ + ctx->Driver.UpdateState = r128DDUpdateState; + + ctx->Driver.ClearIndex = NULL; + ctx->Driver.ClearColor = r128DDClearColor; + ctx->Driver.Index = NULL; + ctx->Driver.Color = r128DDColor; + ctx->Driver.SetDrawBuffer = r128DDSetDrawBuffer; + ctx->Driver.SetReadBuffer = r128DDSetReadBuffer; + + ctx->Driver.IndexMask = NULL; + ctx->Driver.ColorMask = r128DDColorMask; + ctx->Driver.LogicOp = NULL; + ctx->Driver.Dither = NULL; + + ctx->Driver.NearFar = NULL; + + ctx->Driver.RenderStart = r128DDUpdateHWState; + ctx->Driver.RenderFinish = NULL; + ctx->Driver.RasterSetup = NULL; + + ctx->Driver.RenderVBClippedTab = NULL; + ctx->Driver.RenderVBCulledTab = NULL; + ctx->Driver.RenderVBRawTab = NULL; + + ctx->Driver.ReducedPrimitiveChange = r128DDReducedPrimitiveChange; + ctx->Driver.MultipassFunc = NULL; + + ctx->Driver.AlphaFunc = r128DDAlphaFunc; + ctx->Driver.BlendEquation = NULL; + ctx->Driver.BlendFunc = r128DDBlendFunc; + ctx->Driver.BlendFuncSeparate = r128DDBlendFuncSeparate; + ctx->Driver.ClearDepth = r128DDClearDepth; + ctx->Driver.CullFace = r128DDCullFace; + ctx->Driver.FrontFace = r128DDFrontFace; + ctx->Driver.DepthFunc = r128DDDepthFunc; + ctx->Driver.DepthMask = r128DDDepthMask; + ctx->Driver.DepthRange = NULL; + ctx->Driver.Enable = r128DDEnable; + ctx->Driver.Fogfv = NULL; + ctx->Driver.Hint = NULL; + ctx->Driver.Lightfv = NULL; + ctx->Driver.LightModelfv = NULL; + ctx->Driver.PolygonMode = NULL; + ctx->Driver.Scissor = r128DDScissor; + ctx->Driver.ShadeModel = NULL; + ctx->Driver.ClearStencil = NULL; + ctx->Driver.StencilFunc = NULL; + ctx->Driver.StencilMask = NULL; + ctx->Driver.StencilOp = NULL; + ctx->Driver.Viewport = NULL; +} + +/* Initialize the context's hardware state */ +void r128DDInitState(r128ContextPtr r128ctx) +{ + int dst_bpp, depth_bpp, pitch, i; + CARD32 depthClear; + + pitch = r128ctx->r128Screen->fbStride / r128ctx->r128Screen->bpp; + + switch (r128ctx->r128Screen->bpp) { + case 8: + dst_bpp = R128_GMC_DST_8BPP_CI; + break; + case 16: + if (r128ctx->r128Screen->depth == 15) dst_bpp = R128_GMC_DST_15BPP; + else dst_bpp = R128_GMC_DST_16BPP; + break; + case 24: + dst_bpp = R128_GMC_DST_24BPP; + break; + case 32: + default: + dst_bpp = R128_GMC_DST_32BPP; + break; + } + + switch ( +#if 0 + /* FIXME: Figure out how to use 16bpp depth buffer in 32bpp mode */ + r128ctx->glCtx->Visual->DepthBits +#else + r128ctx->r128Screen->bpp +#endif + ) { + case 16: + depthClear = 0x0000ffff; + depth_bpp = R128_Z_PIX_WIDTH_16; + break; + case 24: + depthClear = 0x00ffffff; + depth_bpp = R128_Z_PIX_WIDTH_24; + break; + case 32: + depthClear = 0xffffffff; + depth_bpp = R128_Z_PIX_WIDTH_32; + break; + default: + /* FIXME: This is an error */ + depthClear = 0x00000000; + depth_bpp = R128_Z_PIX_WIDTH_16; + break; + } + + r128ctx->dirty = R128_CLEAN; + r128ctx->needClip = GL_FALSE; + + r128ctx->RenderIndex = R128_FALLBACK_BIT; + r128ctx->PointsFunc = NULL; + r128ctx->LineFunc = NULL; + r128ctx->TriangleFunc = NULL; + r128ctx->QuadFunc = NULL; + + r128ctx->IndirectTriangles = 0; + r128ctx->Fallback = 0; + + if (r128ctx->glCtx->Visual->DBflag) { + r128ctx->drawX = r128ctx->r128Screen->backX; + r128ctx->drawY = r128ctx->r128Screen->backY; + r128ctx->readX = r128ctx->r128Screen->backX; + r128ctx->readY = r128ctx->r128Screen->backY; + } else { + r128ctx->drawX = r128ctx->r128Screen->fbX; + r128ctx->drawY = r128ctx->r128Screen->fbY; + r128ctx->readX = r128ctx->r128Screen->fbX; + r128ctx->readY = r128ctx->r128Screen->fbY; + } + + r128ctx->ClearColor = 0x00000000; + r128ctx->ClearDepth = depthClear; + + r128ctx->regs.scale_3d_cntl = + R128_SCALE_DITHER_ERR_DIFF | + R128_TEX_CACHE_SIZE_FULL | + R128_DITHER_INIT_RESET | + R128_SCALE_3D_TEXMAP_SHADE | + R128_SCALE_PIX_REPLICATE | + R128_ALPHA_COMB_ADD_CLAMP | + R128_FOG_TABLE | + R128_ALPHA_BLEND_SRC_ONE | + R128_ALPHA_BLEND_DST_ZERO | + R128_ALPHA_TEST_ALWAYS | + R128_COMPOSITE_SHADOW_CMP_EQUAL | + R128_TEX_MAP_ALPHA_IN_TEXTURE | + R128_TEX_CACHE_LINE_SIZE_8QW; + + r128ctx->regs.dst_pitch_offset_c = pitch << R128_PITCH_SHIFT; + + r128ctx->regs.dp_gui_master_cntl = + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_DST_CLIPPING | + R128_GMC_BRUSH_SOLID_COLOR | + dst_bpp | + R128_GMC_SRC_DATATYPE_COLOR | + R128_GMC_BYTE_MSB_TO_LSB | + R128_GMC_CONVERSION_TEMP_6500 | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_3D_FCN_EN | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_AUX_CLIP_DIS | + R128_GMC_WR_MSK_DIS; + + r128ctx->regs.sc_top_left_c = 0x00000000; + r128ctx->regs.sc_bottom_right_c = 0x1fff1fff; + r128ctx->regs.z_offset_c = (r128ctx->r128Screen->depthX * + (r128ctx->r128Screen->bpp/8) + + r128ctx->r128Screen->depthY * + r128ctx->r128Screen->fbStride); + r128ctx->regs.z_pitch_c = pitch; + + r128ctx->regs.z_sten_cntl_c = + depth_bpp | + R128_Z_TEST_LESS | + R128_STENCIL_TEST_ALWAYS | + R128_STENCIL_S_FAIL_KEEP | + R128_STENCIL_ZPASS_KEEP | + R128_STENCIL_ZFAIL_KEEP; + + r128ctx->regs.tex_cntl_c = + R128_Z_WRITE_ENABLE | + R128_SHADE_ENABLE | + R128_ALPHA_IN_TEX_COMPLETE_A | + R128_LIGHT_DIS | + R128_ALPHA_LIGHT_DIS | + R128_TEX_CACHE_FLUSH | + (0x0f << R128_LOD_BIAS_SHIFT); + + r128ctx->regs.misc_3d_state_cntl_reg = + R128_MISC_SCALE_3D_TEXMAP_SHADE | + R128_MISC_SCALE_PIX_REPLICATE | + R128_ALPHA_COMB_ADD_CLAMP | + R128_FOG_TABLE | + R128_ALPHA_BLEND_SRC_ONE | + R128_ALPHA_BLEND_DST_ZERO | + R128_ALPHA_TEST_ALWAYS; + + r128ctx->regs.texture_clr_cmp_clr_c = 0x00000000; + r128ctx->regs.texture_clr_cmp_msk_c = 0xffffffff; + r128ctx->regs.fog_color_c = 0x00808080; + + r128ctx->regs.prim_tex_cntl_c = + R128_MIN_BLEND_NEAREST | + R128_MAG_BLEND_NEAREST | + R128_MIP_MAP_DISABLE | + R128_TEX_CLAMP_S_WRAP | + R128_TEX_CLAMP_T_WRAP; + + r128ctx->regs.prim_texture_combine_cntl_c = + R128_COMB_MODULATE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA; + + r128ctx->regs.tex_size_pitch_c = + (0 << R128_TEX_PITCH_SHIFT) | + (0 << R128_TEX_SIZE_SHIFT) | + (0 << R128_TEX_HEIGHT_SHIFT) | + (0 << R128_TEX_MIN_SIZE_SHIFT) | + (0 << R128_SEC_TEX_PITCH_SHIFT) | + (0 << R128_SEC_TEX_SIZE_SHIFT) | + (0 << R128_SEC_TEX_HEIGHT_SHIFT) | + (0 << R128_SEC_TEX_MIN_SIZE_SHIFT); + + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.prim_tex_offset[i] = 0x00000000; + + r128ctx->regs.sec_tex_cntl_c = + R128_SEC_SELECT_PRIM_ST; + + r128ctx->regs.sec_tex_combine_cntl_c = + R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_DIS | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA; + + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.sec_tex_offset[i] = 0x00000000; + + r128ctx->regs.constant_color_c = 0x00ffffff; + r128ctx->regs.prim_texture_border_color_c = 0x00ffffff; + r128ctx->regs.sec_texture_border_color_c = 0x00ffffff; + r128ctx->regs.sten_ref_mask_c = 0xffff0000; + r128ctx->regs.plane_3d_mask_c = 0xffffffff; + + r128ctx->regs.setup_cntl = + R128_COLOR_GOURAUD | + R128_PRIM_TYPE_TRI | +#if 1 + /* FIXME: Let r128 multiply? */ + R128_TEXTURE_ST_MULT_W | +#else + /* FIXME: Or, pre multiply? */ + R128_TEXTURE_ST_DIRECT | +#endif + R128_STARTING_VERTEX_1 | + R128_ENDING_VERTEX_3 | + R128_SU_POLY_LINE_NOT_LAST | + R128_SUB_PIX_4BITS; + + r128ctx->regs.pm4_vc_fpu_setup = + R128_FRONT_DIR_CCW | + R128_BACKFACE_SOLID | + R128_FRONTFACE_SOLID | + R128_FPU_COLOR_GOURAUD | + R128_FPU_SUB_PIX_4BITS | + R128_FPU_MODE_3D | + R128_TRAP_BITS_DISABLE | + R128_XFACTOR_2 | + R128_YFACTOR_2 | + R128_FLAT_SHADE_VERTEX_OGL | + R128_FPU_ROUND_TRUNCATE | + R128_WM_SEL_8DW; + + r128ctx->regs.fog_3d_table_start = 0x00000000; + r128ctx->regs.fog_3d_table_end = 0xffffffff; + r128ctx->regs.fog_3d_table_density = 0x00000000; + + r128ctx->regs.window_xy_offset = 0x00000000; + + r128ctx->regs.dp_write_mask = 0xffffffff; + + r128ctx->regs.pc_gui_ctlstat = R128_PC_FLUSH_GUI; + + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ALL_DIRTY; +} + +/* Load the current context's state into the hardware */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128LoadContext(r128ContextPtr r128ctx) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + int i; + int tex_size_pitch_done = GL_FALSE; + +#if 0 + r128ctx->dirty_context = R128_ALL_DIRTY; +#endif + +#if 1 + /* FIXME: Why do these need to be updated even when they don't change? */ + r128ctx->dirty_context |= (R128_CTX_MISC | + R128_CTX_ENGINESTATE | + R128_CTX_ALPHASTATE); +#endif + +#if 1 + /* FIXME: Is this _really_ needed? */ + if (r128ctx->dirty_context) R128CCEWaitForIdle(r128ctx->r128Screen); +#endif + +#if !FLUSH_VB_ON_STATE_CHANGE + /* FIXME: It might make sense to do this here instead of flushing + immediately in each state setting routine. */ + /* FIXME: Is this _really_ necessary? It slows down rendering, and + it seems like state changes shouldn't take effect until after the + VB has completed rendering. */ + if (r128ctx->dirty_context) R128_FLUSH_VB(r128ctx); +#endif + + if (r128ctx->dirty_context & R128_CTX_MISC) { + R128CCE_WAIT_LOCKED(3); + R128CCE1(R128_CCE_PACKET1, R128_SCALE_3D_CNTL, R128_DP_WRITE_MASK); + R128CCE(r128ctx->regs.scale_3d_cntl); + R128CCE(r128ctx->regs.dp_write_mask); + + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_DST_PITCH_OFFSET_C, 1); + R128CCE(r128ctx->regs.dst_pitch_offset_c); + R128CCE(r128ctx->regs.dp_gui_master_cntl); + + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_TEXTURE_CLR_CMP_CLR_C, 1); + R128CCE(r128ctx->regs.texture_clr_cmp_clr_c); + R128CCE(r128ctx->regs.texture_clr_cmp_msk_c); + + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_STEN_REF_MASK_C, 1); + R128CCE(r128ctx->regs.sten_ref_mask_c); + R128CCE(r128ctx->regs.plane_3d_mask_c); + } + + if (r128ctx->dirty_context & R128_CTX_ENGINESTATE) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_CNTL_C, 0); + R128CCE(r128ctx->regs.tex_cntl_c); + } + + if (r128ctx->dirty_context & R128_CTX_TEX0STATE) { + R128CCE_WAIT_LOCKED(4+R128_TEX_MAXLEVELS); + R128CCE0(R128_CCE_PACKET0, R128_PRIM_TEX_CNTL_C, 2+R128_TEX_MAXLEVELS); + R128CCE(r128ctx->regs.prim_tex_cntl_c); + R128CCE(r128ctx->regs.prim_texture_combine_cntl_c); + R128CCE(r128ctx->regs.tex_size_pitch_c); + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + R128CCE(r128ctx->regs.prim_tex_offset[i]); + + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_PRIM_TEXTURE_BORDER_COLOR_C, 0); + R128CCE(r128ctx->regs.prim_texture_border_color_c); + + tex_size_pitch_done = GL_TRUE; + } + + if (r128ctx->dirty_context & R128_CTX_TEX1STATE) { + if (!tex_size_pitch_done) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_TEX_SIZE_PITCH_C, 0); + R128CCE(r128ctx->regs.tex_size_pitch_c); + } + + R128CCE_WAIT_LOCKED(3+R128_TEX_MAXLEVELS); + R128CCE0(R128_CCE_PACKET0, R128_SEC_TEX_CNTL_C, 1+R128_TEX_MAXLEVELS); + R128CCE(r128ctx->regs.sec_tex_cntl_c); + R128CCE(r128ctx->regs.sec_tex_combine_cntl_c); + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + R128CCE(r128ctx->regs.sec_tex_offset[i]); + + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_SEC_TEXTURE_BORDER_COLOR_C, 0); + R128CCE(r128ctx->regs.sec_texture_border_color_c); + + } + + if (r128ctx->dirty_context & R128_CTX_TEXENVSTATE) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_CONSTANT_COLOR_C, 0); + R128CCE(r128ctx->regs.constant_color_c); + } + + if (r128ctx->dirty_context & R128_CTX_FOGSTATE) { + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_FOG_3D_TABLE_START, 1); + R128CCE(r128ctx->regs.fog_3d_table_start); + R128CCE(r128ctx->regs.fog_3d_table_end); + + R128CCE_WAIT_LOCKED(3); + R128CCE1(R128_CCE_PACKET1, + R128_FOG_COLOR_C, R128_FOG_3D_TABLE_DENSITY); + R128CCE(r128ctx->regs.fog_color_c); + R128CCE(r128ctx->regs.fog_3d_table_density); + } + + if (r128ctx->dirty_context & R128_CTX_ZSTENSTATE) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_Z_STEN_CNTL_C, 0); + R128CCE(r128ctx->regs.z_sten_cntl_c); + } + + if (r128ctx->dirty_context & R128_CTX_SCISSORS) { + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_SC_TOP_LEFT_C, 1); + R128CCE(r128ctx->regs.sc_top_left_c); + R128CCE(r128ctx->regs.sc_bottom_right_c); + } + + if (r128ctx->dirty_context & (R128_CTX_ALPHASTATE | + R128_CTX_FOGSTATE)) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_MISC_3D_STATE_CNTL_REG, 0); + R128CCE(r128ctx->regs.misc_3d_state_cntl_reg); + } + + if (r128ctx->dirty_context & R128_CTX_SETUPSTATE) { + R128CCE_WAIT_LOCKED(3); + R128CCE1(R128_CCE_PACKET1, R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP); + R128CCE(r128ctx->regs.setup_cntl); + R128CCE(r128ctx->regs.pm4_vc_fpu_setup); + } + + if (r128ctx->dirty_context & R128_CTX_WIN_Z_POS) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_WINDOW_XY_OFFSET, 0); + R128CCE(r128ctx->regs.window_xy_offset); + + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_Z_OFFSET_C, 1); + R128CCE(r128ctx->regs.z_offset_c); + R128CCE(r128ctx->regs.z_pitch_c); + } + + if (r128ctx->dirty_context & R128_CTX_FLUSH_PIX_CACHE) { + R128CCE_WAIT_LOCKED(2); + R128CCE0(R128_CCE_PACKET0, R128_PC_GUI_CTLSTAT, 0); + R128CCE(r128ctx->regs.pc_gui_ctlstat); + } + + R128CCE_END_LOCKED(); + + /* Turn off the texture cache flushing */ + r128ctx->regs.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; + + /* Turn off the pixel cache flushing */ + r128ctx->regs.pc_gui_ctlstat &= ~R128_PC_FLUSH_ALL; + + r128ctx->dirty_context = R128_CTX_CLEAN; +} + +/* Set a hardware clip rect for drawing to the current color buffer */ +/* NOTE: This function is only called while holding the hardware lock */ +void r128SetClipRect(r128ContextPtr r128ctx, XF86DRIClipRectPtr pc) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + + /* FIXME: Use the Rage 128's multiple clip rects */ + R128CCE_WAIT_LOCKED(3); + R128CCE0(R128_CCE_PACKET0, R128_SC_TOP_LEFT_C, 1); + R128CCE(((pc->y1 + r128ctx->drawY) << 16)|(pc->x1 + r128ctx->drawX)); + R128CCE(((pc->y2-1 + r128ctx->drawY) << 16)|(pc->x2-1 + r128ctx->drawX)); + R128CCE_END_LOCKED(); +} + +/* Update the driver's notion of the window position */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UpdateWindowPosition(r128ContextPtr r128ctx) +{ + int x = r128ctx->driDrawable->x + r128ctx->drawX; + int y = r128ctx->driDrawable->y + r128ctx->drawY; + +#if 0 + /* FIXME: This happens during a lock, but is it _really_ needed? */ + R128_FLUSH_VB(r128ctx); +#endif + r128ctx->regs.window_xy_offset = ((y << R128_WINDOW_Y_SHIFT) | + (x << R128_WINDOW_X_SHIFT)); + + /* Recalculate the Z buffer offset since we might be drawing to the + back buffer and window_xy_offset affects both color buffer and + depth drawing */ + r128ctx->regs.z_offset_c = ((r128ctx->r128Screen->depthX - + r128ctx->drawX) * + (r128ctx->r128Screen->bpp/8) + + (r128ctx->r128Screen->depthY - + r128ctx->drawY) * + r128ctx->r128Screen->fbStride); + + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_WIN_Z_POS; + + r128ctx->needClip = (r128ctx->driDrawable->numClipRects > 1); +} + +/* Update the hardware state */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UpdateHWStateLocked(r128ContextPtr r128ctx) +{ + r128ScreenPtr r128Screen = r128ctx->r128Screen; + + if (r128ctx->dirty & R128_REQUIRE_QUIESCENCE) + R128WaitForIdle(r128Screen); + + /* Update any state that might have changed recently */ + + /* Update the clip rects */ + if (r128ctx->dirty & R128_UPDATE_WINPOS) + r128UpdateWindowPosition(r128ctx); + + /* Update texture state and then upload the images */ + /* Note: Texture images can only be updated after the state has been set */ + if (r128ctx->dirty & R128_UPDATE_TEXSTATE) + r128UpdateTextureState(r128ctx); + if (r128ctx->dirty & R128_UPDATE_TEX0IMAGES) + r128UploadTexImages(r128ctx, r128ctx->CurrentTexObj[0]); + if (r128ctx->dirty & R128_UPDATE_TEX1IMAGES) + r128UploadTexImages(r128ctx, r128ctx->CurrentTexObj[1]); + + /* Load the state into the hardware */ + /* Note: This must be done after all other state has been set */ + if (r128ctx->dirty & R128_UPDATE_CONTEXT) + r128LoadContext(r128ctx); + + r128ctx->dirty = R128_CLEAN; +} + +/* Update the hardware state */ +void r128UpdateHWState(r128ContextPtr r128ctx) +{ + LOCK_HARDWARE(r128ctx); + r128UpdateHWStateLocked(r128ctx); + UNLOCK_HARDWARE(r128ctx); +} + +/* Update the driver's state */ +/* NOTE: This function is only called while holding the hardware lock */ +void r128UpdateState(r128ContextPtr r128ctx, int winMoved) +{ + if (r128ctx->SAREA->ctxOwner != r128ctx->driContext->hHWContext) { + r128ctx->SAREA->ctxOwner = r128ctx->driContext->hHWContext; + r128ctx->dirty |= R128_ALL_DIRTY; + } + + if (r128ctx->SAREA->texAge != r128ctx->lastTexAge) { +#if USE_AGP_TEXTURES + int sz = 1 << r128ctx->r128Screen->log2AGPTexGran; +#else + int sz = 1 << r128ctx->r128Screen->log2TexGran; +#endif + int nr = 0; + int idx; + + for (idx = r128ctx->SAREA->texList[R128_NR_TEX_REGIONS].prev; + idx != R128_NR_TEX_REGIONS && nr < R128_NR_TEX_REGIONS; + idx = r128ctx->SAREA->texList[idx].prev, nr++) { + + /* If switching texturing schemes, then the SAREA might not + have been properly cleared, so we need to reset the + global texture LRU. */ +#if USE_AGP_TEXTURES + if (idx * sz > r128ctx->r128Screen->agpTexSize) { +#else + if (idx * sz > r128ctx->r128Screen->textureSize) { +#endif + nr = R128_NR_TEX_REGIONS; + break; + } + + if (r128ctx->SAREA->texList[idx].age > r128ctx->lastTexAge) + r128TexturesGone(r128ctx, idx * sz, sz, + r128ctx->SAREA->texList[idx].in_use); + } + + if (nr == R128_NR_TEX_REGIONS) { +#if USE_AGP_TEXTURES + r128TexturesGone(r128ctx, 0, r128ctx->r128Screen->agpTexSize, 0); +#else + r128TexturesGone(r128ctx, 0, r128ctx->r128Screen->textureSize, 0); +#endif + r128ResetGlobalLRU(r128ctx); + } + + r128ctx->dirty |= R128_UPDATE_TEX0IMAGES; + r128ctx->dirty |= R128_UPDATE_TEX1IMAGES; + r128ctx->lastTexAge = r128ctx->SAREA->texAge; + } + + if (winMoved) { /* FIXME??: handle window moves */ + r128ctx->dirty |= R128_UPDATE_WINPOS; + } + + if (r128ctx->dirty) r128UpdateHWStateLocked(r128ctx); +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_state.h b/xc/lib/GL/mesa/src/drv/r128/r128_state.h new file mode 100644 index 000000000..570d38f8e --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_state.h @@ -0,0 +1,51 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_STATE_H_ +#define _R128_STATE_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128DDInitState(r128ContextPtr r128ctx); +extern void r128DDInitStateFuncs(GLcontext *ctx); + +extern void r128UpdateState(r128ContextPtr r128ctx, int winMoved); +extern void r128UpdateHWState(r128ContextPtr r128ctx); + +extern void r128SetClipRect(r128ContextPtr r128ctx, XF86DRIClipRectPtr pc); +extern CARD32 r128PackColor(GLuint d, + GLubyte r, GLubyte g, GLubyte b, GLubyte a); + +#endif +#endif /* _R128_STATE_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_swap.c b/xc/lib/GL/mesa/src/drv/r128/r128_swap.c new file mode 100644 index 000000000..7f934586c --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_swap.c @@ -0,0 +1,110 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_vb.h" +#include "r128_swap.h" + +/* Copy the back color buffer to the front color buffer */ +void r128SwapBuffers(r128ContextPtr r128ctx) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; + int nc = dPriv->numClipRects; + XF86DRIClipRectPtr c = dPriv->pClipRects; + int dst_bpp; + + if (r128ctx->SWonly) { + /* FIXME: Provide software fallback for this case?? */ + } + + switch (r128ctx->r128Screen->bpp) { + case 8: + dst_bpp = R128_GMC_DST_8BPP_CI; + break; + case 16: + if (r128ctx->r128Screen->depth == 15) dst_bpp = R128_GMC_DST_15BPP; + else dst_bpp = R128_GMC_DST_16BPP; + break; + case 24: + dst_bpp = R128_GMC_DST_24BPP; + break; + case 32: + default: + dst_bpp = R128_GMC_DST_32BPP; + break; + } + + /* Flush any outstanding vertex buffers */ + R128_FLUSH_VB(r128ctx); + + LOCK_HARDWARE(r128ctx); + + /* Cycle through the clip rects */ + while (nc--) { + int fx = c[nc].x1; + int fy = c[nc].y1; + int fw = c[nc].x2 - fx; + int fh = c[nc].y2 - fy; + int bx = fx + r128ctx->r128Screen->backX; + int by = fy + r128ctx->r128Screen->backY; + + fx += r128ctx->r128Screen->fbX; + fy += r128ctx->r128Screen->fbY; + + R128CCE_WAIT_LOCKED(5); + R128CCE3(R128_CCE_PACKET3_CNTL_BITBLT_MULTI, 3); + R128CCE(R128_GMC_BRUSH_NONE + | R128_GMC_SRC_DATATYPE_COLOR + | R128_DP_SRC_SOURCE_MEMORY + | dst_bpp + | R128_ROP3_S); + R128CCE((bx << 16) | by); + R128CCE((fx << 16) | fy); + R128CCE((fw << 16) | fh); + } + + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ALL_DIRTY; + + R128CCE_END_LOCKED(); + + UNLOCK_HARDWARE(r128ctx); +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_swap.h b/xc/lib/GL/mesa/src/drv/r128/r128_swap.h new file mode 100644 index 000000000..32851041c --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_swap.h @@ -0,0 +1,43 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_SWAP_H_ +#define _R128_SWAP_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128SwapBuffers(r128ContextPtr r128ctx); + +#endif +#endif /* _R128_SWAP_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_tex.c b/xc/lib/GL/mesa/src/drv/r128/r128_tex.c new file mode 100644 index 000000000..b61f9cdc1 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_tex.c @@ -0,0 +1,1186 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_state.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_vb.h" +#include "r128_tex.h" + +#include "mmath.h" +#include "simple_list.h" + +static void r128SetTexWrap(r128TexObjPtr t, GLenum srwap, GLenum twrap); +static void r128SetTexFilter(r128TexObjPtr t, GLenum minf, GLenum magf); +static void r128SetTexBorderColor(r128TexObjPtr t, GLubyte c[4]); + +/* Allocate and initialize hardware state associated with texture `t' */ +/* NOTE: This function is only called while holding the hardware lock */ +static r128TexObjPtr r128CreateTexObj(r128ContextPtr r128ctx, + struct gl_texture_object *tObj) +{ + r128TexObjPtr t; + struct gl_texture_image *image; + CARD32 texFormat; + int log2Pitch, log2Height, log2Size, log2MinSize; + int pitch, totalSize, width; + int i; + + image = tObj->Image[0]; + if (!image) return NULL; /* ERROR!!! */ + + t = (r128TexObjPtr)calloc(1,sizeof(*t)); + if (!t) return NULL; /* ERROR!!! */ + + for (i = 1, log2Height = 0; i < image->Height; i *= 2) log2Height++; + for (i = 1, log2Pitch = 0; i < image->Width; i *= 2) log2Pitch++; + if (image->Width > image->Height) log2Size = log2Pitch; + else log2Size = log2Height; + + pitch = image->Width; + t->internFormat = image->IntFormat; + + switch (image->Format) { + case GL_LUMINANCE: + case GL_ALPHA: + case GL_RGB: + if (r128ctx->r128Screen->bpp == 16 && + (t->internFormat == GL_RGB || t->internFormat == 3)) + t->internFormat = GL_RGB5; + + switch (t->internFormat) { + case GL_RGB5: pitch *= 2; texFormat = R128_DATATYPE_RGB565; break; + case 3: + case GL_RGB: +#if USE_RGB8_TEXTURES + case GL_RGB8: pitch *= 3; texFormat = R128_DATATYPE_RGB888; break; +#else + case GL_RGB8: pitch *= 4; texFormat = R128_DATATYPE_ARGB8888; break; +#endif + default: + /* Format not supported */ + free(t); + return NULL; + } + break; + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_RGBA: + if (r128ctx->r128Screen->bpp == 16 && + (t->internFormat == GL_RGBA || t->internFormat == 4)) + t->internFormat = GL_RGBA4; + + switch (t->internFormat) { + case GL_RGB5_A1: pitch *= 2; texFormat = R128_DATATYPE_ARGB1555; break; + case GL_RGBA4: pitch *= 2; texFormat = R128_DATATYPE_ARGB4444; break; + case 4: + case GL_RGBA: + case GL_RGBA8: pitch *= 4; texFormat = R128_DATATYPE_ARGB8888; break; + default: + /* Format not supported */ + free(t); + return NULL; + } + break; + case GL_COLOR_INDEX: + switch (t->internFormat) { + case 1: + case GL_COLOR_INDEX: + case GL_COLOR_INDEX8_EXT: texFormat = R128_DATATYPE_CI8; break; + default: + /* Format not supported */ + free(t); + return NULL; + } + break; + default: + /* ERROR!!! */ + free(t); + return NULL; + } + + t->dirty_images = 0; + t->bound = 0; + t->tObj = tObj; + + t->memBlock = NULL; + t->bufAddr = NULL; + + totalSize = 0; + width = image->Width; + for (i = 0; i <= log2Size && tObj->Image[i]; i++) { + t->image[i].offset = totalSize; + t->image[i].width = width; + t->dirty_images |= 1 << i; + totalSize += tObj->Image[i]->Height * pitch; + pitch /= 2; + width /= 2; + } + log2MinSize = log2Size - i + 1; + + t->totalSize = totalSize; + + t->regs.tex_cntl = texFormat; + t->regs.size_pitch = ((log2Pitch << R128_TEX_PITCH_SHIFT) | + (log2Size << R128_TEX_SIZE_SHIFT) | + (log2Height << R128_TEX_HEIGHT_SHIFT) | + (log2MinSize << R128_TEX_MIN_SIZE_SHIFT)); + t->regs.border_color = 0x00000000; + + if (log2MinSize == log2Size || + log2MinSize != 0) + t->regs.tex_cntl |= R128_MIP_MAP_DISABLE; + + r128SetTexWrap(t, tObj->WrapS, tObj->WrapT); + r128SetTexFilter(t, tObj->MinFilter, tObj->MagFilter); + r128SetTexBorderColor(t, tObj->BorderColor); + + tObj->DriverData = t; + /* r128ctx->dirty |= R128_UPDATE_CONTEXT; */ + + make_empty_list(t); + + return t; +} + +/* Destroy hardware state associated with texture `t' */ +/* NOTE: This function can be called while holding the hardware lock and + while not holding the lock*/ +void r128DestroyTexObj(r128ContextPtr r128ctx, r128TexObjPtr t) +{ + if (!t) return; + + if (t->memBlock) { + mmFreeMem(t->memBlock); + t->memBlock = NULL; + } + + if (t->tObj) t->tObj->DriverData = NULL; + if (t->bound) r128ctx->CurrentTexObj[t->bound-1] = NULL; + + remove_from_list(t); + free(t); +} + +/* Keep track of swapped out texture objects */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128SwapOutTexObj(r128ContextPtr r128ctx, r128TexObjPtr t) +{ + if (t->memBlock) { + mmFreeMem(t->memBlock); + t->memBlock = NULL; + } + + t->dirty_images = ~0; + move_to_tail(&r128ctx->SwappedOut, t); +} + +/* Upload the texture image associated with texture `t' at level `level' + at the address relative to `start'. */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UploadTexLevel(r128TexObjPtr t, int level, int start) +{ + struct gl_texture_image *image; + int i, j, width; + + if (level < 0 || level > R128_TEX_MAXLEVELS) return; + if (!(image = t->tObj->Image[level])) return; + + width = t->image[level].width; + + /* FIXME: Use HOSTDATA_BLT (type 3 packet) for texture uploads */ + /* FIXME: Add the other texture formats that we support here */ + switch (t->internFormat) { + case GL_RGB5: + { + CARD16 *dst = (CARD16 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + dst[i] = (((src[0] & 0xf8) << 8) | + ((src[1] & 0xfc) << 3) | + ((src[2] & 0xf8) >> 3)); + src += 3; + } + dst += width; + } + break; + } + case 3: + case GL_RGB: + case GL_RGB8: + { +#if USE_RGB8_TEXTURES + CARD8 *dst = (CARD8 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + *dst++ = src[0]; + *dst++ = src[1]; + *dst++ = src[2]; + src += 3; + } + } +#else + CARD32 *dst = (CARD32 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + dst[i] = ((src[0] << 16) | + (src[1] << 8) | + (src[2] << 0) | + (0xff << 24)); + src += 3; + } + dst += width; + } +#endif + break; + } + case GL_RGB5_A1: + { + CARD16 *dst = (CARD16 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + dst[i] = (((src[0] & 0xf8) << 7) | + ((src[1] & 0xf8) << 2) | + ((src[2] & 0xf8) >> 3) | + ((src[3] & 0x80) << 8)); + src += 4; + } + dst += width; + } + break; + } + case GL_RGBA4: + { + CARD16 *dst = (CARD16 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + dst[i] = (((src[0] & 0xf0) << 4) | + ((src[1] & 0xf0) << 0) | + ((src[2] & 0xf0) >> 4) | + ((src[3] & 0xf0) << 8)); + src += 4; + } + dst += width; + } + break; + } + case 4: + case GL_RGBA: + case GL_RGBA8: + { + CARD32 *dst = (CARD32 *)(t->image[level].offset + t->bufAddr + start); + CARD8 *src = (CARD8 *)image->Data; + + for (j = 0; j < image->Height; j++) { + for (i = 0; i < width; i++) { + dst[i] = ((src[0] << 16) | + (src[1] << 8) | + (src[2] << 0) | + (src[3] << 24)); + src += 4; + } + dst += width; + } + break; + } + default: + return; + } +} + +/* Reset the global texture LRU */ +/* NOTE: This function is only called while holding the hardware lock */ +void r128ResetGlobalLRU(r128ContextPtr r128ctx) +{ + R128TexRegion *list = r128ctx->SAREA->texList; +#if USE_AGP_TEXTURES + int sz = 1 << r128ctx->r128Screen->log2AGPTexGran; +#else + int sz = 1 << r128ctx->r128Screen->log2TexGran; +#endif + int i; + + /* + * (Re)initialize the global circular LRU list. The last element in + * the array (R128_NR_TEX_REGIONS) is the sentinal. Keeping it at + * the end of the array allows it to be addressed rationally when + * looking up objects at a particular location in texture memory. + */ + +#if USE_AGP_TEXTURES + for (i = 0; (i+1) * sz <= r128ctx->r128Screen->agpTexSize; i++) { +#else + for (i = 0; (i+1) * sz <= r128ctx->r128Screen->textureSize; i++) { +#endif + list[i].prev = i-1; + list[i].next = i+1; + list[i].age = 0; + } + + i--; + list[0].prev = R128_NR_TEX_REGIONS; + list[i].prev = i-1; + list[i].next = R128_NR_TEX_REGIONS; + list[R128_NR_TEX_REGIONS].prev = i; + list[R128_NR_TEX_REGIONS].next = 0; + r128ctx->SAREA->texAge = 0; +} + +/* Update the local and glock texture LRUs */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UpdateTexLRU(r128ContextPtr r128ctx, r128TexObjPtr t) +{ + R128TexRegion *list = r128ctx->SAREA->texList; +#if USE_AGP_TEXTURES + int log2sz = r128ctx->r128Screen->log2AGPTexGran; +#else + int log2sz = r128ctx->r128Screen->log2TexGran; +#endif + + int start = t->memBlock->ofs >> log2sz; + int end = (t->memBlock->ofs + t->memBlock->size - 1) >> log2sz; + int i; + + r128ctx->lastTexAge = ++r128ctx->SAREA->texAge; + + /* Update our local LRU */ + move_to_head(&r128ctx->TexObjList, t); + + /* Update the global LRU */ + for (i = start ; i <= end ; i++) { + list[i].in_use = 1; + list[i].age = r128ctx->lastTexAge; + + /* remove_from_list(i) */ + list[(CARD32)list[i].next].prev = list[i].prev; + list[(CARD32)list[i].prev].next = list[i].next; + + /* insert_at_head(list, i) */ + list[i].prev = R128_NR_TEX_REGIONS; + list[i].next = list[R128_NR_TEX_REGIONS].next; + list[(CARD32)list[R128_NR_TEX_REGIONS].next].prev = i; + list[R128_NR_TEX_REGIONS].next = i; + } +} + +/* Update our notion of what textures have been changed since we last + held the lock. This pertains to both our local textures and the + textures belonging to other clients. Keep track of other client's + textures by pushing a placeholder texture onto the LRU list -- these + are denoted by (tObj == NULL). */ +/* NOTE: This function is only called while holding the hardware lock */ +void r128TexturesGone(r128ContextPtr r128ctx, + int offset, int size, int in_use) +{ + r128TexObjPtr t, tmp; + + foreach_s (t, tmp, &r128ctx->TexObjList) { + if (t->memBlock->ofs >= offset + size || + t->memBlock->ofs + t->memBlock->size <= offset) + continue; + + /* It overlaps - kick it out. Need to hold onto the currently + bound objects, however. */ + if (t->bound) r128SwapOutTexObj(r128ctx, t); + else r128DestroyTexObj(r128ctx, t); + } + + if (in_use) { + t = (r128TexObjPtr) calloc(1,sizeof(*t)); + if (!t) return; + + t->memBlock = mmAllocMem(r128ctx->texHeap, size, 0, offset); + insert_at_head(&r128ctx->TexObjList, t); + } +} + +/* Upload the texture images associated with texture `t'. This might + require removing our own and/or other client's texture objects to + make room for these images. */ +/* NOTE: This function is only called while holding the hardware lock */ +int r128UploadTexImages(r128ContextPtr r128ctx, r128TexObjPtr t) +{ + int i; + int minLevel; + int maxLevel; + + if (!t) return 0; + + /* Do we need to eject LRU texture objects? */ + if (!t->memBlock) { + while (1) { + /* Allocate a memory block on a 4k boundary (1<<12 == 4096) */ + t->memBlock = mmAllocMem(r128ctx->texHeap, t->totalSize, 12, 0); + if (t->memBlock) break; + + if (r128ctx->TexObjList.prev->bound) { + fprintf(stderr, + "r128UploadTexImages: ran into bound texture\n"); + return -1; + } + if (r128ctx->TexObjList.prev == &(r128ctx->TexObjList)) { + fprintf(stderr, + "r128UploadTexImages: upload texture failure, sz=%d\n", + t->totalSize); + return -1; + } + + r128DestroyTexObj(r128ctx, r128ctx->TexObjList.prev); + } + + /* FIXME: Allow both local and AGP textures to co-exist. */ +#if USE_AGP_TEXTURES + t->bufAddr = (unsigned char *)r128ctx->r128Screen->agpTexStart; +#else + t->bufAddr = (unsigned char *)(r128ctx->r128Screen->textureY * + r128ctx->r128Screen->fbStride + + r128ctx->r128Screen->textureX * + (r128ctx->r128Screen->bpp/8)); +#endif + t->bufAddr += t->memBlock->ofs; + + maxLevel = ((t->regs.size_pitch & R128_TEX_SIZE_MASK) >> + R128_TEX_SIZE_SHIFT); + minLevel = ((t->regs.size_pitch & R128_TEX_MIN_SIZE_MASK) >> + R128_TEX_MIN_SIZE_SHIFT); + + /* Update the hardware's texture image addresses */ + switch (t->bound) { + case 1: + if (t->regs.tex_cntl & R128_MIP_MAP_DISABLE) { + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.prim_tex_offset[i] = (CARD32)t->bufAddr; + } else { + for (i = maxLevel; i >= minLevel; i--) + r128ctx->regs.prim_tex_offset[i] = + t->image[maxLevel-i].offset + (CARD32)t->bufAddr; + } +#if USE_AGP_TEXTURES + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.prim_tex_offset[i] |= 0x02000000; +#endif + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_TEX0STATE; + break; + case 2: + if (t->regs.tex_cntl & R128_MIP_MAP_DISABLE) { + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.sec_tex_offset[i] = (CARD32)t->bufAddr; + } else { + for (i = maxLevel; i >= minLevel; i--) + r128ctx->regs.sec_tex_offset[i] = + t->image[maxLevel-i].offset + (CARD32)t->bufAddr; + } +#if USE_AGP_TEXTURES + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.sec_tex_offset[i] |= 0x02000000; +#endif + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_TEX1STATE; + break; + default: + return -1; + } + } + + /* Let the world know we've used this memory recently */ + r128UpdateTexLRU(r128ctx, t); + + /* Wait for texturing to complete */ + R128CCEWaitForIdle(r128ctx->r128Screen); + + /* Upload any images that are new */ + if (t->dirty_images) { + int num_levels = (((t->regs.size_pitch & R128_TEX_SIZE_MASK) >> + R128_TEX_SIZE_SHIFT) - + ((t->regs.size_pitch & R128_TEX_MIN_SIZE_MASK) >> + R128_TEX_MIN_SIZE_SHIFT)); + + for (i = 0; i <= num_levels; i++) + if (t->dirty_images & (1<<i)) { +#if USE_AGP_TEXTURES + r128UploadTexLevel(t, i, (int)r128ctx->r128Screen->agp); +#else + r128UploadTexLevel(t, i, (int)r128ctx->r128Screen->fb); +#endif + } + + r128ctx->regs.tex_cntl_c |= R128_TEX_CACHE_FLUSH; + + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_ENGINESTATE; + + /* FIXME: r128ctx->regs.pc_gui_ctlstat = R128_PC_FLUSH_GUI; */ + /* FIXME: r128ctx->dirty_context |= R128_CTX_FLUSH_PIX_CACHE; */ + } + + t->dirty_images = 0; + return 0; +} + +/* Update the hardware state for texture unit 0 */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UpdateTex0State(r128ContextPtr r128ctx) +{ + GLcontext *ctx = r128ctx->glCtx; + r128TexObjPtr t; + struct gl_texture_object *tObj; + int i; + CARD32 tex_size_pitch, tex_combine_cntl; + + /* Only update the hardware texture state if the texture is current, + complete and enabled. */ + if (!(tObj = ctx->Texture.Unit[0].Current)) return; + if (tObj != ctx->Texture.Unit[0].CurrentD[2]) return; + if (!tObj->Complete) return; + if (!(ctx->Texture.Enabled & 0x0f)) return; + + /* If this is the first time the texture has been used, then create + a new texture object for it. */ + t = tObj->DriverData; + if (!t) t = r128CreateTexObj(r128ctx, tObj); + if (!t) return; + + /* Force any texture images to be loaded into the hardware */ + if (t->dirty_images) r128ctx->dirty |= R128_UPDATE_TEX0IMAGES; + + /* Bind texture to texture 0 unit */ + r128ctx->CurrentTexObj[0] = t; + t->bound = 1; + + if (t->memBlock) r128UpdateTexLRU(r128ctx, t); + + /* Set the texture environment state */ + /* FIXME: This only works for GL_RGB and GL_RGBA right now */ + /* FIXME: Handle GL_ALPHA, GL_LIMINANCE{_ALPHA} and GL_INTENSITY */ + switch (ctx->Texture.Unit[0].EnvMode) { + case GL_REPLACE: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_DIS | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_MODULATE: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_MODULATE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_MODULATE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_MODULATE | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_DECAL: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_BLEND_TEXTURE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_BLEND: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_BLEND_PREV | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_BLEND_PREV | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_INT_COLOR | + R128_COMB_ALPHA_MODULATE | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_INT_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + default: + return; + } + + tex_size_pitch = r128ctx->regs.tex_size_pitch_c; + tex_size_pitch &= ~R128_TEX_SIZE_PITCH_MASK; + tex_size_pitch |= t->regs.size_pitch << R128_TEX_SIZE_PITCH_SHIFT; + + /* Set the primary texture state in r128ctx->regs */ + r128ctx->regs.prim_tex_cntl_c = t->regs.tex_cntl; + r128ctx->regs.prim_texture_combine_cntl_c = tex_combine_cntl; + r128ctx->regs.tex_size_pitch_c = tex_size_pitch; + r128ctx->regs.prim_texture_border_color_c = t->regs.border_color; + if (t->regs.tex_cntl & R128_MIP_MAP_DISABLE) { + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.prim_tex_offset[i] = (CARD32)t->bufAddr; + } else { + int maxLevel = ((t->regs.size_pitch & R128_TEX_SIZE_MASK) >> + R128_TEX_SIZE_SHIFT); + int minLevel = ((t->regs.size_pitch & R128_TEX_MIN_SIZE_MASK) >> + R128_TEX_MIN_SIZE_SHIFT); + for (i = maxLevel; i >= minLevel; i--) + r128ctx->regs.prim_tex_offset[i] = + t->image[maxLevel-i].offset + (CARD32)t->bufAddr; + } +#if USE_AGP_TEXTURES + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.prim_tex_offset[i] |= 0x02000000; +#endif + + /* Force loading the new state into the hardware */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_TEX0STATE; +} + +/* Update the hardware state for texture unit 1 */ +/* NOTE: This function is only called while holding the hardware lock */ +static void r128UpdateTex1State(r128ContextPtr r128ctx) +{ + GLcontext *ctx = r128ctx->glCtx; + r128TexObjPtr t; + struct gl_texture_object *tObj; + int i; + CARD32 tex_size_pitch, tex_combine_cntl, tex_cntl; + + /* Only update the hardware texture state if the texture is current, + complete and enabled. */ + if (!(tObj = ctx->Texture.Unit[1].Current)) return; + if (tObj != ctx->Texture.Unit[1].CurrentD[2]) return; + if (!tObj->Complete) return; + if (!(ctx->Texture.Enabled & 0xf0)) return; + + /* If this is the first time the texture has been used, then create + a new texture object for it. */ + t = tObj->DriverData; + if (!t) t = r128CreateTexObj(r128ctx, tObj); + if (!t) return; + + /* Force any texture images to be loaded into the hardware */ + if (t->dirty_images) r128ctx->dirty |= R128_UPDATE_TEX1IMAGES; + + /* Bind texture to texture 1 unit */ + r128ctx->CurrentTexObj[1] = t; + t->bound = 2; + + if (t->memBlock) r128UpdateTexLRU(r128ctx, t); + + /* Set the texture environment state */ + /* FIXME: This only works for GL_RBG and GL_RGBA right now */ + /* FIXME: Handle GL_ALPHA, GL_LIMINANCE{_ALPHA} and GL_INTENSITY */ + /* FIXME: Handle when no Tex0: i.e., !(ctx->Texture.Enabled & 0x0f) */ + switch (ctx->Texture.Unit[1].EnvMode) { + case GL_REPLACE: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_DIS | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_MODULATE: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_MODULATE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_MODULATE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_MODULATE | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_DECAL: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_DIS | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_BLEND_TEXTURE | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + case GL_BLEND: + switch (tObj->Image[0]->Format) { + case GL_RGB: + tex_combine_cntl = (R128_COMB_BLEND_PREV | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_COPY_INP | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_RGBA: + tex_combine_cntl = (R128_COMB_BLEND_PREV | + R128_COLOR_FACTOR_TEX | + R128_INPUT_FACTOR_PREV_COLOR | + R128_COMB_ALPHA_MODULATE | + R128_ALPHA_FACTOR_TEX_ALPHA | + R128_INP_FACTOR_A_PREV_ALPHA); + break; + case GL_LUMINANCE: + case GL_ALPHA: + case GL_LUMINANCE_ALPHA: + case GL_INTENSITY: + case GL_COLOR_INDEX: + default: + return; + } + break; + default: + return; + } + + tex_size_pitch = r128ctx->regs.tex_size_pitch_c; + tex_size_pitch &= ~R128_SEC_TEX_SIZE_PITCH_MASK; + tex_size_pitch |= t->regs.size_pitch << R128_SEC_TEX_SIZE_PITCH_SHIFT; + + tex_cntl = t->regs.tex_cntl | R128_SEC_SELECT_SEC_ST; + + /* Set the secondary texture state in r128ctx->regs */ + r128ctx->regs.sec_tex_cntl_c = tex_cntl; + r128ctx->regs.sec_tex_combine_cntl_c = tex_combine_cntl; + r128ctx->regs.tex_size_pitch_c = tex_size_pitch; + r128ctx->regs.sec_texture_border_color_c = t->regs.border_color; + if (t->regs.tex_cntl & R128_MIP_MAP_DISABLE) { + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.sec_tex_offset[i] = (CARD32)t->bufAddr; + } else { + int maxLevel = ((t->regs.size_pitch & R128_TEX_SIZE_MASK) >> + R128_TEX_SIZE_SHIFT); + int minLevel = ((t->regs.size_pitch & R128_TEX_MIN_SIZE_MASK) >> + R128_TEX_MIN_SIZE_SHIFT); + for (i = maxLevel; i >= minLevel; i--) + r128ctx->regs.sec_tex_offset[i] = + t->image[maxLevel-i].offset + (CARD32)t->bufAddr; + } +#if USE_AGP_TEXTURES + for (i = 0; i < R128_TEX_MAXLEVELS; i++) + r128ctx->regs.sec_tex_offset[i] |= 0x02000000; +#endif + + /* Force loading the new state into the hardware */ + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_TEX1STATE; +} + +/* Update the hardware texture state */ +/* NOTE: This function is only called while holding the hardware lock */ +void r128UpdateTextureState(r128ContextPtr r128ctx) +{ + /* Unbind any currently bound textures */ + if (r128ctx->CurrentTexObj[0]) r128ctx->CurrentTexObj[0]->bound = 0; + if (r128ctx->CurrentTexObj[1]) r128ctx->CurrentTexObj[1]->bound = 0; + r128ctx->CurrentTexObj[0] = NULL; + r128ctx->CurrentTexObj[1] = NULL; + + /* Update the texture unit 0/1 state */ + r128UpdateTex0State(r128ctx); + r128UpdateTex1State(r128ctx); +} + +/* Set the texture wrap mode */ +static void r128SetTexWrap(r128TexObjPtr t, GLenum swrap, GLenum twrap) +{ + t->regs.tex_cntl &= ~(R128_TEX_CLAMP_S_MASK | R128_TEX_CLAMP_T_MASK); + + switch (swrap) { + case GL_CLAMP: t->regs.tex_cntl |= R128_TEX_CLAMP_S_CLAMP; break; + case GL_REPEAT: t->regs.tex_cntl |= R128_TEX_CLAMP_S_WRAP; break; + default: /* ERROR!! */ return; + } + + switch (twrap) { + case GL_CLAMP: t->regs.tex_cntl |= R128_TEX_CLAMP_T_CLAMP; break; + case GL_REPEAT: t->regs.tex_cntl |= R128_TEX_CLAMP_T_WRAP; break; + default: /* ERROR!! */ return; + } +} + +/* Set the texture filter mode */ +static void r128SetTexFilter(r128TexObjPtr t, GLenum minf, GLenum magf) +{ + t->regs.tex_cntl &= ~(R128_MIN_BLEND_MASK | R128_MAG_BLEND_MASK); + + switch (minf) { + case GL_NEAREST: + t->regs.tex_cntl |= R128_MIN_BLEND_NEAREST; + break; + case GL_LINEAR: + t->regs.tex_cntl |= R128_MIN_BLEND_LINEAR; + break; + case GL_NEAREST_MIPMAP_NEAREST: + t->regs.tex_cntl |= R128_MIN_BLEND_MIPNEAREST; + break; + case GL_LINEAR_MIPMAP_NEAREST: + t->regs.tex_cntl |= R128_MIN_BLEND_LINEARMIPNEAREST; + break; + case GL_NEAREST_MIPMAP_LINEAR: + t->regs.tex_cntl |= R128_MIN_BLEND_MIPLINEAR; + break; + case GL_LINEAR_MIPMAP_LINEAR: + t->regs.tex_cntl |= R128_MIN_BLEND_LINEARMIPLINEAR; + break; + default: /* ERROR!! */ return; + } + + switch (magf) { + case GL_NEAREST: + t->regs.tex_cntl |= R128_MAG_BLEND_NEAREST; + break; + case GL_LINEAR: + t->regs.tex_cntl |= R128_MAG_BLEND_LINEAR; + break; + } +} + +/* Set the texture border color */ +static void r128SetTexBorderColor(r128TexObjPtr t, GLubyte c[4]) +{ + t->regs.border_color = r128PackColor(32, c[0], c[1], c[2], c[3]); +} + +/* Set the texture environment state */ +static void r128DDTexEnv(GLcontext *ctx, GLenum pname, const GLfloat *param) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + struct gl_texture_unit *texUnit; + GLubyte c[4]; + CARD32 col; + + switch (pname) { + case GL_TEXTURE_ENV_MODE: + /* TexEnv modes are handled in UpdateTextureState */ + R128_FLUSH_VB(r128ctx); + r128ctx->dirty |= R128_UPDATE_TEXSTATE; + break; + case GL_TEXTURE_ENV_COLOR: + texUnit = &ctx->Texture.Unit[ctx->Texture.CurrentUnit]; + FLOAT_RGBA_TO_UBYTE_RGBA(texUnit->EnvColor, c); + col = r128PackColor(32, c[0], c[1], c[2], c[3]); + if (r128ctx->regs.constant_color_c != col) { + R128_FLUSH_VB(r128ctx); + r128ctx->regs.constant_color_c = col; + r128ctx->dirty |= R128_UPDATE_CONTEXT; + r128ctx->dirty_context |= R128_CTX_TEXENVSTATE; + } + break; + default: + return; + } +} + +/* Upload a new texture image */ +static void r128DDTexImage(GLcontext *ctx, GLenum target, + struct gl_texture_object *tObj, GLint level, + GLint internalFormat, + const struct gl_texture_image *image) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128TexObjPtr t; + + if (target != GL_TEXTURE_2D) return; + if (level >= R128_TEX_MAXLEVELS) return; + + t = (r128TexObjPtr)tObj->DriverData; + if (t) { + if (t->bound) R128_FLUSH_VB(r128ctx); + + /* Destroy the old texture, and upload a new one. The actual + uploading of the texture image occurs in the UploadTexLevel + function. */ + r128DestroyTexObj(r128ctx, t); + r128ctx->dirty |= R128_UPDATE_TEXSTATE; + } +} + +/* Upload a new texture sub-image */ +static void r128DDTexSubImage(GLcontext *ctx, GLenum target, + struct gl_texture_object *tObj, GLint level, + GLint xoffset, GLint yoffset, + GLsizei width, GLsizei height, + GLint internalFormat, + const struct gl_texture_image *image) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128TexObjPtr t; + + if (target != GL_TEXTURE_2D) return; + if (level >= R128_TEX_MAXLEVELS) return; + + t = (r128TexObjPtr)tObj->DriverData; + if (t) { + if (t->bound) R128_FLUSH_VB(r128ctx); + + /* Destroy the old texture, and upload a new one. The actual + uploading of the texture image occurs in the UploadTexLevel + function. */ + r128DestroyTexObj(r128ctx, t); + tObj->DriverData = NULL; + r128ctx->dirty |= R128_UPDATE_TEXSTATE; + } +} + +/* Set the texture parameter state */ +static void r128DDTexParameter(GLcontext *ctx, GLenum target, + struct gl_texture_object *tObj, + GLenum pname, const GLfloat *params) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128TexObjPtr t = (r128TexObjPtr)tObj->DriverData; + + if (!t) return; + if (target != GL_TEXTURE_2D) return; + + switch (pname) { + case GL_TEXTURE_MIN_FILTER: + case GL_TEXTURE_MAG_FILTER: + if (t->bound) R128_FLUSH_VB(r128ctx); + + r128SetTexFilter(t, tObj->MinFilter, tObj->MagFilter); + break; + + case GL_TEXTURE_WRAP_S: + case GL_TEXTURE_WRAP_T: + if (t->bound) R128_FLUSH_VB(r128ctx); + + r128SetTexWrap(t, tObj->WrapS, tObj->WrapT); + break; + + case GL_TEXTURE_BORDER_COLOR: + if (t->bound) R128_FLUSH_VB(r128ctx); + + r128SetTexBorderColor(t, tObj->BorderColor); + break; + + default: + return; + } + + r128ctx->dirty |= R128_UPDATE_TEXSTATE; +} + +/* Bind a texture to the currently active texture unit */ +static void r128DDBindTexture(GLcontext *ctx, GLenum target, + struct gl_texture_object *tObj) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + + R128_FLUSH_VB(r128ctx); + + /* Unbind the old texture */ + if (r128ctx->CurrentTexObj[ctx->Texture.CurrentUnit]) { + r128ctx->CurrentTexObj[ctx->Texture.CurrentUnit]->bound = 0; + r128ctx->CurrentTexObj[ctx->Texture.CurrentUnit] = NULL; + } + + /* The actualy binding occurs in the Tex[01]UpdateState function */ + r128ctx->dirty |= R128_UPDATE_TEXSTATE; +} + +/* Remove texture from AGP/local texture memory */ +static void r128DDDeleteTexture(GLcontext *ctx, + struct gl_texture_object *tObj) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128TexObjPtr t = (r128TexObjPtr)tObj->DriverData; + + if (t) { + if (t->bound) { + R128_FLUSH_VB(r128ctx); + + r128ctx->CurrentTexObj[t->bound-1] = 0; + r128ctx->dirty |= R128_UPDATE_TEXSTATE; + } + + r128DestroyTexObj(r128ctx, t); + tObj->DriverData = NULL; + } +} + +/* Determine if a texture is currently residing in either AGP/local + texture memory */ +static GLboolean r128DDIsTextureResident(GLcontext *ctx, + struct gl_texture_object *tObj) +{ + r128TexObjPtr t = (r128TexObjPtr)tObj->DriverData; + + return t && t->memBlock; +} + +/* Initialize the driver's texture functions */ +void r128DDInitTextureFuncs(GLcontext *ctx) +{ + ctx->Driver.TexEnv = r128DDTexEnv; + ctx->Driver.TexImage = r128DDTexImage; + ctx->Driver.TexSubImage = r128DDTexSubImage; + ctx->Driver.TexParameter = r128DDTexParameter; + ctx->Driver.BindTexture = r128DDBindTexture; + ctx->Driver.DeleteTexture = r128DDDeleteTexture; + ctx->Driver.UpdateTexturePalette = NULL; + ctx->Driver.UseGlobalTexturePalette = NULL; + ctx->Driver.ActiveTexture = NULL; + ctx->Driver.IsTextureResident = r128DDIsTextureResident; + ctx->Driver.PrioritizeTexture = NULL; +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_tex.h b/xc/lib/GL/mesa/src/drv/r128/r128_tex.h new file mode 100644 index 000000000..ff12f0a0d --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_tex.h @@ -0,0 +1,50 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_TEX_H_ +#define _R128_TEX_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void r128ResetGlobalLRU(r128ContextPtr r128ctx); +extern void r128TexturesGone(r128ContextPtr r128ctx, + int offset, int size, int in_use); +extern int r128UploadTexImages(r128ContextPtr r128ctx, r128TexObjPtr t); +extern void r128UpdateTextureState(r128ContextPtr r128ctx); +extern void r128DestroyTexObj(r128ContextPtr r128ctx, r128TexObjPtr t); + +extern void r128DDInitTextureFuncs(GLcontext *ctx); + +#endif +#endif /* _R128_TEX_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_texobj.h b/xc/lib/GL/mesa/src/drv/r128/r128_texobj.h new file mode 100644 index 000000000..6b94d90d5 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_texobj.h @@ -0,0 +1,81 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_TEXOBJ_H_ +#define _R128_TEXOBJ_H_ + +#include "mm.h" + +#define R128_TEX_MAXLEVELS 11 + +/* Setup registers for each texture */ +typedef struct { + CARD32 tex_cntl; + CARD32 size_pitch; + CARD32 border_color; +} r128TextureRegs; + +/* Individual texture image information */ +typedef struct { + int offset; /* Offset into locally shared texture space (i.e., + relative to bufAddr (below) */ + int width; /* Width of texture image */ +} r128TexImage; + +typedef struct r128_tex_obj r128TexObj, *r128TexObjPtr; + +/* Texture object in locally shared texture space */ +struct r128_tex_obj { + r128TexObjPtr next, prev; + + struct gl_texture_object *tObj; /* Mesa texture object */ + + PMemBlock memBlock; /* Memory block containing texture */ + unsigned char *bufAddr; /* Offset to start of locally + shared texture block */ + + CARD32 dirty_images; /* Flags for whether or not + images need to be uploaded to + local or AGP texture space */ + int bound; /* Texture unit currently bound to */ + r128TexImage image[R128_TEX_MAXLEVELS]; /* Image data for all + mipmap levels */ + int totalSize; /* Total size of the texture + including all mipmap levels */ + int internFormat; /* Internal format used to store + texture on card */ + r128TextureRegs regs; /* Setup regs for texture */ +}; + +#endif /* _R128_TEXOBJ_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_tris.c b/xc/lib/GL/mesa/src/drv/r128/r128_tris.c new file mode 100644 index 000000000..48e6cef09 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_tris.c @@ -0,0 +1,234 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_vb.h" +#include "r128_tris.h" +#include "r128_state.h" + +static triangle_func tri_tab[0x40]; /* only 0x20 actually used */ +static quad_func quad_tab[0x40]; /* only 0x20 actually used */ +static line_func line_tab[0x40]; /* less than 0x20 used */ +static points_func points_tab[0x40]; /* less than 0x20 used */ + +/* Draw a triangle from the vertices in the vertex buffer */ +void r128DrawTriangle(r128ContextPtr r128ctx, + r128_vertex *v0, + r128_vertex *v1, + r128_vertex *v2) +{ +#if USE_VERTEX_BUFFERS + r128_vertex *vbptr = r128CCEAllocVBSpace(r128ctx, 3); + + *vbptr++ = *v0; + *vbptr++ = *v1; + *vbptr++ = *v2; +#else + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + + BEGIN_CLIP_LOOP(r128ctx); + +#if USE_RHW2 + R128CCE_WAIT_LOCKED(36); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_PRIM, 34); +#else + R128CCE_WAIT_LOCKED(33); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_PRIM, 31); +#endif + R128CCE(R128_FULL_VERTEX_FORMAT); + R128CCE(R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST | + R128_CCE_VC_CNTL_PRIM_WALK_RING | + (3 << R128_CCE_VC_CNTL_NUM_SHIFT)); + + R128CCE_SEND_VERTEX(v0); + R128CCE_SEND_VERTEX(v1); + R128CCE_SEND_VERTEX(v2); + + R128CCE_END_LOCKED(); + + END_CLIP_LOOP(r128ctx); +#endif +} + +/* Draw a line from the vertices in the vertex buffer */ +void r128DrawLine(r128ContextPtr r128ctx, + r128_vertex *tmp0, r128_vertex *tmp1, + float width) +{ +} + +/* Draw a point from the vertices in the vertex buffer */ +void r128DrawPoint(r128ContextPtr r128ctx, + r128_vertex *tmp, float sz) +{ +} + +#define R128_COLOR(to, from) \ +do { \ + (to)[0] = (from)[2]; \ + (to)[1] = (from)[1]; \ + (to)[2] = (from)[0]; \ + (to)[3] = (from)[3]; \ +} while (0) + +#define IND (0) +#define TAG(x) x +#include "r128_tritmp.h" + +#define IND (R128_FLAT_BIT) +#define TAG(x) x##_flat +#include "r128_tritmp.h" + +#define IND (R128_OFFSET_BIT) +#define TAG(x) x##_offset +#include "r128_tritmp.h" + +#define IND (R128_OFFSET_BIT | R128_FLAT_BIT) +#define TAG(x) x##_offset_flat +#include "r128_tritmp.h" + +#define IND (R128_TWOSIDE_BIT) +#define TAG(x) x##_twoside +#include "r128_tritmp.h" + +#define IND (R128_TWOSIDE_BIT | R128_FLAT_BIT) +#define TAG(x) x##_twoside_flat +#include "r128_tritmp.h" + +#define IND (R128_TWOSIDE_BIT | R128_OFFSET_BIT) +#define TAG(x) x##_twoside_offset +#include "r128_tritmp.h" + +#define IND (R128_TWOSIDE_BIT | R128_OFFSET_BIT | R128_FLAT_BIT) +#define TAG(x) x##_twoside_offset_flat +#include "r128_tritmp.h" + +/* Initialize the table of points, line and triangle drawing functions */ +void r128TriangleFuncsInit(void) +{ + init(); + init_flat(); + init_offset(); + init_offset_flat(); + init_twoside(); + init_twoside_flat(); + init_twoside_offset(); + init_twoside_offset_flat(); +} + +/* Setup the Point, Line, Triangle and Quad functions based on the + current rendering state. Wherever possible, use the hardware to + render the primitive. Otherwise, fallback to software rendering. */ +void r128ChooseRenderState(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + GLuint flags = ctx->TriangleCaps; + + if (r128ctx->SWonly) { + r128ctx->IndirectTriangles = DD_SW_RASTERIZE; + r128ctx->PointsFunc = NULL; + r128ctx->LineFunc = NULL; + r128ctx->TriangleFunc = NULL; + r128ctx->QuadFunc = NULL; + return; + } else { + r128ctx->IndirectTriangles = 0; + } + + if (flags) { + CARD32 index = 0; + CARD32 shared = 0; + CARD32 fallback = R128_FALLBACK_BIT; + + if (r128ctx->SWfallbackDisable) fallback = 0; /* No fallbacks */ + if (r128ctx->SWonly) shared = fallback; /* Everything's a fallback */ + + if (flags & DD_FLATSHADE) shared |= R128_FLAT_BIT; + if (flags & DD_MULTIDRAW) shared |= fallback; + if (flags & DD_SELECT) shared |= R128_FALLBACK_BIT; + if (flags & DD_FEEDBACK) shared |= R128_FALLBACK_BIT; + + /* Setup PointFunc */ + index = shared; + if (flags & DD_POINT_SMOOTH) index |= fallback; + if (flags & DD_POINT_ATTEN) index |= fallback; + + r128ctx->RenderIndex = index; + r128ctx->PointsFunc = points_tab[index]; + if (index & R128_FALLBACK_BIT) + r128ctx->IndirectTriangles |= DD_POINT_SW_RASTERIZE; + + /* Setup LineFunc */ + index = shared; + if (flags & DD_LINE_SMOOTH) index |= fallback; + if (flags & DD_LINE_STIPPLE) index |= fallback; + + r128ctx->RenderIndex |= index; + r128ctx->LineFunc = line_tab[index]; + if (index & R128_FALLBACK_BIT) + r128ctx->IndirectTriangles |= DD_LINE_SW_RASTERIZE; + + /* Setup TriangleFunc and QuadFunc */ + index = shared; + if (flags & DD_TRI_SMOOTH) index |= fallback; +#if 1 + if (flags & DD_TRI_OFFSET) index |= fallback; + if (flags & DD_TRI_LIGHT_TWOSIDE) index |= fallback; +#else + if (flags & DD_TRI_OFFSET) index |= R128_OFFSET_BIT; + if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R128_TWOSIDE_BIT; +#endif + if (flags & DD_TRI_UNFILLED) index |= fallback; + if (flags & DD_TRI_STIPPLE) index |= fallback; + + r128ctx->RenderIndex |= index; + r128ctx->TriangleFunc = tri_tab[index]; + r128ctx->QuadFunc = quad_tab[index]; + if (index & R128_FALLBACK_BIT) + r128ctx->IndirectTriangles |= (DD_TRI_SW_RASTERIZE | + DD_QUAD_SW_RASTERIZE); + } else if (r128ctx->RenderIndex) { + r128ctx->RenderIndex = 0; + r128ctx->PointsFunc = points_tab[0]; + r128ctx->LineFunc = line_tab[0]; + r128ctx->TriangleFunc = tri_tab[0]; + r128ctx->QuadFunc = quad_tab[0]; + } +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_tris.h b/xc/lib/GL/mesa/src/drv/r128/r128_tris.h new file mode 100644 index 000000000..91f30d80b --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_tris.h @@ -0,0 +1,66 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_TRIS_H_ +#define _R128_TRIS_H_ + +#ifdef GLX_DIRECT_RENDERING + +#include "r128_vb.h" + +#define R128_ANTIALIAS_BIT 0x00 /* ignored for now, no fallback */ +#define R128_FLAT_BIT 0x01 +#define R128_OFFSET_BIT 0x02 +#define R128_TWOSIDE_BIT 0x04 +#define R128_NODRAW_BIT 0x08 +#define R128_FALLBACK_BIT 0x10 +#define R128_FEEDBACK_BIT 0x20 +#define R128_SELECT_BIT 0x40 +#define R128_POINT_PARAM_BIT 0x80 /* not needed? */ + +extern void r128DrawTriangle(r128ContextPtr r128ctx, + r128_vertex *v0, + r128_vertex *v1, + r128_vertex *v2); +extern void r128DrawLine(r128ContextPtr r128ctx, + r128_vertex *tmp0, r128_vertex *tmp1, + float width); +extern void r128DrawPoint(r128ContextPtr r128ctx, + r128_vertex *tmp, float sz); + +extern void r128ChooseRenderState(GLcontext *ctx); +extern void r128TriangleFuncsInit(void); + +#endif +#endif /* _R128_TRIS_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_tritmp.h b/xc/lib/GL/mesa/src/drv/r128/r128_tritmp.h new file mode 100644 index 000000000..5cd66a8cd --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_tritmp.h @@ -0,0 +1,328 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#if !defined(TAG) || !defined(IND) + this is an error +#endif + +/* Draw a single triangle. Note that the device-dependent vertex data + might need to be changed based on the render state. */ +static void TAG(triangle)(GLcontext *ctx, + GLuint e0, GLuint e1, GLuint e2, + GLuint pv) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + struct vertex_buffer *VB = ctx->VB; + r128VertexPtr r128verts = R128_DRIVER_DATA(VB)->verts; + const r128_vertex *v0 = &r128verts[e0].v; + const r128_vertex *v1 = &r128verts[e1].v; + const r128_vertex *v2 = &r128verts[e2].v; + +#if (IND & R128_OFFSET_BIT) + GLfloat offset = ctx->Polygon.OffsetUnits * 1.0/0x10000; +#endif + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + int c0 = *(int *)&r128verts[pv].v.dif_argb; + int c1 = c0; + int c2 = c0; +#endif + +#if (IND & (R128_TWOSIDE_BIT | R128_OFFSET_BIT)) + { + GLfloat ex = v0->x - v2->x; + GLfloat ey = v0->y - v2->y; + GLfloat fx = v1->x - v2->x; + GLfloat fy = v1->y - v2->y; + GLfloat c = ex*fy - ey*fx; + +#if (IND & R128_TWOSIDE_BIT) + { + GLuint facing = (c > 0.0) ^ ctx->Polygon.FrontBit; + GLubyte (*vbcolor)[4] = VB->Color[facing]->data; + if (IND & R128_FLAT_BIT) { + R128_COLOR((char *)&c0, vbcolor[pv]); + c2 = c1 = c0; + } else { + R128_COLOR((char *)&c0, vbcolor[e0]); + R128_COLOR((char *)&c1, vbcolor[e1]); + R128_COLOR((char *)&c2, vbcolor[e2]); + } + } +#endif + +#if (IND & R128_OFFSET_BIT) + { + if (c * c > 1e-16) { + GLfloat factor = ctx->Polygon.OffsetFactor; + GLfloat ez = v0->z - v2->z; + GLfloat fz = v1->z - v2->z; + GLfloat a = ey*fz - ez*fy; + GLfloat b = ez*fx - ex*fz; + GLfloat ic = 1.0 / c; + GLfloat ac = a * ic; + GLfloat bc = b * ic; + if (ac < 0.0f) ac = -ac; + if (bc < 0.0f) bc = -bc; + offset += MAX2(ac, bc) * factor; + } + } +#endif + } +#endif + + if (r128ctx->regs.tex_cntl_c & (R128_TEXMAP_ENABLE | + R128_SEC_TEXMAP_ENABLE)) { + BEGIN_CLIP_LOOP(r128ctx); + +#if USE_RHW2 + R128CCE_WAIT_LOCKED(36); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_PRIM, 34); +#else + R128CCE_WAIT_LOCKED(33); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_PRIM, 31); +#endif + R128CCE(R128_FULL_VERTEX_FORMAT); + R128CCE(R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST | + R128_CCE_VC_CNTL_PRIM_WALK_RING | + (3 << R128_CCE_VC_CNTL_NUM_SHIFT)); + + R128CCEF(v0->x); + R128CCEF(v0->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v0->z + offset); +#else + R128CCEF(v0->z); +#endif + R128CCEF(v0->rhw); + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c0); +#else + R128CCE(*(int *)&v0->dif_argb); +#endif + R128CCE(*(int *)&v0->spec_frgb); + + R128CCEF(v0->tu0); + R128CCEF(v0->tv0); + R128CCEF(v0->tu1); + R128CCEF(v0->tv1); +#if USE_RHW2 + R128CCEF(v0->rhw2); +#endif + + R128CCEF(v1->x); + R128CCEF(v1->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v1->z + offset); +#else + R128CCEF(v1->z); +#endif + R128CCEF(v1->rhw); + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c1); +#else + R128CCE(*(int *)&v1->dif_argb); +#endif + R128CCE(*(int *)&v1->spec_frgb); + + R128CCEF(v1->tu0); + R128CCEF(v1->tv0); + R128CCEF(v1->tu1); + R128CCEF(v1->tv1); +#if USE_RHW2 + R128CCEF(v1->rhw2); +#endif + + R128CCEF(v2->x); + R128CCEF(v2->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v2->z + offset); +#else + R128CCEF(v2->z); +#endif + R128CCEF(v2->rhw); + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c2); +#else + R128CCE(*(int *)&v2->dif_argb); +#endif + R128CCE(*(int *)&v2->spec_frgb); + + R128CCEF(v2->tu0); + R128CCEF(v2->tv0); + R128CCEF(v2->tu1); + R128CCEF(v2->tv1); +#if USE_RHW2 + R128CCEF(v2->rhw2); +#endif + + R128CCE_END_LOCKED(); + + END_CLIP_LOOP(r128ctx); + } else { + BEGIN_CLIP_LOOP(r128ctx); + + R128CCE_WAIT_LOCKED(15); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_PRIM, 13); + R128CCE(R128_CCE_VC_FRMT_DIFFUSE_ARGB); + R128CCE(R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST | + R128_CCE_VC_CNTL_PRIM_WALK_RING | + (3 << R128_CCE_VC_CNTL_NUM_SHIFT)); + + R128CCEF(v0->x); + R128CCEF(v0->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v0->z + offset); +#else + R128CCEF(v0->z); +#endif + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c0); +#else + R128CCE(*(int *)&v0->dif_argb); +#endif + + R128CCEF(v1->x); + R128CCEF(v1->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v1->z + offset); +#else + R128CCEF(v1->z); +#endif + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c1); +#else + R128CCE(*(int *)&v1->dif_argb); +#endif + + R128CCEF(v2->x); + R128CCEF(v2->y); +#if (IND & R128_OFFSET_BIT) + R128CCEF(v2->z + offset); +#else + R128CCEF(v2->z); +#endif + +#if (IND & (R128_FLAT_BIT | R128_TWOSIDE_BIT)) + R128CCE(c2); +#else + R128CCE(*(int *)&v2->dif_argb); +#endif + + R128CCE_END_LOCKED(); + + END_CLIP_LOOP(r128ctx); + } +} + +static void TAG(quad)(GLcontext *ctx, + GLuint v0, GLuint v1, GLuint v2, GLuint v3, + GLuint pv) +{ + TAG(triangle)(ctx, v0, v1, v3, pv); + TAG(triangle)(ctx, v1, v2, v3, pv); +} + +#if ((IND & ~R128_FLAT_BIT) == 0) + +/* Draw a single line. Note that the device-dependent vertex data might + need to be changed based on the render state. */ +static void TAG(line)(GLcontext *ctx, + GLuint v0, GLuint v1, + GLuint pv) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + r128VertexPtr r128verts = R128_DRIVER_DATA(ctx->VB)->verts; + r128_vertex tmp0 = r128verts[v0].v; + r128_vertex tmp1 = r128verts[v1].v; + float width = ctx->Line.Width; + + if (IND & R128_FLAT_BIT) { + *(int *)&tmp1.dif_argb = + *(int *)&tmp0.dif_argb = + *(int *)&r128verts[pv].v.dif_argb; + } + + BEGIN_CLIP_LOOP(r128ctx); + + r128DrawLine(r128ctx, &tmp0, &tmp1, width); + + END_CLIP_LOOP(r128ctx); +} + +/* Draw a set of points. Note that the device-dependent vertex data + might need to be changed based on the render state. */ +static void TAG(points)(GLcontext *ctx, + GLuint first, GLuint last) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + struct vertex_buffer *VB = ctx->VB; + r128VertexPtr r128verts = R128_DRIVER_DATA(VB)->verts; + GLfloat sz = ctx->Point.Size * 0.5; + int i; + + BEGIN_CLIP_LOOP(r128ctx); + + for(i = first; i <= last; i++) { + if(VB->ClipMask[i] == 0) { + r128_vertex *tmp = &r128verts[i].v; + r128DrawPoint(r128ctx, tmp, sz); + } + } + + END_CLIP_LOOP(r128ctx); +} + +#endif + +/* Initialize the table of primitives to render. */ +static void TAG(init)(void) +{ + tri_tab[IND] = TAG(triangle); + quad_tab[IND] = TAG(quad); + +#if ((IND & ~R128_FLAT_BIT) == 0) + line_tab[IND] = TAG(line); + points_tab[IND] = TAG(points); +#endif +} + +#undef IND +#undef TAG diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_vb.c b/xc/lib/GL/mesa/src/drv/r128/r128_vb.c new file mode 100644 index 000000000..36c41a466 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_vb.c @@ -0,0 +1,559 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#include "r128_init.h" +#include "r128_mesa.h" +#include "r128_xmesa.h" +#include "r128_context.h" +#include "r128_lock.h" +#include "r128_reg.h" +#include "r128_cce.h" +#include "r128_state.h" +#include "r128_vb.h" + +#include "stages.h" + +#define TEX0 \ +do { \ + v->v.tu0 = tc0[i][0]; \ + v->v.tv0 = tc0[i][1]; \ +} while (0) + +#define TEX1 \ +do { \ + v->v.tu1 = tc1[i][0]; \ + v->v.tv1 = tc1[i][1]; \ +} while (0) + +#define SPC \ +do { \ + GLubyte *spec = &(VB->Spec[0][i][0]); \ + v->v.spec_frgb.r = spec[0]; \ + v->v.spec_frgb.g = spec[1]; \ + v->v.spec_frgb.b = spec[2]; \ +} while (0) + +#define FOG \ +do { \ + GLubyte *spec = &(VB->Spec[0][i][0]); \ + v->v.spec_frgb.a = spec[3]; \ +} while (0) + +#define COL \ +do { \ + GLubyte *col = &(VB->Color[0]->data[i][0]); \ + v->v.dif_argb.a = col[3]; \ + v->v.dif_argb.r = col[0]; \ + v->v.dif_argb.g = col[1]; \ + v->v.dif_argb.b = col[2]; \ +} while (0) + +#if 1 +/* FIXME: These are handled by the Rage 128 */ +#define TEX0_4 +#define TEX1_4 +#else +#define TEX0_4 \ +do { \ + if (VB->TexCoordPtr[0]->size == 4) { \ + GLfloat (*tc)[4] = VB->TexCoordPtr[0]->data; \ + v = &(R128_DRIVER_DATA(VB)->verts[start]); \ + for (i = start; i < end; i++, v++) { \ + float oow = 1.0 / tc[i][3]; \ + v->v.rhw *= tc[i][3]; \ + v->v.tu0 *= oow; \ + v->v.tv0 *= oow; \ + } \ + } \ +} while (0) + +#if USE_RHW2 +#define TEX1_4 \ +do { \ + if (VB->TexCoordPtr[1]->size == 4) { \ + GLfloat (*tc)[4] = VB->TexCoordPtr[1]->data; \ + v = &(R128_DRIVER_DATA(VB)->verts[start]); \ + for (i = start; i < end; i++, v++) { \ + float oow = 1.0 / tc[i][3]; \ + v->v.rhw2 *= tc[i][3]; \ + v->v.tu1 *= oow; \ + v->v.tv1 *= oow; \ + } \ + } \ +} while (0) +#else +#define TEX1_4 +#endif +#endif + +#if USE_RHW2 +#define COORD \ +do { \ + GLfloat *win = VB->Win.data[i]; \ + v->v.x = win[0]; \ + v->v.y = r128height - win[1]; \ + v->v.z = (1.0/0x10000) * win[2]; \ + v->v.rhw = v->v.rhw2 = win[3]; \ +} while (0) +#else +#define COORD \ +do { \ + GLfloat *win = VB->Win.data[i]; \ + v->v.x = win[0]; \ + v->v.y = r128height - win[1]; \ + v->v.z = (1.0/0x10000) * win[2]; \ + v->v.rhw = win[3]; \ +} while (0) +#endif + +#define NOP + +/* Setup the r128 vertex buffer entries */ +#define SETUPFUNC(name,win,col,tex0,tex1,tex0_4,tex1_4,spec,fog) \ +static void name(struct vertex_buffer *VB, GLuint start, GLuint end) \ +{ \ + r128ContextPtr r128ctx = R128_CONTEXT(VB->ctx); \ + __DRIdrawablePrivate *dPriv = r128ctx->driDrawable; \ + r128VertexPtr v; \ + GLfloat (*tc0)[4]; \ + GLfloat (*tc1)[4]; \ + GLfloat r128height = dPriv->h; \ + int i; \ + \ + (void) r128height; (void) r128ctx; \ + \ + gl_import_client_data(VB, VB->ctx->RenderFlags, \ + (VB->ClipOrMask \ + ? VEC_WRITABLE | VEC_GOOD_STRIDE \ + : VEC_GOOD_STRIDE)); \ + \ + tc0 = VB->TexCoordPtr[0]->data; \ + tc1 = VB->TexCoordPtr[1]->data; \ + \ + v = &(R128_DRIVER_DATA(VB)->verts[start]); \ + \ + if (VB->ClipOrMask == 0) \ + for (i = start; i < end; i++, v++) { \ + win; \ + col; \ + spec; \ + fog; \ + tex0; \ + tex1; \ + } \ + else \ + for (i = start; i < end; i++, v++) { \ + if (VB->ClipMask[i] == 0) { \ + win; \ + spec; \ + fog; \ + tex0; \ + tex1; \ + } \ + col; \ + } \ + tex0_4; \ + tex1_4; \ +} + + +SETUPFUNC(rs_wt0, COORD, NOP, TEX0, NOP, TEX0_4, NOP, NOP, NOP) +SETUPFUNC(rs_wt1, COORD, NOP, NOP, TEX1, NOP, TEX1_4, NOP, NOP) +SETUPFUNC(rs_wt0t1, COORD, NOP, TEX0, TEX1, TEX0_4, TEX1_4, NOP, NOP) +SETUPFUNC(rs_wft0, COORD, NOP, TEX0, NOP, TEX0_4, NOP, NOP, FOG) +SETUPFUNC(rs_wft1, COORD, NOP, NOP, TEX1, NOP, TEX1_4, NOP, FOG) +SETUPFUNC(rs_wft0t1, COORD, NOP, TEX0, TEX1, TEX0_4, TEX1_4, NOP, FOG) +SETUPFUNC(rs_wg, COORD, COL, NOP, NOP, NOP, NOP, NOP, NOP) +SETUPFUNC(rs_wgs, COORD, COL, NOP, NOP, NOP, NOP, SPC, NOP) +SETUPFUNC(rs_wgt0, COORD, COL, TEX0, NOP, TEX0_4, NOP, NOP, NOP) +SETUPFUNC(rs_wgt1, COORD, COL, NOP, TEX1, NOP, TEX1_4, NOP, NOP) +SETUPFUNC(rs_wgt0t1, COORD, COL, TEX0, TEX1, TEX0_4, TEX1_4, NOP, NOP) +SETUPFUNC(rs_wgst0, COORD, COL, TEX0, NOP, TEX0_4, NOP, SPC, NOP) +SETUPFUNC(rs_wgst1, COORD, COL, NOP, TEX1, NOP, TEX1_4, SPC, NOP) +SETUPFUNC(rs_wgst0t1, COORD, COL, TEX0, TEX1, TEX0_4, TEX1_4, SPC, NOP) +SETUPFUNC(rs_wgf, COORD, COL, NOP, NOP, NOP, NOP, NOP, FOG) +SETUPFUNC(rs_wgfs, COORD, COL, NOP, NOP, NOP, NOP, SPC, FOG) +SETUPFUNC(rs_wgft0, COORD, COL, TEX0, NOP, TEX0_4, NOP, NOP, FOG) +SETUPFUNC(rs_wgft1, COORD, COL, NOP, TEX1, NOP, TEX1_4, NOP, FOG) +SETUPFUNC(rs_wgft0t1, COORD, COL, TEX0, TEX1, TEX0_4, TEX1_4, NOP, FOG) +SETUPFUNC(rs_wgfst0, COORD, COL, TEX0, NOP, TEX0_4, NOP, SPC, FOG) +SETUPFUNC(rs_wgfst1 , COORD, COL, NOP, TEX1, NOP, TEX1_4, SPC, FOG) +SETUPFUNC(rs_wgfst0t1, COORD, COL, TEX0, TEX1, TEX0_4, TEX1_4, SPC, FOG) + +SETUPFUNC(rs_t0, NOP, NOP, TEX0, NOP, TEX0_4, NOP, NOP, NOP) +SETUPFUNC(rs_t1, NOP, NOP, NOP, TEX1, NOP, TEX1_4, NOP, NOP) +SETUPFUNC(rs_t0t1, NOP, NOP, TEX0, TEX1, TEX0_4, TEX1_4, NOP, NOP) +SETUPFUNC(rs_f, NOP, NOP, NOP, NOP, NOP, NOP, NOP, FOG) +SETUPFUNC(rs_ft0, NOP, NOP, TEX0, NOP, TEX0_4, NOP, NOP, FOG) +SETUPFUNC(rs_ft1, NOP, NOP, NOP, TEX1, NOP, TEX1_4, NOP, FOG) +SETUPFUNC(rs_ft0t1, NOP, NOP, TEX0, TEX1, TEX0_4, TEX1_4, NOP, FOG) +SETUPFUNC(rs_g, NOP, COL, NOP, NOP, NOP, NOP, NOP, NOP) +SETUPFUNC(rs_gs, NOP, COL, NOP, NOP, NOP, NOP, SPC, NOP) +SETUPFUNC(rs_gt0, NOP, COL, TEX0, NOP, TEX0_4, NOP, NOP, NOP) +SETUPFUNC(rs_gt1, NOP, COL, NOP, TEX1, NOP, TEX1_4, NOP, NOP) +SETUPFUNC(rs_gt0t1, NOP, COL, TEX0, TEX1, TEX0_4, TEX1_4, NOP, NOP) +SETUPFUNC(rs_gst0, NOP, COL, TEX0, NOP, TEX0_4, NOP, SPC, NOP) +SETUPFUNC(rs_gst1, NOP, COL, NOP, TEX1, NOP, TEX1_4, SPC, NOP) +SETUPFUNC(rs_gst0t1, NOP, COL, TEX0, TEX1, TEX0_4, TEX1_4, SPC, NOP) +SETUPFUNC(rs_gf, NOP, COL, NOP, NOP, NOP, NOP, NOP, FOG) +SETUPFUNC(rs_gfs, NOP, COL, NOP, NOP, NOP, NOP, SPC, FOG) +SETUPFUNC(rs_gft0, NOP, COL, TEX0, NOP, TEX0_4, NOP, NOP, FOG) +SETUPFUNC(rs_gft1, NOP, COL, NOP, TEX1, NOP, TEX1_4, NOP, FOG) +SETUPFUNC(rs_gft0t1, NOP, COL, TEX0, TEX1, TEX0_4, TEX1_4, NOP, FOG) +SETUPFUNC(rs_gfst0, NOP, COL, TEX0, NOP, TEX0_4, NOP, SPC, FOG) +SETUPFUNC(rs_gfst1, NOP, COL, NOP, TEX1, NOP, TEX1_4, SPC, FOG) +SETUPFUNC(rs_gfst0t1, NOP, COL, TEX0, TEX1, TEX0_4, TEX1_4, SPC, FOG) + +static void rs_invalid(struct vertex_buffer *VB, GLuint start, GLuint end) +{ + R128_DEBUG(("r128RasterSetup(): invalid setup function\n")); +} + +typedef void (*setupFunc)(struct vertex_buffer *, GLuint, GLuint); +static setupFunc setup_func[0x80]; + +/* Initialize the table of vertex buffer setup functions */ +void r128SetupInit(void) +{ + int i; + + for (i = 0; i < 0x80; i++) setup_func[i] = rs_invalid; + + /* Funcs to build vertices from scratch */ + setup_func[R128_WIN_BIT|R128_TEX0_BIT] = rs_wt0; + setup_func[R128_WIN_BIT|R128_TEX1_BIT] = rs_wt1; + setup_func[R128_WIN_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wt0t1; + setup_func[R128_WIN_BIT|R128_FOG_BIT|R128_TEX0_BIT] = rs_wft0; + setup_func[R128_WIN_BIT|R128_FOG_BIT|R128_TEX1_BIT] = rs_wft1; + setup_func[R128_WIN_BIT|R128_FOG_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wft0t1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT] = rs_wg; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_SPEC_BIT] = rs_wgs; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_TEX0_BIT] = rs_wgt0; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_TEX1_BIT] = rs_wgt1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wgt0t1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX0_BIT] = rs_wgst0; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX1_BIT] = rs_wgst1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wgst0t1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT] = rs_wgf; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT] = rs_wgfs; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_TEX0_BIT] = rs_wgft0; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_TEX1_BIT] = rs_wgft1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wgft0t1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX0_BIT] = rs_wgfst0; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX1_BIT] = rs_wgfst1; + setup_func[R128_WIN_BIT|R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_wgfst0t1; + + /* Funcs to repair vertices */ + setup_func[R128_TEX0_BIT] = rs_t0; + setup_func[R128_TEX1_BIT] = rs_t1; + setup_func[R128_TEX0_BIT|R128_TEX1_BIT] = rs_t0t1; + setup_func[R128_FOG_BIT] = rs_f; + setup_func[R128_FOG_BIT|R128_TEX0_BIT] = rs_ft0; + setup_func[R128_FOG_BIT|R128_TEX1_BIT] = rs_ft1; + setup_func[R128_FOG_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_ft0t1; + setup_func[R128_RGBA_BIT] = rs_g; + setup_func[R128_RGBA_BIT|R128_SPEC_BIT] = rs_gs; + setup_func[R128_RGBA_BIT|R128_TEX0_BIT] = rs_gt0; + setup_func[R128_RGBA_BIT|R128_TEX1_BIT] = rs_gt1; + setup_func[R128_RGBA_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_gt0t1; + setup_func[R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX0_BIT] = rs_gst0; + setup_func[R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX1_BIT] = rs_gst1; + setup_func[R128_RGBA_BIT|R128_SPEC_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_gst0t1; + setup_func[R128_RGBA_BIT|R128_FOG_BIT] = rs_gf; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT] = rs_gfs; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_TEX0_BIT] = rs_gft0; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_TEX1_BIT] = rs_gft1; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_gft0t1; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX0_BIT] = rs_gfst0; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX1_BIT] = rs_gfst1; + setup_func[R128_RGBA_BIT|R128_FOG_BIT|R128_SPEC_BIT|R128_TEX0_BIT|R128_TEX1_BIT] = rs_gfst0t1; +} + +/* Initialize the vertex buffer setup functions based on the current + rendering state */ +void r128ChooseRasterSetupFunc(GLcontext *ctx) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + int funcIndex = R128_WIN_BIT | R128_RGBA_BIT; + + if (ctx->Texture.Enabled & 0xf) { + if (ctx->Texture.Unit[0].EnvMode == GL_REPLACE) + funcIndex &= ~R128_RGBA_BIT; + funcIndex |= R128_TEX0_BIT; + } + + if (ctx->Texture.Enabled & 0xf0) + funcIndex |= R128_TEX1_BIT; + + /* FIXME: Verify this works properly */ + if (ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) + funcIndex |= R128_SPEC_BIT; + + if (ctx->FogMode == FOG_FRAGMENT) + funcIndex |= R128_FOG_BIT; + + r128ctx->SetupIndex = funcIndex; + ctx->Driver.RasterSetup = setup_func[funcIndex]; +} + +/* Check to see if any updates of the vertex buffer entries are needed */ +void r128CheckPartialRasterSetup(GLcontext *ctx, + struct gl_pipeline_stage *s) +{ + r128ContextPtr r128ctx = R128_CONTEXT(ctx); + int tmp = r128ctx->SetupDone; + + s->type = 0; + r128ctx->SetupDone = GL_FALSE; + + if ((ctx->Array.Summary & VERT_OBJ_ANY) == 0) return; + if (ctx->IndirectTriangles) return; + + r128ctx->SetupDone = tmp; +} + +/* Update the vertex buffer entries, if necessary */ +void r128PartialRasterSetup(struct vertex_buffer *VB) +{ + r128ContextPtr r128ctx = R128_CONTEXT(VB->ctx); + int new = VB->pipeline->new_outputs; + int available = VB->pipeline->outputs; + int index = 0; + + if (new & VERT_WIN) { + new = available; + index |= R128_WIN_BIT | R128_FOG_BIT; + } + + if (new & VERT_RGBA) index |= R128_RGBA_BIT | R128_SPEC_BIT; + if (new & VERT_TEX0_ANY) index |= R128_TEX0_BIT; + if (new & VERT_TEX1_ANY) index |= R128_TEX1_BIT; +#if 0 + /* FIXME */ + if (new & VERT_FOG_COORD) index |= R128_FOG_BIT; +#endif + + r128ctx->SetupDone &= ~index; + index &= r128ctx->SetupIndex; + r128ctx->SetupDone |= index; + + if (index) setup_func[index & ~R128_ALPHA_BIT](VB, VB->Start, VB->Count); +} + +/* Perform the raster setup for the fast path, if using CVA */ +void r128DoRasterSetup(struct vertex_buffer *VB) +{ + GLcontext *ctx = VB->ctx; + + if (VB->Type == VB_CVA_PRECALC) r128PartialRasterSetup(VB); + else if (ctx->Driver.RasterSetup) ctx->Driver.RasterSetup(VB, + VB->CopyStart, + VB->Count); +} + +/* Resize an existing vertex buffer */ +void r128ResizeVB(struct vertex_buffer *VB, GLuint size) +{ + r128VertexBufferPtr r128vb = R128_DRIVER_DATA(VB); + + while (r128vb->size < size) + r128vb->size *= 2; + + free(r128vb->vert_store); + r128vb->vert_store = malloc(sizeof(r128Vertex) * r128vb->size + 31); + if (!r128vb->vert_store) { + fprintf(stderr, "Cannot allocate vertex store! Exiting...\n"); + exit(1); + } + + r128vb->verts = (r128VertexPtr)(((CARD32)r128vb->vert_store + 31) & ~31); + + gl_vector1ui_free(&r128vb->clipped_elements); + gl_vector1ui_alloc(&r128vb->clipped_elements, + VEC_WRITABLE, r128vb->size, 32); + if (!r128vb->clipped_elements.start) { + fprintf(stderr, "Cannot allocate clipped elements! Exiting...\n"); + exit(1); + } + + free(VB->ClipMask); + VB->ClipMask = (GLubyte *)malloc(sizeof(GLubyte) * r128vb->size); + if (!VB->ClipMask) { + fprintf(stderr, "Cannot allocate clipmask! Exiting...\n"); + exit(1); + } +} + +/* Create a new device-dependent vertex buffer */ +void r128DDRegisterVB(struct vertex_buffer *VB) +{ + r128VertexBufferPtr r128vb; + + r128vb = (r128VertexBufferPtr)calloc(1, sizeof(*r128vb)); + + r128vb->size = VB->Size * 2; + r128vb->vert_store = malloc(sizeof(r128Vertex) * r128vb->size + 31); + if (!r128vb->vert_store) { + fprintf(stderr, "Cannot allocate vertex store! Exiting...\n"); + exit(1); + } + + r128vb->verts = (r128VertexPtr)(((CARD32)r128vb->vert_store + 31) & ~31); + + gl_vector1ui_alloc(&r128vb->clipped_elements, + VEC_WRITABLE, r128vb->size, 32); + if (!r128vb->clipped_elements.start) { + fprintf(stderr, "Cannot allocate clipped elements! Exiting...\n"); + exit(1); + } + + free(VB->ClipMask); + VB->ClipMask = (GLubyte *)malloc(sizeof(GLubyte) * r128vb->size); + if (!VB->ClipMask) { + fprintf(stderr, "Cannot allocate clipmask! Exiting...\n"); + exit(1); + } + + VB->driver_data = r128vb; +} + +/* Destroy a device-dependent vertex buffer */ +void r128DDUnregisterVB(struct vertex_buffer *VB) +{ + r128VertexBufferPtr r128vb = R128_DRIVER_DATA(VB); + + if (r128vb) { + if (r128vb->vert_store) free(r128vb->vert_store); + gl_vector1ui_free(&r128vb->clipped_elements); + free(r128vb); + VB->driver_data = 0; + } +} + +/* Get a new VB from the pool of vertex buffers in AGP space */ +static r128CCEVertBufPtr r128CCEGetNewVB(r128ContextPtr r128ctx) +{ +#define R128_VB_SIZE 4096 + + /* FIXME: This only works for a single client right now!!! */ + if (r128ctx->vb) { + r128ctx->vb->start += R128_VB_SIZE; + if (r128ctx->vb->start > + r128ctx->r128Screen->vbStart + r128ctx->r128Screen->vbSize) + r128ctx->vb->start = r128ctx->r128Screen->vbStart; + } else { + r128ctx->vb = (r128CCEVertBufPtr)malloc(sizeof(*r128ctx->vb)); + r128ctx->vb->start = r128ctx->r128Screen->vbStart; + r128ctx->vb->size = R128_VB_SIZE/sizeof(r128_vertex); + } + + r128ctx->vb->count = 0; + r128ctx->vb->done = GL_FALSE; + + return r128ctx->vb; +} + +/* Release a VB back to the pool of vertex buffers in AGP space */ +static void r128CCEReleaseVB(r128ContextPtr r128ctx) +{ + r128ctx->vb->done = GL_TRUE; +} + +/* Reserve space in a VB to store `verts' vertices. If adding these + vertices to the VB would exceed the size of the VB, then flush the + current VB, get a new one from the pool of VBs, and reserve space in + the new VB for the `verts' vertices. */ +r128_vertex *r128CCEAllocVBSpace(r128ContextPtr r128ctx, int verts) +{ + r128_vertex *vbptr; + r128CCEVertBufPtr vb = r128ctx->vb; + + if (!vb || vb->done) vb = r128CCEGetNewVB(r128ctx); + + if (vb->count + verts > vb->size) { + r128CCEFlushVB(r128ctx); + vb = r128CCEGetNewVB(r128ctx); + } + + vbptr = (r128_vertex *)(r128ctx->r128Screen->agp + vb->start) + vb->count; + vb->count += verts; + return vbptr; +} + +/* Send a VB to the Rage 128 to be processed */ +void r128CCEFlushVB(r128ContextPtr r128ctx) +{ + unsigned char *R128MMIO = r128ctx->r128Screen->mmio; + + if (!r128ctx->vb || + !r128ctx->vb->count || + r128ctx->vb->done) return; + + /* Make sure vertices are in memory, and not stuck in the WC cache */ + R128FlushWCMemory(); + + /* FIXME: The textures referenced in this VB cannot be removed until + after this buffer has been processed. ATI suggests loading new + textures via HOSTDATA command packets to solve this problem. */ + + /* FIXME: We need a way to detect if the VB is free or if it is + still in use. By waiting for idle, we know that the currently + processing buffer is complete, but waiting is slow. A better + solution is to use a counter that is stored in one of the + GUI_SCRATCH_REGs, which gets incremented after each VB is + processed. Also, we will need to associate the count value with + each VB in the pool of VBs -- this will need to be stored in the + SAREA. */ + +#if 1 + /* FIXME: Is this _really_ needed? */ + R128CCEWaitForIdle(r128ctx->r128Screen); +#endif + + BEGIN_CLIP_LOOP(r128ctx); + + R128CCE_WAIT_LOCKED(5); + R128CCE3(R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); + R128CCE(r128ctx->vb->start); + R128CCE(r128ctx->vb->count); + R128CCE(R128_FULL_VERTEX_FORMAT); + R128CCE(R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST | + R128_CCE_VC_CNTL_PRIM_WALK_LIST | + (r128ctx->vb->count << R128_CCE_VC_CNTL_NUM_SHIFT)); + R128CCE_END_LOCKED(); + + END_CLIP_LOOP(r128ctx); + + r128CCEReleaseVB(r128ctx); +} diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_vb.h b/xc/lib/GL/mesa/src/drv/r128/r128_vb.h new file mode 100644 index 000000000..9b0a3f7c7 --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_vb.h @@ -0,0 +1,162 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_VB_H_ +#define _R128_VB_H_ + +#ifdef GLX_DIRECT_RENDERING + +#define USE_RHW2 0 + +/* FIXME: This is endian-specific */ +typedef struct { + GLubyte b; + GLubyte g; + GLubyte r; + GLubyte a; +} r128Color; + +typedef struct { + GLfloat x, y, z; /* Coordinates in screen space */ + GLfloat rhw; /* Reciprocal homogeneous w */ + r128Color dif_argb; /* Diffuse color */ + r128Color spec_frgb; /* Specular color (alpha is fog) */ + GLfloat tu0, tv0; /* Texture 0 coordinates */ + GLfloat tu1, tv1; /* Texture 1 coordinates */ +#if USE_RHW2 + GLfloat rhw2; /* Reciprocal homogeneous w */ +#endif +} r128_vertex; + +#if USE_RHW2 +/* Format of vertices in r128_vertex struct */ +#define R128_FULL_VERTEX_FORMAT \ + R128_CCE_VC_FRMT_RHW | \ + R128_CCE_VC_FRMT_DIFFUSE_ARGB | \ + R128_CCE_VC_FRMT_SPEC_FRGB | \ + R128_CCE_VC_FRMT_S_T | \ + R128_CCE_VC_FRMT_S2_T2 | \ + R128_CCE_VC_FRMT_RHW2 + +/* Send a single vertex to the ring buffer */ +#define R128CCE_SEND_VERTEX(v) \ +do { \ + R128CCEF((v)->x); \ + R128CCEF((v)->y); \ + R128CCEF((v)->z); \ + R128CCEF((v)->rhw); \ + R128CCE(*(int *)&(v)->dif_argb); \ + R128CCE(*(int *)&(v)->spec_frgb); \ + R128CCEF((v)->tu0); \ + R128CCEF((v)->tv0); \ + R128CCEF((v)->tu1); \ + R128CCEF((v)->tv1); \ + R128CCEF((v)->rhw2); \ +} while (0) + +#else /* !USE_RHW2 */ + +/* Format of vertices in r128_vertex struct */ +#define R128_FULL_VERTEX_FORMAT \ + R128_CCE_VC_FRMT_RHW | \ + R128_CCE_VC_FRMT_DIFFUSE_ARGB | \ + R128_CCE_VC_FRMT_SPEC_FRGB | \ + R128_CCE_VC_FRMT_S_T | \ + R128_CCE_VC_FRMT_S2_T2 + +/* Send a single vertex to the ring buffer */ +#define R128CCE_SEND_VERTEX(v) \ +do { \ + R128CCEF((v)->x); \ + R128CCEF((v)->y); \ + R128CCEF((v)->z); \ + R128CCEF((v)->rhw); \ + R128CCE(*(int *)&(v)->dif_argb); \ + R128CCE(*(int *)&(v)->spec_frgb); \ + R128CCEF((v)->tu0); \ + R128CCEF((v)->tv0); \ + R128CCEF((v)->tu1); \ + R128CCEF((v)->tv1); \ +} while (0) +#endif + +/* FIXME: We currently only have assembly for 16-stride vertices */ +typedef union { + r128_vertex v; + float f[16]; +} r128Vertex, *r128VertexPtr; + +/* Vertex buffer for use when on the fast path */ +typedef struct { + GLuint size; /* Number of vertices in store */ + void *vert_store; /* Storage for vertex buffer */ + r128VertexPtr verts; /* Aligned start of verts in storage */ + int last_vert; /* Index of last vertex used */ + GLvector1ui clipped_elements; /* List of clipped elements */ +} *r128VertexBufferPtr; + +#define R128_DRIVER_DATA(vb) ((r128VertexBufferPtr)((vb)->driver_data)) + +#if USE_VERTEX_BUFFERS +#define R128_FLUSH_VB(CC) \ +do { \ + if ((CC)->vb) r128CCEFlushVB(CC); \ +} while (0) +#else +#define R128_FLUSH_VB(CC) (void)(CC) +#endif + +#define R128_SPEC_BIT 0x01 +#define R128_FOG_BIT 0x02 +#define R128_ALPHA_BIT 0x04 /* GL_BLEND, not used */ +#define R128_TEX1_BIT 0x08 +#define R128_TEX0_BIT 0x10 +#define R128_RGBA_BIT 0x20 +#define R128_WIN_BIT 0x40 + +extern void r128SetupInit(void); +extern void r128ChooseRasterSetupFunc(GLcontext *ctx); +extern void r128CheckPartialRasterSetup(GLcontext *ctx, + struct gl_pipeline_stage *s); +extern void r128PartialRasterSetup(struct vertex_buffer *VB); +extern void r128DoRasterSetup(struct vertex_buffer *VB); +extern void r128ResizeVB(struct vertex_buffer *VB, GLuint size); +extern void r128DDRegisterVB(struct vertex_buffer *VB); +extern void r128DDUnregisterVB(struct vertex_buffer *VB); + +extern r128_vertex *r128CCEAllocVBSpace(r128ContextPtr r128ctx, int verts); +extern void r128CCEFlushVB(r128ContextPtr r128ctx); + +#endif +#endif /* _R128_VB_H_ */ diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.c b/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.c new file mode 100644 index 000000000..8a23ae34e --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.c @@ -0,0 +1,307 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifdef GLX_DIRECT_RENDERING + +/* r128 Mesa driver includes */ +#include "r128_init.h" +#include "r128_context.h" +#include "r128_xmesa.h" +#include "r128_state.h" +#include "r128_tex.h" +#include "r128_swap.h" + +/* Mesa src includes */ +#include "context.h" +#include "simple_list.h" + +#ifdef DEBUG_LOCKING +char *prevLockFile = NULL; +int prevLockLine = 0; +#endif + +static r128ContextPtr r128Context = NULL; + +/* Count the number of bits set */ +static int count_bits(unsigned int n) +{ + int bits = 0; + + while (n > 0) { + if (n & 1) bits++; + n >>= 1; + } + return bits; +} + +/* FIXME: */ + +/* Initialize the driver specific screen private data */ +GLboolean XMesaInitDriver(__DRIscreenPrivate *sPriv) +{ + sPriv->private = (void *)r128CreateScreen(sPriv); + if (!sPriv->private) return GL_FALSE; + + return GL_TRUE; +} + +/* Reset the driver specific screen private data */ +void XMesaResetDriver(__DRIscreenPrivate *sPriv) +{ + r128DestroyScreen(sPriv); +} + +/* Create and initialize the Mesa and driver specific visual data */ +XMesaVisual XMesaCreateVisual(XMesaDisplay *display, + XMesaVisualInfo visinfo, + GLboolean rgb_flag, + GLboolean alpha_flag, + GLboolean db_flag, + GLboolean stereo_flag, + GLboolean ximage_flag, + GLint depth_size, + GLint stencil_size, + GLint accum_size, + GLint level) +{ + XMesaVisual v; + + /* FIXME: Only RGB visuals are currently supported */ + if (!rgb_flag) return NULL; + + v = (XMesaVisual)Xmalloc(sizeof(*v)); + if (!v) return NULL; + + v->visinfo = (XVisualInfo *)Xmalloc(sizeof(*visinfo)); + if(!v->visinfo) { + Xfree(v); + return NULL; + } + memcpy(v->visinfo, visinfo, sizeof(*visinfo)); + + v->display = display; + v->level = level; + + v->gl_visual = (GLvisual *)Xmalloc(sizeof(*v->gl_visual)); + if (!v->gl_visual) { + Xfree(v->visinfo); + XFree(v); + return NULL; + } + + v->gl_visual->RGBAflag = rgb_flag; + v->gl_visual->DBflag = db_flag; + v->gl_visual->StereoFlag = stereo_flag; + + v->gl_visual->RedBits = count_bits(visinfo->red_mask); + v->gl_visual->GreenBits = count_bits(visinfo->green_mask); + v->gl_visual->BlueBits = count_bits(visinfo->blue_mask); + v->gl_visual->AlphaBits = 0; /* Not currently supported */ + + v->gl_visual->AccumBits = accum_size; + v->gl_visual->DepthBits = depth_size; + v->gl_visual->StencilBits = stencil_size; + + return v; +} + +/* Destroy the Mesa and driver specific visual data */ +void XMesaDestroyVisual(XMesaVisual v) +{ + Xfree(v->gl_visual); + Xfree(v->visinfo); + Xfree(v); +} + +/* Create and initialize the Mesa and driver specific context data */ +XMesaContext XMesaCreateContext(XMesaVisual v, XMesaContext share_list, + __DRIcontextPrivate *driContextPriv) +{ + XMesaContext c; + + c = (XMesaContext)Xmalloc(sizeof(*c)); + if (!c) { + return NULL; + } + + /* Initialize XMesaContext */ + c->display = v->display; + c->xm_visual = v; + c->xm_buffer = NULL; /* Set by MakeCurrent */ + c->driContextPriv = driContextPriv; + c->private = (void *)r128CreateContext(v->gl_visual, c, share_list); + if (!c->private) { + Xfree(c); + return NULL; + } + + return c; +} + +/* Destroy the Mesa and driver specific context data */ +void XMesaDestroyContext(XMesaContext c) +{ + if (c->private == (void *)r128Context) r128Context = NULL; + r128DestroyContext((r128ContextPtr)c->private); + Xfree(c); +} + +/* Create and initialize the Mesa and driver specific window buffer data */ +XMesaBuffer XMesaCreateWindowBuffer(XMesaVisual v, + XMesaWindow w, + __DRIdrawablePrivate *driDrawPriv) +{ + XMesaBuffer xm_buf; + + xm_buf = (XMesaBuffer)Xmalloc(sizeof(*xm_buf)); + /* FIXME: Change when HW stencil support is added */ + xm_buf->gl_buffer = gl_create_framebuffer(v->gl_visual, + GL_FALSE, + v->gl_visual->StencilBits > 0, + v->gl_visual->AccumBits > 0, + v->gl_visual->AlphaBits > 0); + xm_buf->driDrawPriv = driDrawPriv; + + return xm_buf; +} + +/* Create and initialize the Mesa and driver specific pixmap buffer data */ +XMesaBuffer XMesaCreatePixmapBuffer(XMesaVisual v, + XMesaPixmap p, + XMesaColormap c, + __DRIdrawablePrivate *driDrawPriv) +{ + XMesaBuffer xm_buf; + + xm_buf = (XMesaBuffer)Xmalloc(sizeof(*xm_buf)); + /* FIXME: Change when HW stencil support is added */ + xm_buf->gl_buffer = gl_create_framebuffer(v->gl_visual, + GL_FALSE, + v->gl_visual->StencilBits > 0, + v->gl_visual->AccumBits > 0, + v->gl_visual->AlphaBits > 0); + xm_buf->driDrawPriv = driDrawPriv; + + return xm_buf; +} + +/* Destroy the Mesa and driver specific color buffer data */ +void XMesaDestroyBuffer(XMesaBuffer b) +{ + gl_destroy_framebuffer(b->gl_buffer); + Xfree(b); +} + +/* Copy the back color buffer to the front color buffer */ +void XMesaSwapBuffers(XMesaBuffer b) +{ + /* + ** FIXME: This assumes buffer is currently bound to a context. + ** This needs to be able to swap buffers when not currently bound. + */ + if (r128Context == NULL) return; + + /* FIXME: Only swap buffers when a back buffer exists */ + + FLUSH_VB(R128_MESACTX(r128Context), "swap buffers"); + r128SwapBuffers(r128Context); +} + +/* Force the context `c' to be the current context and associate with it + buffer `b' */ +GLboolean XMesaMakeCurrent(XMesaContext c, XMesaBuffer b) +{ + if (c) { + if (r128Context && + c->private == (void *)r128Context && + b->driDrawPriv == R128_DRIDRAWABLE(r128Context)) + return GL_TRUE; + + r128Context = r128MakeCurrent(r128Context, (r128ContextPtr)c->private, + b->driDrawPriv); + + gl_make_current(R128_MESACTX(r128Context), b->gl_buffer); + + if (!R128_MESACTX(r128Context)->Viewport.Width) { + gl_Viewport(R128_MESACTX(r128Context), 0, 0, + b->driDrawPriv->w, b->driDrawPriv->h); + } + } else { + gl_make_current(0,0); + r128Context = NULL; + } + + return GL_TRUE; +} + +/* Force the context `c' to be unbound from its buffer */ +GLboolean XMesaUnbindContext(XMesaContext c) +{ + return GL_TRUE; +} + +/* Update the hardware state. This is called if another context has + grabbed the hardware lock, which includes the X server. This + function also updates the driver's window state after the X server + moves, resizes or restacks a window -- the change will be reflected + in the drawable position and clip rects. Since the X server grabs + the hardware lock when it changes the window state, this routine will + automatically be called after such a change. */ +/* NOTE: This routine is only called while holding the hardware lock. */ +void XMesaUpdateState(XMesaContext c) +{ + __DRIscreenPrivate *sPriv = R128_DRISCREEN((r128ContextPtr)c->private); + __DRIdrawablePrivate *dPriv = R128_DRIDRAWABLE((r128ContextPtr)c->private); + int stamp = dPriv->lastStamp; + + /* The window might have moved, so we might need to get new clip + rects. + + NOTE: This releases and regrabs the hw lock to allow the X server + to respond to the DRI protocol request for new drawable info. + Since the hardware state depends on having the latest drawable + clip rects, all state checking must be done _after_ this call. */ + XMESA_VALIDATE_DRAWABLE_INFO(c->display, sPriv, dPriv); + + r128UpdateState((r128ContextPtr)c->private, (stamp != dPriv->lastStamp)); +} + +/* This function is called by libGL.so as soon as libGL.so is loaded. + * This is where we'd register new extension functions with the dispatcher. + */ +void __driRegisterExtensions(void) +{ +} + +#endif diff --git a/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.h b/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.h new file mode 100644 index 000000000..ac35fad2d --- /dev/null +++ b/xc/lib/GL/mesa/src/drv/r128/r128_xmesa.h @@ -0,0 +1,44 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_XMESA_H_ +#define _R128_XMESA_H_ + +#ifdef GLX_DIRECT_RENDERING + +extern void XMesaUpdateState(XMesaContext c); +extern void __driRegisterExtensions(void); + +#endif +#endif /* _R128_XMESA_H_ */ diff --git a/xc/programs/Xserver/Imakefile b/xc/programs/Xserver/Imakefile index 45300d897..0305b16ce 100644 --- a/xc/programs/Xserver/Imakefile +++ b/xc/programs/Xserver/Imakefile @@ -619,7 +619,7 @@ XF86IDRVOBJS = $(XF86SRC)/input/drvConf.o XF86IDRVLIBS = $(XF86IDRIVERLIB) XF86SCANLIB = $(XF86SRC)/scanpci/LibraryTargetName(scanpci) XF86LIBS = $(XF86INIT) $(XF86COMLIB) $(XF86RACLIB) $(XF86PARSLIB) \ - $(XF86OSLIB) $(XF86INT10LIB) + $(XF86OSLIB) $(XF86INT10LIB) $(XF86DDCLIB) #else XF86LIBS = $(XF86INIT) $(XF86COMLIB) $(XF86PARSLIB) $(XF86OSLIB) #endif diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/Imakefile b/xc/programs/Xserver/hw/xfree86/drivers/r128/Imakefile index e3f7178bf..8f0f33a35 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/Imakefile +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/Imakefile @@ -6,9 +6,16 @@ XCOMM #define IHaveModules #include <Server.tmpl> -SRCS = r128_driver.c r128_cursor.c r128_accel.c # r128_i2c.c +#if BuildXF86DRI +DRISRCS = r128_dri.c +DRIOBJS = r128_dri.o +DRIINCLUDES = -I$(SERVERSRC)/GL/dri -I$(LIBSRC)/GL/dri +DRIDEFINES = $(GLX_DEFINES) +#endif + +SRCS = r128_driver.c r128_cursor.c r128_accel.c $(DRISRCS) # r128_i2c.c -OBJS = r128_driver.o r128_cursor.o r128_accel.o # r128_i2c.o +OBJS = r128_driver.o r128_cursor.o r128_accel.o $(DRIOBJS) # r128_i2c.o #if defined(XF86DriverSDK) INCLUDES = -I. -I../../include @@ -22,9 +29,12 @@ INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) \ -I$(XF86SRC)/ddc -I$(XF86SRC)/i2c -I$(XF86OSSRC)/vbe \ -I$(XF86SRC)/int10 -I$(SERVERSRC)/Xext \ -I$(FONTINCSRC) -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ - -I$(EXTINCSRC) -I$(XF86SRC)/xf24_32bpp + -I$(EXTINCSRC) -I$(XF86SRC)/xf24_32bpp \ + $(DRIINCLUDES) #endif +DEFINES = $(DRIDEFINES) + #if MakeHasPosixVariableSubstitutions SubdirLibraryRule($(OBJS)) #endif @@ -49,5 +59,10 @@ InstallDriverSDKNonExecFile(r128_cursor.c,$(DRIVERSDKDIR)/drivers/r128) InstallDriverSDKNonExecFile(r128_driver.c,$(DRIVERSDKDIR)/drivers/r128) InstallDriverSDKNonExecFile(r128_reg.h,$(DRIVERSDKDIR)/drivers/r128) +InstallDriverSDKNonExecFile(r128_dri.c,$(DRIVERSDKDIR)/drivers/r128) +InstallDriverSDKNonExecFile(r128_dri.h,$(DRIVERSDKDIR)/drivers/r128) +InstallDriverSDKNonExecFile(r128_dripriv.h,$(DRIVERSDKDIR)/drivers/r128) +InstallDriverSDKNonExecFile(r128_sarea.h,$(DRIVERSDKDIR)/drivers/r128) + InstallDriverSDKObjectModule(r128,$(DRIVERSDKMODULEDIR),drivers) diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h index d5d120153..7f2c2e0c6 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h @@ -1,8 +1,8 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/r128/r128.h,v 1.8 2000/02/23 04:47:18 martin Exp $ */ /************************************************************************** -Copyright 1999 ATI Technologies Inc. and Precision Insight, Inc., - Cedar Park, Texas. +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -28,18 +28,21 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* * Authors: - * Rickard E. Faith <faith@precisioninsight.com> * Kevin E. Martin <kevin@precisioninsight.com> + * Rickard E. Faith <faith@precisioninsight.com> * */ #ifndef _R128_H_ #define _R128_H_ -#define R128_DEBUG 0 /* Turn off debugging output */ +#define R128_DEBUG 1 /* Turn off debugging output */ #define R128_TIMEOUT 2000000 /* Fall out of wait loops after this count */ #define R128_MMIOSIZE 0x80000 + /* R128_NAME is used for the server-side + ddx driver, the client-side DRI driver, + and the kernel-level DRM driver. */ #define R128_NAME "r128" #define R128_VERSION_MAJOR 3 #define R128_VERSION_MINOR 0 @@ -157,7 +160,7 @@ typedef struct { unsigned char *FB; /* Map of frame buffer */ CARD32 MemCntl; - CARD32 BusCntl; + CARD32 BusCntl; unsigned long FbMapSize; /* Size of frame buffer, in bytes */ int Flags; /* Saved copy of mode flags */ @@ -199,8 +202,74 @@ typedef struct { int scanline_words; int scanline_direct; int scanline_bpp; /* Only used for ImageWrite */ + +#ifdef XF86DRI + Bool directRenderingEnabled; + DRIInfoPtr pDRIInfo; + int drmFD; + int numVisualConfigs; + __GLXvisualConfig *pVisualConfigs; + R128ConfigPrivPtr pVisualConfigsPriv; + + drmHandle fbHandle; + + drmSize registerSize; + drmHandle registerHandle; + + drmSize agpSize; + drmHandle agpMemHandle; /* Handle from drmAgpAlloc */ + unsigned long agpOffset; + drmHandle agpHandle; /* Handle from drmAddMap */ + unsigned char *AGP; /* Map */ + + Bool CCEInUse; /* CCE is currently active */ + int CCEMode; /* CCE mode that server/clients use */ + int CCEFifoSize; /* Size of the CCE command FIFO */ + + /* CCE ring buffer data */ + unsigned long ringStart; + int ringSize; + int ringWrite; + unsigned long ringReadOffset; + + /* CCE vertex buffer data */ + unsigned long vbStart; + int vbSize; + + /* CCE indirect buffer data */ + unsigned long indStart; + int indSize; + + /* CCE AGP Texture data */ + unsigned long agpTexStart; + int agpTexSize; + int log2AGPTexGran; + + /* DRI screen private data */ + int fbX; + int fbY; + int backX; + int backY; + int depthX; + int depthY; + int textureX; + int textureY; + int textureSize; + int log2TexGran; +#endif } R128InfoRec, *R128InfoPtr; +#define R128WaitForFifo(pScrn, entries) \ +do { \ + if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \ + info->fifo_slots -= entries; \ +} while (0) + +extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries); +extern void R128WaitForIdle(ScrnInfoPtr pScrn); +extern void R128EngineReset(ScrnInfoPtr pScrn); +extern void R128EngineFlush(ScrnInfoPtr pScrn); + extern int INPLL(ScrnInfoPtr pScrn, int addr); extern void R128WaitForVerticalSync(ScrnInfoPtr pScrn); @@ -208,4 +277,15 @@ extern Bool R128AccelInit(ScreenPtr pScreen); extern void R128EngineInit(ScrnInfoPtr pScrn); extern Bool R128CursorInit(ScreenPtr pScreen); +extern int R128MinBits(int val); + +#ifdef XF86DRI +extern Bool R128DRIScreenInit(ScreenPtr pScreen); +extern void R128DRICloseScreen(ScreenPtr pScreen); +extern Bool R128DRIFinishScreenInit(ScreenPtr pScreen); +extern void R128DRICCEInitRingBuffer(ScrnInfoPtr pScrn); +extern void R128CCEStart(ScrnInfoPtr pScrn); +extern void R128CCEStop(ScrnInfoPtr pScrn); +#endif + #endif diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_accel.c b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_accel.c index 5b0223661..b9a3b2af4 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_accel.c +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_accel.c @@ -1,8 +1,8 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/r128/r128_accel.c,v 1.7 2000/02/23 04:47:18 martin Exp $ */ /************************************************************************** -Copyright 1999 ATI Technologies Inc. and Precision Insight, Inc., - Cedar Park, Texas. +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -95,6 +95,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* DDC support */ #include "xf86DDC.h" + /* DRI support */ +#ifdef XF86DRI +#include "GL/glxint.h" +#include "xf86drm.h" +#include "sarea.h" +#define _XF86DRI_SERVER_ +#include "xf86dri.h" +#include "dri.h" +#include "r128_dri.h" +#include "r128_dripriv.h" +#include "r128_sarea.h" +#endif + /* Driver data structures */ #include "r128.h" #include "r128_reg.h" @@ -122,7 +135,7 @@ static struct { }; /* Flush all dirty data in the Pixel Cache to memory. */ -static void R128EngineFlush(ScrnInfoPtr pScrn) +void R128EngineFlush(ScrnInfoPtr pScrn) { int i; R128MMIO_VARS(); @@ -134,7 +147,7 @@ static void R128EngineFlush(ScrnInfoPtr pScrn) } /* Reset graphics card to known state. */ -static void R128EngineReset(ScrnInfoPtr pScrn) +void R128EngineReset(ScrnInfoPtr pScrn) { CARD32 clock_cntl_index; CARD32 mclk_cntl; @@ -160,15 +173,9 @@ static void R128EngineReset(ScrnInfoPtr pScrn) OUTREG(R128_GEN_RESET_CNTL, gen_reset_cntl); } -#define R128WaitForFifo(pScrn, entries) \ -do { \ - if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \ - info->fifo_slots -= entries; \ -} while (0) - /* The FIFO has 64 slots. This routines waits until at least `entries' of these slots are empty. */ -static void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries) +void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries) { R128InfoPtr info = R128PTR(pScrn); int i; @@ -192,7 +199,7 @@ static void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries) /* Wait for the graphics engine to be completely idle: the FIFO has drained, the Pixel Cache is flushed, and the engine is idle. This is a standard "sync" function that will make the hardware "quiescent". */ -static void R128WaitForIdle(ScrnInfoPtr pScrn) +void R128WaitForIdle(ScrnInfoPtr pScrn) { int i; R128MMIO_VARS(); @@ -969,16 +976,20 @@ void R128EngineInit(ScrnInfoPtr pScrn) R128WaitForIdle(pScrn); } -/* Initialize XAA for supported acceleration and also initialize the - graphics hardware for acceleration. */ -Bool R128AccelInit(ScreenPtr pScreen) +#if 0 +#ifdef XF86DRI + /* FIXME: When direct rendering is enabled, we should use the CCE to + draw 2D commands */ +static void R128CCEAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; - R128InfoPtr info = R128PTR(pScrn); - XAAInfoRecPtr a; +} +#endif +#endif + +static void R128MMIOAccelInit(ScrnInfoPtr pScrn, XAAInfoRecPtr a) +{ + R128InfoPtr info = R128PTR(pScrn); - if (!(a = info->accel = XAACreateInfoRec())) return FALSE; - a->Flags = (PIXMAP_CACHE | OFFSCREEN_PIXMAPS | LINEAR_FRAMEBUFFER); @@ -1065,7 +1076,28 @@ Bool R128AccelInit(ScreenPtr pScreen) | SCANLINE_PAD_DWORD | SYNC_AFTER_IMAGE_WRITE); #endif - +} + +/* Initialize XAA for supported acceleration and also initialize the + graphics hardware for acceleration. */ +Bool R128AccelInit(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr info = R128PTR(pScrn); + XAAInfoRecPtr a; + + if (!(a = info->accel = XAACreateInfoRec())) return FALSE; + +#if 0 +#ifdef XF86DRI + /* FIXME: When direct rendering is enabled, we should use the CCE to + draw 2D commands */ + if (info->directRenderingEnabled) R128CCEAccelInit(pScrn, a); + else +#endif +#endif + R128MMIOAccelInit(pScrn, a); + R128EngineInit(pScrn); return XAAInit(pScreen, a); } diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_cursor.c b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_cursor.c index a96872702..517f63a86 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_cursor.c +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_cursor.c @@ -1,8 +1,8 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/r128/r128_cursor.c,v 1.6 2000/03/06 22:59:26 dawes Exp $ */ /************************************************************************** -Copyright 1999 ATI Technologies Inc. and Precision Insight, Inc., - Cedar Park, Texas. +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -60,6 +60,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* DDC support */ #include "xf86DDC.h" + /* DRI support */ +#ifdef XF86DRI +#include "GL/glxint.h" +#include "xf86drm.h" +#include "sarea.h" +#define _XF86DRI_SERVER_ +#include "xf86dri.h" +#include "dri.h" +#include "r128_dri.h" +#include "r128_dripriv.h" +#include "r128_sarea.h" +#endif + /* Driver data structures */ #include "r128.h" #include "r128_reg.h" diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.c b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.c new file mode 100644 index 000000000..f5e5aefb8 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.c @@ -0,0 +1,919 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * Rickard E. Faith <faith@precisioninsight.com> + * Daryll Strauss <daryll@precisioninsight.com> + * + */ + + + /* X and server generic header files */ +#include "xf86.h" +#include "xf86_ansic.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86RAC.h" +#include "xf86cmap.h" +#include "xf86fbman.h" + + /* Backing store, software cursor, and + colormap initialization */ +#include "mibstore.h" +#include "mipointer.h" +#include "micmap.h" + + /* CFB support */ +#define PSZ 8 +#include "cfb.h" +#undef PSZ +#include "cfb16.h" +#include "cfb24.h" +#include "cfb32.h" +#include "cfb24_32.h" + + /* XAA and Cursor Support */ +#include "xaa.h" +#include "xf86Cursor.h" + + /* PCI support */ +#include "xf86PciInfo.h" +#include "xf86Pci.h" + + /* DDC support */ +#include "xf86DDC.h" + + /* DRI support */ +#include "GL/glxint.h" +#include "xf86drm.h" +#include "sarea.h" +#define _XF86DRI_SERVER_ +#include "xf86dri.h" +#include "dri.h" +#include "r128_dri.h" +#include "r128_sarea.h" +#include "r128_dripriv.h" + + /* Driver data structures */ +#include "r128.h" +#include "r128_reg.h" + +#define R128_WATERMARK_L 16 +#define R128_WATERMARK_M 8 +#define R128_WATERMARK_N 8 +#define R128_WATERMARK_K 128 + +static int CCEFifoSlots = 0; + +#define R128CCEWaitForFifo(pScrn, entries) \ +do { \ + if (CCEFifoSlots < entries) R128WaitForFifoFunction(pScrn, entries); \ + CCEFifoSlots -= entries; \ +} while (0) + +/* Wait for at least `entries' slots are free. The actual number of + slots available is stored in info->CCEFifoSize. */ +static void R128CCEWaitForFifoFunction(ScrnInfoPtr pScrn, int entries) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + int i; + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + CCEFifoSlots = INREG(R128_PM4_STAT) & R128_PM4_FIFOCNT_MASK; + if (CCEFifoSlots >= entries) return; + } + R128EngineReset(pScrn); + } +} + +/* Wait until the CCE is completely idle: the FIFO has drained and the + CCE is idle. */ +static void R128CCEWaitForIdle(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + int i; + + R128CCEWaitForFifoFunction(pScrn, info->CCEFifoSize); + + for (;;) { + for (i = 0; i < R128_TIMEOUT; i++) { + if (!(INREG(R128_PM4_STAT) + & (R128_PM4_BUSY | R128_PM4_GUI_ACTIVE))) { + R128EngineFlush(pScrn); + return; + } + } + R128EngineReset(pScrn); + } +} + +/* Start the CCE, but only if it is not already in use and the requested + mode is a CCE mode. The mode is stored in info->CCEMode. */ +void R128CCEStart(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + if (info->CCEInUse || info->CCEMode == R128_PM4_NONPM4) return; + + R128WaitForIdle(pScrn); + OUTREG(R128_PM4_BUFFER_CNTL, info->CCEMode); + (void)INREG(R128_PM4_BUFFER_ADDR); /* as per the sample code */ + OUTREG(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); + info->CCEInUse = TRUE; +} + +/* Stop the CCE, but only if it is in use and the requested mode is not + the non-CCE mode. This function also flushes any outstanding + requests before switching modes.*/ +void R128CCEStop(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + + if (!info->CCEInUse || info->CCEMode == R128_PM4_NONPM4) return; + + R128CCEWaitForIdle(pScrn); +#if 0 + /* FIXME: This is needed when we use the ring buffer to flush any + unfinished commands */ + OUTREGP(R128_PM4_BUFFER_DL_WPTR, + R128_PM4_BUFFER_DL_DONE, ~R128_PM4_BUFFER_DL_DONE); +#endif + OUTREG(R128_PM4_MICRO_CNTL, 0); + OUTREG(R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4); + info->CCEInUse = FALSE; +} + +/* Initialize the visual configs that are supported by the hardware. + These are combined with the visual configs that the indirect + rendering core supports, and the intersection is exported to the + client. */ +static Bool R128InitVisualConfigs(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr pR128 = R128PTR(pScrn); + int numConfigs = 0; + __GLXvisualConfig *pConfigs = 0; + R128ConfigPrivPtr pR128Configs = 0; + R128ConfigPrivPtr *pR128ConfigPtrs = 0; + int i; + + switch (pR128->pixel_code) { + case 8: /* 8bpp mode is not support */ + case 15: /* FIXME */ + case 24: /* FIXME */ + return FALSE; + + case 16: + case 32: + numConfigs = 4; + + if (!(pConfigs + = (__GLXvisualConfig*)xnfcalloc(sizeof(__GLXvisualConfig), + numConfigs))) { + return FALSE; + } + if (!(pR128Configs + = (R128ConfigPrivPtr)xnfcalloc(sizeof(R128ConfigPrivRec), + numConfigs))) { + xfree(pConfigs); + return FALSE; + } + if (!(pR128ConfigPtrs + = (R128ConfigPrivPtr*)xnfcalloc(sizeof(R128ConfigPrivPtr), + numConfigs))) { + xfree(pConfigs); + xfree(pR128Configs); + return FALSE; + } + + for (i = 0; i < numConfigs; i++) { + pR128ConfigPtrs[i] = &pR128Configs[i]; + + pConfigs[i].vid = -1; + pConfigs[i].class = -1; + pConfigs[i].rgba = TRUE; + if (pScrn->depth == 16) { + pConfigs[i].redSize = 5; + pConfigs[i].greenSize = 6; + pConfigs[i].blueSize = 5; + pConfigs[i].redMask = 0x0000F800; + pConfigs[i].greenMask = 0x000007E0; + pConfigs[i].blueMask = 0x0000001F; + } else { + pConfigs[i].redSize = 8; + pConfigs[i].greenSize = 8; + pConfigs[i].blueSize = 8; + pConfigs[i].redMask = 0x00FF0000; + pConfigs[i].greenMask = 0x0000FF00; + pConfigs[i].blueMask = 0x000000FF; + } + pConfigs[i].alphaMask = 0; + pConfigs[i].accumRedSize = 0; + pConfigs[i].accumGreenSize = 0; + pConfigs[i].accumBlueSize = 0; + pConfigs[i].accumAlphaSize = 0; + pConfigs[i].doubleBuffer = TRUE; + pConfigs[i].stereo = FALSE; + pConfigs[i].bufferSize = pScrn->depth; + pConfigs[i].depthSize = 16; /* FIXME: Support other depth */ + pConfigs[i].stencilSize = 0; /* buffer depths with the new */ + pConfigs[i].auxBuffers = 0; /* Mesa code. */ + pConfigs[i].level = 0; + pConfigs[i].visualRating = 0; + pConfigs[i].transparentPixel = 0; + pConfigs[i].transparentRed = 0; + pConfigs[i].transparentGreen = 0; + pConfigs[i].transparentBlue = 0; + pConfigs[i].transparentAlpha = 0; + pConfigs[i].transparentIndex = 0; + } + + /* Turn off double buffer support for certain visuals */ + pConfigs[1].doubleBuffer = FALSE; + pConfigs[3].doubleBuffer = FALSE; + + /* Turn off depth buffer support for certain visuals */ + pConfigs[2].depthSize = 0; + pConfigs[3].depthSize = 0; + break; + } + + pR128->numVisualConfigs = numConfigs; + pR128->pVisualConfigs = pConfigs; + pR128->pVisualConfigsPriv = pR128Configs; + GlxSetVisualConfigs(numConfigs, pConfigs, (void**)pR128ConfigPtrs); + return TRUE; +} + +/* Create the Rage 128-specific context information */ +static Bool R128CreateContext(ScreenPtr pScreen, VisualPtr visual, + drmContext hwContext, void *pVisualConfigPriv, + DRIContextType contextStore) +{ + /* Nothing yet */ + return TRUE; +} + +/* Destroy the Rage 128-specific context information */ +static void R128DestroyContext(ScreenPtr pScreen, drmContext hwContext, + DRIContextType contextStore) +{ + /* Nothing yet */ +} + +/* Called when the X server is woken up to allow the last client's + context to be saved and the X server's context to be loaded. This is + not necessary for the Rage 128 since the client detects when it's + context is not currently loaded and then load's it itself. Since the + registers to start and stop the CCE are privileged, only the X server + can start/stop the engine. */ +static void R128EnterServer(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + +#if 1 + /* FIXME: When the CCE is used for 2D drawing in the X server, we + will not need to stop/start the CCE when entering/leaving the X + server. */ + R128CCEStop(pScrn); +#else + R128CCEWaitForIdle(pScrn); +#endif +} + +/* Called when the X server goes to sleep to allow the X server's + context to be saved and the last client's context to be loaded. This + is not necessary for the Rage 128 since the client detects when it's + context is not currently loaded and then load's it itself. Since the + registers to start and stop the CCE are privileged, only the X server + can start/stop the engine. */ +static void R128LeaveServer(ScreenPtr pScreen) +{ +#if 1 + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + + /* FIXME: When the CCE is used for 2D drawing in the X server, we + will not need to stop/start the CCE when entering/leaving the X + server. */ + R128CCEStart(pScrn); +#endif +} + +/* Contexts can be swapped by the X server if necessary. This callback + is currently only used to perform any functions necessary when + entering or leaving the X server, and in the future might not be + necessary. */ +static void R128DRISwapContext(ScreenPtr pScreen, DRISyncType syncType, + DRIContextType oldContextType, void *oldContext, + DRIContextType newContextType, void *newContext) +{ + if ((syncType==DRI_3D_SYNC) && (oldContextType==DRI_2D_CONTEXT) && + (newContextType==DRI_2D_CONTEXT)) { /* Entering from Wakeup */ + R128EnterServer(pScreen); + } + if ((syncType==DRI_2D_SYNC) && (oldContextType==DRI_NO_CONTEXT) && + (newContextType==DRI_2D_CONTEXT)) { /* Exiting from Block Handler */ + R128LeaveServer(pScreen); + } +} + +/* Initialize the state of the back and depth buffers. */ +static void R128DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 index) +{ +#if 0 + /* FIXME: This routine needs to have acceleration turned on */ + ScreenPtr pScreen = pWin->drawable.pScreen; + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr pR128 = R128PTR(pScrn); + BoxPtr pbox; + int nbox; + + /* FIXME: Copy XAAPaintWindow() and use REGION_TRANSLATE() */ + /* FIXME: Only initialize the back and depth buffers for contexts + that request them */ + + pbox = REGION_RECTS(prgn); + nbox = REGION_NUM_RECTS(prgn); + + (*pR128->accel->SetupForSolidFill)(pScrn, 0, GXcopy, -1); + for (; nbox; nbox--, pbox++) { + (*pR128->accel->SubsequentSolidFillRect)(pScrn, + pbox->x1 + pR128->backX, + pbox->y1 + pR128->backY, + pbox->x2 - pbox->x1, + pbox->y2 - pbox->y1); + (*pR128->accel->SubsequentSolidFillRect)(pScrn, + pbox->x1 + pR128->depthX, + pbox->y1 + pR128->depthY, + pbox->x2 - pbox->x1, + pbox->y2 - pbox->y1); + } + + pR128->accel->NeedToSync = TRUE; +#endif +} + +/* Copy the back and depth buffers when the X server moves a window. */ +static void R128DRIMoveBuffers(WindowPtr pWin, DDXPointRec ptOldOrg, + RegionPtr prgnSrc, CARD32 index) +{ + /* FIXME: This routine needs to have acceleration turned on */ + /* FIXME: Copy XAACopyWindow() and use REGION_TRANSLATE() */ + /* FIXME: Only initialize the back and depth buffers for contexts + that request them */ +} + +/* Initialize the AGP state. Request memory for use in AGP space, and + initialize the Rage 128 registers to point to that memory. */ +static Bool R128DRIAgpInit(R128InfoPtr pR128, ScreenPtr pScreen) +{ + unsigned char *R128MMIO = pR128->MMIO; + unsigned long mode; + unsigned int vendor, device; + int ret; + unsigned long cntl; + + if (drmAgpAcquire(pR128->drmFD) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not available\n"); + return FALSE; + } + + /* Modify the mode if the default mode is + not appropriate for this particular + combination of graphics card and AGP + chipset. */ + + mode = drmAgpGetMode(pR128->drmFD); /* Default mode */ + vendor = drmAgpVendorId(pR128->drmFD); + device = drmAgpDeviceId(pR128->drmFD); + +#if 0 + /* FIXME: This turns off AGP 2X mode */ + /* FIXME: Make this configurable */ + mode &= ~0x00000002; +#endif + + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n", + mode, vendor, device, + pR128->PciInfo->vendor, + pR128->PciInfo->chipType); + + if (drmAgpEnable(pR128->drmFD, mode) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n"); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + + /* FIXME: This size was chosen arbitrarily -- make it configurable */ + pR128->agpSize = 8 * 1024 * 1024; + if ((ret = drmAgpAlloc(pR128->drmFD, pR128->agpSize, 0, NULL, + &pR128->agpMemHandle)) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Out of memory (%d)\n", ret); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] %d kB allocated with handle 0x%08x\n", + pR128->agpSize / 1024, pR128->agpMemHandle); + + pR128->agpOffset = 0; + if (drmAgpBind(pR128->drmFD, pR128->agpMemHandle, pR128->agpOffset) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not bind\n"); + drmAgpFree(pR128->drmFD, pR128->agpMemHandle); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + if (drmAddMap(pR128->drmFD, pR128->agpOffset, pR128->agpSize, + DRM_AGP, 0, &pR128->agpHandle) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not add mapping\n"); + drmAgpFree(pR128->drmFD, pR128->agpMemHandle); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] handle = 0x%08lx\n", pR128->agpHandle); + + if (drmMap(pR128->drmFD, pR128->agpHandle, pR128->agpSize, + (drmAddressPtr)&pR128->AGP) < 0) { + xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map\n"); + drmAgpFree(pR128->drmFD, pR128->agpMemHandle); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + xf86DrvMsg(pScreen->myNum, X_INFO, + "[agp] Aperture mapped at 0x%08lx\n", + (unsigned long)pR128->AGP); + + /* Initialize Rage 128's AGP registers */ + cntl = INREG(R128_AGP_CNTL); + cntl &= ~R128_AGP_APER_SIZE_MASK; + switch (pR128->agpSize) { + case 256*1024*1024: cntl |= R128_AGP_APER_SIZE_256MB; break; + case 128*1024*1024: cntl |= R128_AGP_APER_SIZE_128MB; break; + case 64*1024*1024: cntl |= R128_AGP_APER_SIZE_64MB; break; + case 32*1024*1024: cntl |= R128_AGP_APER_SIZE_32MB; break; + case 16*1024*1024: cntl |= R128_AGP_APER_SIZE_16MB; break; + case 8*1024*1024: cntl |= R128_AGP_APER_SIZE_8MB; break; + case 4*1024*1024: cntl |= R128_AGP_APER_SIZE_4MB; break; + default: + xf86DrvMsg(pScreen->myNum, X_ERROR, + "[agp] Illegal aperture size %d kB\n", + pR128->agpSize / 1024); + drmUnmap(pR128->AGP, pR128->agpSize); + pR128->AGP = NULL; + drmAgpFree(pR128->drmFD, pR128->agpMemHandle); + drmAgpRelease(pR128->drmFD); + return FALSE; + } + OUTREG(R128_AGP_BASE, pR128->agpHandle); + OUTREG(R128_AGP_CNTL, cntl); + + return TRUE; +} + +/* Add a map for the MMIO registers that will be accessed by any + DRI-based clients. */ +static Bool R128DRIMapInit(R128InfoPtr pR128, ScreenPtr pScreen) +{ + /* Map registers */ + pR128->registerSize = R128_MMIOSIZE; + if (drmAddMap(pR128->drmFD, pR128->MMIOAddr, pR128->registerSize, + DRM_REGISTERS, 0, &pR128->registerHandle) < 0) { + return FALSE; + } + xf86DrvMsg(pScreen->myNum, X_INFO, + "[drm] register handle = 0x%08lx\n", pR128->registerHandle); + + return TRUE; +} + +/* Load the microcode for the CCE */ +static void R128DRILoadMicrocode(ScrnInfoPtr pScrn) +{ + unsigned char *R128MMIO = R128PTR(pScrn)->MMIO; + int i; + unsigned long R128Microcode[] = { + /* CCE microcode (from ATI) */ + 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 1617039951, + 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 599558925, 0, 589505315, 0, + 596487092, 0, 589505315, 1, 11544576, 1, 206848, 1, 311296, 1, 198656, 2, + 912273422, 11, 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, + 28, 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 30, 1, + 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 1, 15630, 1, 51200, + 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 15717, 1, 15718, 2, 43, 1, + 15936948, 1, 570480831, 1, 14715071, 12, 322123831, 1, 33953125, 12, 55, 1, + 33559908, 1, 15718, 2, 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, + 509952, 1, 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, + 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 15975928, 1, + 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 268449859, 2, 10307, 12, + 176, 1, 15734, 1, 15735, 1, 15630, 1, 15631, 1, 5253120, 6, 3145810, 16, + 2150645232U, 1, 15864, 2, 82, 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, + 1, 7817, 1, 15729, 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, + 1, 16008, 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, + 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 180224, 1, + 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 114880, 14, 125, 12, + 206975, 1, 33559995, 12, 198784, 0, 33570236, 1, 15803, 0, 15804, 3, + 294912, 1, 294912, 3, 442370, 1, 11544576, 0, 811612160, 1, 12593152, 1, + 11536384, 1, 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, + 14793, 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, + 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 114880, 14, + 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 1107312059, 12, 198784, 1, + 1109409212, 2, 162, 1, 1075854781, 1, 1073757627, 1, 1075854780, 1, 540672, + 1, 10485760, 6, 3145894, 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, + 0, 0, 256, 14, 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, + 1, 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 33560360, 1, + 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 409611, 9, 188, 0, + 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0 + }; + + R128WaitForIdle(pScrn); + + OUTREG(R128_PM4_MICROCODE_ADDR, 0); + for (i = 0; i < 256; i += 1) { + OUTREG(R128_PM4_MICROCODE_DATAH, R128Microcode[i*2]); + OUTREG(R128_PM4_MICROCODE_DATAL, R128Microcode[i*2 + 1]); + } +} + +/* Initialize the CCE state, and reserve space in AGP memory for the + ring, vertex, indirect buffers (if used by the current CCEMode. + Allow the rest of AGP memory to be used for textures. */ +static void R128DRICCEInit(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + int s, l; + +/* FIXME: These sizes ware chosen arbitrarily -- make them configurable */ +/* NOTE: These must be page aligned */ +#define RING_SIZE 1*1024*1024 +#define VERTBUF_SIZE 1*1024*1024 +#define INDBUF_SIZE 1*1024*1024 + + /* FIXME: Currently, the ring, vertex and indirect buffers all take + space, even when the CCEMode does not use them. Make the use of + AGP space configurable by only reserving space for the buffers + that are required for the current CCEMode. */ + + /* Initialize the CCE ring buffer data */ + info->ringStart = 0; + info->ringSize = RING_SIZE; + info->ringWrite = 0; + info->ringReadOffset = info->ringStart + info->ringSize + 4096; + + /* Reserve space for the vertex buffer */ + info->vbStart = info->ringReadOffset + 4096; + info->vbSize = VERTBUF_SIZE; + + /* Reserve space for the indirect buffer */ + info->indStart = info->vbStart + info->vbSize; + info->indSize = INDBUF_SIZE; + + /* Reserve the rest for AGP textures */ + info->agpTexStart = info->indStart + info->indSize; + s = (info->agpSize - info->agpTexStart); + l = R128MinBits((s-1) / R128_NR_TEX_REGIONS); + if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY; + info->agpTexSize = (s >> l) << l; + info->log2AGPTexGran = l; + + /* Initialize the CCE ring buffer FIFO size */ + info->CCEInUse = FALSE; + info->CCEMode = R128_CCE_MODE; + switch (info->CCEMode) { + case R128_PM4_NONPM4: info->CCEFifoSize = 0; break; + case R128_PM4_192PIO: info->CCEFifoSize = 192; break; + case R128_PM4_192BM: info->CCEFifoSize = 192; break; + case R128_PM4_128PIO_64INDBM: info->CCEFifoSize = 128; break; + case R128_PM4_128BM_64INDBM: info->CCEFifoSize = 128; break; + case R128_PM4_64PIO_128INDBM: info->CCEFifoSize = 64; break; + case R128_PM4_64BM_128INDBM: info->CCEFifoSize = 64; break; + case R128_PM4_64PIO_64VCBM_64INDBM: info->CCEFifoSize = 64; break; + case R128_PM4_64BM_64VCBM_64INDBM: info->CCEFifoSize = 64; break; + case R128_PM4_64PIO_64VCPIO_64INDPIO: info->CCEFifoSize = 64; break; + } +} + +/* Initialize the ring buffer state for use in the X server and any + DRI-based clients. */ +void R128DRICCEInitRingBuffer(ScrnInfoPtr pScrn) +{ + R128InfoPtr info = R128PTR(pScrn); + unsigned char *R128MMIO = info->MMIO; + unsigned long addr; + + /* FIXME: When we use the CCE for the X server, we should move this + function (and the support functions above) to r128_accel.c */ + + /* Initialize CCE data */ + R128DRICCEInit(pScrn); + + /* The manual (p. 2) says this address is + in "VM space". This means it's an + offset from the start of AGP space. */ + OUTREG(R128_PM4_BUFFER_OFFSET, info->ringStart | 0x02000000); + + OUTREG(R128_PM4_BUFFER_DL_WPTR, 0); + OUTREG(R128_PM4_BUFFER_DL_RPTR, 0); + +#if 1 + OUTREG(R128_PM4_BUFFER_DL_RPTR_ADDR, 0x00000000); +#else + /* DL_RPTR_ADDR is a physical address. + This should be in the SAREA. */ + *(volatile long unsigned *)(info->AGP + info->ringReadOffset) = 0; + OUTREG(R128_PM4_BUFFER_DL_RPTR_ADDR, (info->agpHandle + + info->ringReadOffset)); +#endif + + /* Set watermark control */ + OUTREG(R128_PM4_BUFFER_WM_CNTL, + ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) + | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) + | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) + | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT)); + + addr = INREG(R128_PM4_BUFFER_ADDR); /* Force read. Why? Because it's + in the examples... */ + + R128CCEWaitForIdle(pScrn); + + /* Turn on bus mastering */ + OUTREGP(R128_BUS_CNTL, 0, ~R128_BUS_MASTER_DIS); + +#if 0 + /* FIXME: If we use the CCE ring buffer for the X server, we need to + start the engine here for the X server. */ +#else + /* Make sure the CCE is off for the X server */ + OUTREG(R128_PM4_MICRO_CNTL, 0); + OUTREG(R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4); +#endif +} + +/* Initialize the screen-specific data structures for the DRI and the + Rage 128. This is the main entry point to the device-specific + initialization code. It calls device-independent DRI functions to + create the DRI data structures and initialize the DRI state. */ +Bool R128DRIScreenInit(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr pR128 = R128PTR(pScrn); + DRIInfoPtr pDRIInfo; + R128DRIPtr pR128DRI; + + switch (pR128->pixel_code) { + case 8: + /* These modes are not supported (yet). */ + case 15: + case 24: + return FALSE; + + /* Only 16 and 32 color depths are supports currently. */ + case 16: + case 32: + break; + } + + /* Create the DRI data structure, and fill it in before calling the + DRIScreenInit(). */ + if (!(pDRIInfo = DRICreateInfoRec())) return FALSE; + + pR128->pDRIInfo = pDRIInfo; + pDRIInfo->drmDriverName = R128_NAME; + pDRIInfo->clientDriverName = R128_NAME; + pDRIInfo->busIdString = xalloc(64); + sprintf(pDRIInfo->busIdString, + "PCI:%d:%d:%d", + pR128->PciInfo->bus, + pR128->PciInfo->device, + pR128->PciInfo->func); + pDRIInfo->ddxDriverMajorVersion = R128_VERSION_MAJOR; + pDRIInfo->ddxDriverMinorVersion = R128_VERSION_MINOR; + pDRIInfo->ddxDriverPatchVersion = R128_VERSION_PATCH; + pDRIInfo->frameBufferPhysicalAddress = pR128->LinearAddr; + pDRIInfo->frameBufferSize = pR128->FbMapSize; + pDRIInfo->frameBufferStride = (pScrn->displayWidth + * pR128->pixel_bytes); + pDRIInfo->ddxDrawableTableEntry = R128_MAX_DRAWABLES; + pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES + < R128_MAX_DRAWABLES + ? SAREA_MAX_DRAWABLES + : R128_MAX_DRAWABLES); + +#ifdef NOT_DONE + /* FIXME need to extend DRI protocol to pass this size back to client + * for SAREA mapping that includes a device private record + */ + pDRIInfo->SAREASize = + ((sizeof(XF86DRISAREARec) + 0xfff) & 0x1000); /* round to page */ + /* + shared memory device private rec */ +#else + /* For now the mapping works by using a fixed size defined + * in the SAREA header + */ + if (sizeof(XF86DRISAREARec)+sizeof(R128SAREAPriv)>SAREA_MAX) { + ErrorF("Data does not fit in SAREA\n"); + return FALSE; + } + pDRIInfo->SAREASize = SAREA_MAX; +#endif + + if (!(pR128DRI = (R128DRIPtr)xnfcalloc(sizeof(R128DRIRec),1))) { + DRIDestroyInfoRec(pR128->pDRIInfo); + pR128->pDRIInfo = NULL; + return FALSE; + } + pDRIInfo->devPrivate = pR128DRI; + pDRIInfo->devPrivateSize = sizeof(R128DRIRec); + pDRIInfo->contextSize = sizeof(R128DRIContextRec); + + pDRIInfo->CreateContext = R128CreateContext; + pDRIInfo->DestroyContext = R128DestroyContext; + pDRIInfo->SwapContext = R128DRISwapContext; + pDRIInfo->InitBuffers = R128DRIInitBuffers; + pDRIInfo->MoveBuffers = R128DRIMoveBuffers; + pDRIInfo->bufferRequests = DRI_ALL_WINDOWS; + + if (!DRIScreenInit(pScreen, pDRIInfo, &pR128->drmFD)) { + xfree(pDRIInfo->devPrivate); + pDRIInfo->devPrivate = NULL; + DRIDestroyInfoRec(pDRIInfo); + pDRIInfo = NULL; + return FALSE; + } + + /* Initialize AGP */ + if (!R128DRIAgpInit(pR128, pScreen)) { + R128DRICloseScreen(pScreen); + return FALSE; + } + + /* DRIScreenInit doesn't make add all the + common mappings. Add additional + mappings here, including the one for + AGP. */ + if (!R128DRIMapInit(pR128, pScreen)) { + R128DRICloseScreen(pScreen); + return FALSE; + } + + /* FIXME! When are these mappings unmapped? */ + + if (!R128InitVisualConfigs(pScreen)) { + R128DRICloseScreen(pScreen); + return FALSE; + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Visual configs initialized\n" ); + + /* Load the CCE Microcode */ + R128DRILoadMicrocode(pScrn); + + /* Reset the Graphics Engine */ + R128EngineReset(pScrn); + + return TRUE; +} + +/* Finish initializing the device-dependent DRI state, and call + DRIFinishScreenInit() to complete the device-independent DRI + initialization. */ +Bool R128DRIFinishScreenInit(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr pR128 = R128PTR(pScrn); + R128SAREAPrivPtr pSAREAPriv; + R128DRIPtr pR128DRI; + + pSAREAPriv = (R128SAREAPrivPtr)DRIGetSAREAPrivate(pScreen); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + + R128DRICCEInitRingBuffer(pScrn); + /* FIXME: R128CCEStart(pScrn); */ + + pR128->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT; + /* pR128->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */ + + pR128DRI = (R128DRIPtr)pR128->pDRIInfo->devPrivate; + pR128DRI->registerHandle = pR128->registerHandle; + pR128DRI->registerSize = pR128->registerSize; + pR128DRI->agpHandle = pR128->agpHandle; + pR128DRI->agpSize = pR128->agpSize; + + pR128DRI->deviceID = pR128->Chipset; + pR128DRI->width = pScrn->virtualX; + pR128DRI->height = pScrn->virtualY; + pR128DRI->depth = pScrn->depth; + pR128DRI->bpp = pScrn->bitsPerPixel; + + pR128DRI->fbX = pR128->fbX; + pR128DRI->fbY = pR128->fbY; + pR128DRI->backX = pR128->backX; + pR128DRI->backY = pR128->backY; + pR128DRI->depthX = pR128->depthX; + pR128DRI->depthY = pR128->depthY; + pR128DRI->textureX = pR128->textureX; + pR128DRI->textureY = pR128->textureY; + pR128DRI->textureSize = pR128->textureSize; + pR128DRI->log2TexGran = pR128->log2TexGran; + + pR128DRI->CCEMode = pR128->CCEMode; + pR128DRI->CCEFifoSize = pR128->CCEFifoSize; + + pR128DRI->ringStart = pR128->ringStart; + pR128DRI->ringSize = pR128->ringSize; + pR128DRI->ringWrite = pR128->ringWrite; + pR128DRI->ringReadOffset = pR128->ringReadOffset; + + pR128DRI->vbStart = pR128->vbStart; + pR128DRI->vbSize = pR128->vbSize; + + pR128DRI->indStart = pR128->indStart; + pR128DRI->indSize = pR128->indSize; + + pR128DRI->agpTexStart = pR128->agpTexStart; + pR128DRI->agpTexSize = pR128->agpTexSize; + pR128DRI->log2AGPTexGran = pR128->log2AGPTexGran; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%08lx %d\n", + pR128DRI->registerHandle, pR128DRI->registerSize); + return DRIFinishScreenInit(pScreen); +} + +/* The screen is being closed, so clean up any state and free any + resources used by the DRI. */ +void R128DRICloseScreen(ScreenPtr pScreen) +{ + ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + R128InfoPtr pR128 = R128PTR(pScrn); + + /* De-allocate all AGP resources */ + if (pR128->AGP) { + drmUnmap(pR128->AGP, pR128->agpSize); + pR128->AGP = NULL; + } + if (pR128->agpMemHandle) { + drmAgpUnbind(pR128->drmFD, pR128->agpMemHandle); + drmAgpFree(pR128->drmFD, pR128->agpMemHandle); + pR128->agpMemHandle = 0; + drmAgpRelease(pR128->drmFD); + } + + /* De-allocate all DRI resources */ + DRICloseScreen(pScreen); + + /* De-allocate all DRI data structures */ + if (pR128->pDRIInfo) { + if (pR128->pDRIInfo->devPrivate) { + xfree(pR128->pDRIInfo->devPrivate); + pR128->pDRIInfo->devPrivate = NULL; + } + DRIDestroyInfoRec(pR128->pDRIInfo); + pR128->pDRIInfo = NULL; + } + if (pR128->pVisualConfigs) { + xfree(pR128->pVisualConfigs); + pR128->pVisualConfigs = NULL; + } + if (pR128->pVisualConfigsPriv) { + xfree(pR128->pVisualConfigsPriv); + pR128->pVisualConfigsPriv = NULL; + } +} diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.h new file mode 100644 index 000000000..911cde1b5 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dri.h @@ -0,0 +1,99 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * Rickard E. Faith <faith@precisioninsight.com> + * + */ + +#ifndef _R128_DRI_ +#define _R128_DRI_ + +#include <xf86drm.h> + +/* The CCE will default to the following mode: */ +#define R128_CCE_MODE R128_PM4_64PIO_64VCBM_64INDBM + +typedef struct { + /* FIXME: There needs to be two register regions. One to allow + read-only access to the block of non-FIFO'd GUI registers + (0x0000-0x0FFC), and one to allow read/write acces to the block + of FIFO'd GUI registers (0x1000-0x1FFC) */ + + /* MMIO register data */ + drmHandle registerHandle; + drmSize registerSize; + + /* AGP data */ + drmHandle agpHandle; + drmSize agpSize; + + /* DRI screen private data */ + int deviceID; /* PCI device ID */ + int width; /* Width in pixels of display */ + int height; /* Height in scanlines of display */ + int depth; /* Depth of display (8, 15, 16, 24) */ + int bpp; /* Bit depth of display (8, 16, 24, 32) */ + + int fbX; /* Start of frame buffer */ + int fbY; + int backX; /* Start of shared back buffer */ + int backY; + int depthX; /* Start of shared depth buffer */ + int depthY; + int textureX; /* Start of texture data in frame buffer */ + int textureY; + int textureSize; + int log2TexGran; + + int CCEMode; /* CCE mode that server/clients use */ + int CCEFifoSize; /* Size of the CCE command FIFO */ + + /* CCE ring buffer data */ + unsigned long ringStart; + int ringSize; + int ringWrite; + unsigned long ringReadOffset; + + /* CCE vertex buffer data */ + unsigned long vbStart; + int vbSize; + + /* CCE indirect buffer data */ + unsigned long indStart; + int indSize; + + /* CCE AGP Texture data */ + unsigned long agpTexStart; + int agpTexSize; + int log2AGPTexGran; +} R128DRIRec, *R128DRIPtr; + +#endif diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dripriv.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dripriv.h new file mode 100644 index 000000000..acec5e269 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_dripriv.h @@ -0,0 +1,54 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Rickard E. Faith <faith@precisioninsight.com> + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_DRIPRIV_H_ +#define _R128_DRIPRIV_H_ + +#define R128_MAX_DRAWABLES 256 + +extern void GlxSetVisualConfigs(int nconfigs, __GLXvisualConfig *configs, + void **configprivs); + +typedef struct { + /* Nothing here yet */ + int dummy; +} R128ConfigPrivRec, *R128ConfigPrivPtr; + +typedef struct { + /* Nothing here yet */ + int dummy; +} R128DRIContextRec, *R128DRIContextPtr; + +#endif diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c index b5da4cb6e..79b0a8620 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c @@ -1,8 +1,8 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/r128/r128_driver.c,v 1.26 2000/03/06 23:17:44 martin Exp $ */ /************************************************************************** -Copyright 1999 ATI Technologies Inc. and Precision Insight, Inc., - Cedar Park, Texas. +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -107,6 +107,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* VESA support */ #include "vbe.h" + /* DRI support */ +#ifdef XF86DRI +#include "GL/glxint.h" +#include "xf86drm.h" +#include "sarea.h" +#define _XF86DRI_SERVER_ +#include "xf86dri.h" +#include "dri.h" +#include "r128_dri.h" +#include "r128_dripriv.h" +#include "r128_sarea.h" +#endif + /* Driver data structures */ #include "r128.h" #include "r128_reg.h" @@ -299,6 +312,38 @@ static const char *ramdacSymbols[] = { NULL }; +#ifdef XF86DRI +static const char *drmSymbols[] = { + "drmAddBufs", + "drmAddMap", + "drmAvailable", + "drmCtlAddCommand", + "drmCtlInstHandler", + "drmGetInterruptFromBusID", + "drmMapBufs", + "drmMarkBufs", + "drmUnmapBufs", + NULL +}; + +static const char *driSymbols[] = { + "DRIGetDrawableIndex", + "DRIFinishScreenInit", + "DRIDestroyInfoRec", + "DRICloseScreen", + "DRIDestroyInfoRec", + "DRIScreenInit", + "DRIDestroyInfoRec", + "DRICreateInfoRec", + "DRILock", + "DRIUnlock", + "DRIGetSAREAPrivate", + "DRIGetContext", + "GlxSetVisualConfigs", + NULL +}; +#endif + static MODULESETUPPROTO(R128Setup); static XF86ModuleVersionInfo R128VersRec = @@ -347,6 +392,10 @@ static pointer R128Setup(pointer module, pointer opts, int *errmaj, xaaSymbols, xf8_32bppSymbols, ramdacSymbols, +#ifdef XF86DRI + drmSymbols, + driSymbols, +#endif fbdevHWSymbols, vbeSymbols, 0 /* ddcsymbols */, @@ -518,7 +567,7 @@ static void R128Unblank(ScrnInfoPtr pScrn) } /* Compute log base 2 of val. */ -static int R128MinBits(int val) +int R128MinBits(int val) { int bits; @@ -779,6 +828,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) int offset = 0; /* RAM Type */ MessageType from; unsigned char *R128MMIO; + /* Chipset */ from = X_PROBED; if (dev->chipset && *dev->chipset) { @@ -895,7 +945,7 @@ static Bool R128PreInitConfig(ScrnInfoPtr pScrn) pScrn->videoRam); from = X_CONFIG; pScrn->videoRam = dev->videoRam; - } + } pScrn->videoRam &= ~1023; info->FbMapSize = pScrn->videoRam * 1024; xf86DrvMsg(pScrn->scrnIndex, from, @@ -1231,9 +1281,19 @@ static Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, R128TRACE(("R128ScreenInit %x %d\n", pScrn->memPhysBase, pScrn->fbOffset)); +#ifdef XF86DRI + /* Turn off the CCE for now. */ + info->CCEInUse = FALSE; + info->CCEMode = R128_PM4_NONPM4; +#endif + if (!R128MapMem(pScrn)) return FALSE; pScrn->fbOffset = 0; - +#ifdef XF86DRI + info->fbX = 0; + info->fbY = 0; +#endif + R128Save(pScrn); if (info->FBDev) { if (!fbdevHWModeInit(pScrn, pScrn->currentMode)) return FALSE; @@ -1251,6 +1311,15 @@ static Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, pScrn->rgbBits, pScrn->defaultVisual)) return FALSE; +#ifdef XF86DRI + /* Setup DRI after visuals have been + established, but before cfbScreenInit is + called. cfbScreenInit will eventually + call the driver's InitGLXVisuals call + back. */ + info->directRenderingEnabled = R128DRIScreenInit(pScreen); +#endif + #ifdef USE_FB if (!fbScreenInit (pScreen, info->FB, pScrn->virtualX, pScrn->virtualY, @@ -1358,6 +1427,101 @@ static Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, } } +#ifdef XF86DRI + /* Allocate frame buffer space for the + shared back and depth buffers as well + as for local textures. */ + if (info->directRenderingEnabled) { + FBAreaPtr fbarea; + int width_bytes = pScrn->displayWidth * info->pixel_bytes; + int maxy = info->FbMapSize / width_bytes; + int l; + + /* Allocate the shared back buffer */ + if ((fbarea = xf86AllocateOffscreenArea(pScreen, + pScrn->virtualX, + pScrn->virtualY, + 32, NULL, NULL, NULL))) { + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved back buffer from (%d,%d) to (%d,%d)\n", + fbarea->box.x1, fbarea->box.y1, + fbarea->box.x2, fbarea->box.y2); + + info->backX = fbarea->box.x1; + info->backY = fbarea->box.y1; + } else { + xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve back buffer\n"); + info->backX = -1; + info->backY = -1; + } + + /* Allocate the shared depth buffer */ + if ((fbarea = xf86AllocateOffscreenArea(pScreen, + pScrn->virtualX, + pScrn->virtualY, + 32, NULL, NULL, NULL))) { + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved depth buffer from (%d,%d) to (%d,%d)\n", + fbarea->box.x1, fbarea->box.y1, + fbarea->box.x2, fbarea->box.y2); + + info->depthX = fbarea->box.x1; + info->depthY = fbarea->box.y1; + } else { + xf86DrvMsg(scrnIndex, X_ERROR, "Unable to reserve depth buffer\n"); + info->depthX = -1; + info->depthY = -1; + } + + /* Allocate local texture space */ + if (((maxy - MemBox.y2 - 1) * width_bytes) > + (pScrn->virtualX * pScrn->virtualY * 2 * info->pixel_bytes)) { + info->textureX = 0; + info->textureY = MemBox.y2 + 1; + info->textureSize = (maxy - MemBox.y2 - 1) * width_bytes; + + l = R128MinBits((info->textureSize-1) / R128_NR_TEX_REGIONS); + if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY; + + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved %d kb for textures: (%d,%d)-(%d,%d)\n", + info->textureSize/1024, + info->textureX, info->textureY, + pScrn->displayWidth, maxy); + } else if ((fbarea = xf86AllocateOffscreenArea(pScreen, + pScrn->virtualX, + pScrn->virtualY * 2, + 32, + NULL, NULL, NULL))) { + info->textureX = fbarea->box.x1; + info->textureY = fbarea->box.y1; + info->textureSize = ((fbarea->box.y2 - fbarea->box.y1) * + (fbarea->box.x2 - fbarea->box.x1) * + info->pixel_bytes); + + l = R128MinBits((info->textureSize-1) / R128_NR_TEX_REGIONS); + if (l < R128_LOG_TEX_GRANULARITY) l = R128_LOG_TEX_GRANULARITY; + + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + xf86DrvMsg(scrnIndex, X_INFO, + "Reserved %d kb for textures: (%d,%d)-(%d,%d)\n", + info->textureSize/1024, + fbarea->box.x1, fbarea->box.y1, + fbarea->box.x2, fbarea->box.y2); + } else { + xf86DrvMsg(scrnIndex, X_ERROR, + "Unable to reserve texture space in frame buffer\n"); + info->textureX = -1; + info->textureY = -1; + } + } +#endif + /* Backing store setup */ miInitializeBackingStore(pScreen); xf86SetBackingStore(pScreen); @@ -1453,6 +1617,21 @@ static Bool R128ScreenInit(int scrnIndex, ScreenPtr pScreen, if (serverGeneration == 1) xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); +#ifdef XF86DRI + /* DRI finalization */ + if (info->directRenderingEnabled) { + /* Now that mi, cfb, drm and others have + done their thing, complete the DRI + setup. */ + info->directRenderingEnabled = R128DRIFinishScreenInit(pScreen); + } + if (info->directRenderingEnabled) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering disabled\n"); + } +#endif + return TRUE; } @@ -2037,6 +2216,7 @@ static Bool R128ModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode) R128InfoPtr info = R128PTR(pScrn); if (!R128Init(pScrn, mode, &info->ModeReg)) return FALSE; + /* FIXME? DRILock/DRIUnlock here? */ R128Blank(pScrn); R128RestoreMode(pScrn, &info->ModeReg); R128Unblank(pScrn); @@ -2099,11 +2279,27 @@ static Bool R128EnterVT(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; R128TRACE(("R128EnterVT\n")); +#ifdef XF86DRI + if (R128PTR(pScrn)->directRenderingEnabled) DRIUnlock(pScrn->pScreen); +#endif if (!R128ModeInit(pScrn, pScrn->currentMode)) return FALSE; R128AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); return TRUE; } +/* Called when VT switching away from the X server. Restore the original + text mode. */ +static void R128LeaveVT(int scrnIndex, int flags) +{ + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + + R128TRACE(("R128LeaveVT\n")); +#ifdef XF86DRI + if (R128PTR(pScrn)->directRenderingEnabled) DRILock(pScrn->pScreen, 0); +#endif + R128Restore(pScrn); +} + static Bool R128EnterVTFBDev(int scrnIndex, int flags) { @@ -2116,8 +2312,6 @@ R128EnterVTFBDev(int scrnIndex, int flags) return TRUE; } -/* Called when VT switching away from the X server. Restore the original - text mode. */ static void R128LeaveVTFBDev(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; @@ -2127,14 +2321,6 @@ static void R128LeaveVTFBDev(int scrnIndex, int flags) fbdevHWLeaveVT(scrnIndex,flags); } -static void R128LeaveVT(int scrnIndex, int flags) -{ - ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - - R128TRACE(("R128LeaveVT\n")); - R128Restore(pScrn); -} - /* Called at the end of each server generation. Restore the original text mode, unmap video memory, and unwrap and call the saved CloseScreen function. */ @@ -2144,6 +2330,15 @@ static Bool R128CloseScreen(int scrnIndex, ScreenPtr pScreen) R128InfoPtr info = R128PTR(pScrn); R128TRACE(("R128CloseScreen\n")); + +#ifdef XF86DRI + /* Disable direct rendering */ + if (info->directRenderingEnabled) { + R128DRICloseScreen(pScreen); + info->directRenderingEnabled = FALSE; + } +#endif + if (pScrn->vtSema) { R128Restore(pScrn); R128UnmapMem(pScrn); diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h index 86652affa..6c0998897 100644 --- a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h @@ -1,8 +1,8 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/r128/r128_reg.h,v 1.6 2000/02/23 04:47:19 martin Exp $ */ /************************************************************************** -Copyright 1999 ATI Technologies Inc. and Precision Insight, Inc., - Cedar Park, Texas. +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a @@ -159,6 +159,14 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_AGP_APER_OFFSET 0x0178 #define R128_AGP_BASE 0x0170 #define R128_AGP_CNTL 0x0174 +# define R128_AGP_APER_SIZE_256MB (0x00 << 0) +# define R128_AGP_APER_SIZE_128MB (0x20 << 0) +# define R128_AGP_APER_SIZE_64MB (0x30 << 0) +# define R128_AGP_APER_SIZE_32MB (0x38 << 0) +# define R128_AGP_APER_SIZE_16MB (0x3c << 0) +# define R128_AGP_APER_SIZE_8MB (0x3e << 0) +# define R128_AGP_APER_SIZE_4MB (0x3f << 0) +# define R128_AGP_APER_SIZE_MASK (0x3f << 0) #define R128_AGP_COMMAND 0x0f58 /* PCI */ #define R128_AGP_PLL_CNTL 0x0010 /* PLL */ #define R128_AGP_STATUS 0x0f54 /* PCI */ @@ -257,11 +265,12 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_BRUSH_SCALE 0x1470 #define R128_BRUSH_Y_X 0x1474 #define R128_BUS_CNTL 0x0030 -# define R128_BUS_RD_DISCARD_EN (1 << 24) -# define R128_BUS_RD_ABORT_EN (1 << 25) -# define R128_BUS_MSTR_DISCONNECT_EN (1 << 28) -# define R128_BUS_WRT_BURST (1 << 29) -# define R128_BUS_READ_BURST (1 << 30) +# define R128_BUS_MASTER_DIS (1 << 6) +# define R128_BUS_RD_DISCARD_EN (1 << 24) +# define R128_BUS_RD_ABORT_EN (1 << 25) +# define R128_BUS_MSTR_DISCONNECT_EN (1 << 28) +# define R128_BUS_WRT_BURST (1 << 29) +# define R128_BUS_READ_BURST (1 << 30) #define R128_BUS_CNTL1 0x0034 #define R128_CACHE_CNTL 0x1724 @@ -360,8 +369,11 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) -#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define R128_FOG_3D_TABLE_START 0x1810 +#define R128_FOG_3D_TABLE_END 0x1814 +#define R128_FOG_3D_TABLE_DENSITY 0x181c #define R128_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define R128_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define R128_DEVICE_ID 0x0f02 /* PCI */ #define R128_DP_BRUSH_BKGD_CLR 0x1478 #define R128_DP_BRUSH_FRGD_CLR 0x147c @@ -388,6 +400,19 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l # define R128_GMC_BRUSH_8x8_COLOR (10 << 4) # define R128_GMC_BRUSH_1X8_COLOR (12 << 4) # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define R128_GMC_BRUSH_NONE (15 << 4) +# define R128_GMC_DST_8BPP_CI (2 << 8) +# define R128_GMC_DST_15BPP (3 << 8) +# define R128_GMC_DST_16BPP (4 << 8) +# define R128_GMC_DST_24BPP (5 << 8) +# define R128_GMC_DST_32BPP (6 << 8) +# define R128_GMC_DST_8BPP_RGB (7 << 8) +# define R128_GMC_DST_Y8 (8 << 8) +# define R128_GMC_DST_RGB8 (9 << 8) +# define R128_GMC_DST_VYUY (11 << 8) +# define R128_GMC_DST_YVYU (12 << 8) +# define R128_GMC_DST_AYUV444 (14 << 8) +# define R128_GMC_DST_ARGB4444 (15 << 8) # define R128_GMC_DST_DATATYPE_MASK (0x0f << 8) # define R128_GMC_DST_DATATYPE_SHIFT 8 # define R128_GMC_SRC_DATATYPE_MASK (3 << 12) @@ -395,8 +420,11 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l # define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) # define R128_GMC_BYTE_PIX_ORDER (1 << 14) +# define R128_GMC_BYTE_MSB_TO_LSB (0 << 14) # define R128_GMC_BYTE_LSB_TO_MSB (1 << 14) # define R128_GMC_CONVERSION_TEMP (1 << 15) +# define R128_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define R128_GMC_CONVERSION_TEMP_9300 (1 << 15) # define R128_GMC_ROP3_MASK (0xff << 16) # define R128_DP_SRC_SOURCE_MASK (7 << 24) # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) @@ -404,7 +432,7 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l # define R128_GMC_3D_FCN_EN (1 << 27) # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define R128_AUX_CLIP_DIS (1 << 29) -# define R128_GMC_WR_MSK_DS (1 << 30) +# define R128_GMC_WR_MSK_DIS (1 << 30) # define R128_GMC_LD_BRUSH_Y_X (1 << 31) # define R128_ROP3_ZERO 0x00000000 # define R128_ROP3_DSa 0x00880000 @@ -456,6 +484,7 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_DST_PITCH 0x1408 #define R128_DST_PITCH_OFFSET 0x142c #define R128_DST_PITCH_OFFSET_C 0x1c80 +# define R128_PITCH_SHIFT 21 #define R128_DST_WIDTH 0x140c #define R128_DST_WIDTH_HEIGHT 0x1598 #define R128_DST_WIDTH_X 0x1588 @@ -573,7 +602,6 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_MEM_VGA_RP_SEL 0x003c #define R128_MEM_VGA_WP_SEL 0x0038 #define R128_MIN_GRANT 0x0f3e /* PCI */ -#define R128_MISC_3D_STATE_CNTL_REG 0x1CA0 #define R128_MM_DATA 0x0004 #define R128_MM_INDEX 0x0000 #define R128_MPLL_CNTL 0x000e /* PLL */ @@ -593,6 +621,7 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_PC_GUI_CTLSTAT 0x1748 #define R128_PC_GUI_MODE 0x1744 #define R128_PC_NGUI_CTLSTAT 0x0184 +# define R128_PC_FLUSH_GUI (3 << 0) # define R128_PC_FLUSH_ALL 0x00ff # define R128_PC_BUSY (1 << 31) #define R128_PC_NGUI_MODE 0x0180 @@ -689,6 +718,525 @@ static inline unsigned short regr16(volatile unsigned long base_addr, unsigned l #define R128_XDLL_CNTL 0x000c /* PLL */ #define R128_XPLL_CNTL 0x000b /* PLL */ + /* Registers for CCE and Microcode Engine */ +#define R128_PM4_MICROCODE_ADDR 0x07d4 +#define R128_PM4_MICROCODE_RADDR 0x07d8 +#define R128_PM4_MICROCODE_DATAH 0x07dc +#define R128_PM4_MICROCODE_DATAL 0x07e0 + +#define R128_PM4_BUFFER_OFFSET 0x0700 +#define R128_PM4_BUFFER_CNTL 0x0704 +# define R128_PM4_NONPM4 (0 << 28) +# define R128_PM4_192PIO (1 << 28) +# define R128_PM4_192BM (2 << 28) +# define R128_PM4_128PIO_64INDBM (3 << 28) +# define R128_PM4_128BM_64INDBM (4 << 28) +# define R128_PM4_64PIO_128INDBM (5 << 28) +# define R128_PM4_64BM_128INDBM (6 << 28) +# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) +# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) +# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) +#define R128_PM4_BUFFER_WM_CNTL 0x0708 +# define R128_WMA_SHIFT 0 +# define R128_WMB_SHIFT 8 +# define R128_WMC_SHIFT 16 +# define R128_WB_WM_SHIFT 24 +#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c +#define R128_PM4_BUFFER_DL_RPTR 0x0710 +#define R128_PM4_BUFFER_DL_WPTR 0x0714 +# define R128_PM4_BUFFER_DL_DONE (1 << 31) +#define R128_PM4_VC_FPU_SETUP 0x071c +# define R128_FRONT_DIR_CW (0 << 0) +# define R128_FRONT_DIR_CCW (1 << 0) +# define R128_FRONT_DIR_MASK (1 << 0) +# define R128_BACKFACE_CULL (0 << 1) +# define R128_BACKFACE_POINTS (1 << 1) +# define R128_BACKFACE_LINES (2 << 1) +# define R128_BACKFACE_SOLID (3 << 1) +# define R128_BACKFACE_MASK (3 << 1) +# define R128_FRONTFACE_CULL (0 << 3) +# define R128_FRONTFACE_POINTS (1 << 3) +# define R128_FRONTFACE_LINES (2 << 3) +# define R128_FRONTFACE_SOLID (3 << 3) +# define R128_FRONTFACE_MASK (3 << 3) +# define R128_FPU_COLOR_SOLID (0 << 5) +# define R128_FPU_COLOR_FLAT (1 << 5) +# define R128_FPU_COLOR_GOURAUD (2 << 5) +# define R128_FPU_COLOR_GOURAUD2 (3 << 5) +# define R128_FPU_SUB_PIX_2BITS (0 << 7) +# define R128_FPU_SUB_PIX_4BITS (1 << 7) +# define R128_FPU_MODE_2D (0 << 8) +# define R128_FPU_MODE_3D (1 << 8) +# define R128_TRAP_BITS_DISABLE (1 << 9) +# define R128_EDGE_ANTIALIAS (1 << 10) +# define R128_SUPERSAMPLE (1 << 11) +# define R128_XFACTOR_2 (0 << 12) +# define R128_XFACTOR_4 (1 << 12) +# define R128_YFACTOR_2 (0 << 13) +# define R128_YFACTOR_4 (1 << 13) +# define R128_FLAT_SHADE_VERTEX_D3D (0 << 14) +# define R128_FLAT_SHADE_VERTEX_OGL (1 << 14) +# define R128_FPU_ROUND_TRUNCATE (0 << 15) +# define R128_FPU_ROUND_NEAREST (1 << 15) +# define R128_WM_SEL_8DW (0 << 16) +# define R128_WM_SEL_16DW (1 << 16) +# define R128_WM_SEL_32DW (2 << 16) +#define R128_PM4_STAT 0x07b8 +# define R128_PM4_FIFOCNT_MASK 0x0fff +# define R128_PM4_BUSY (1 << 16) +# define R128_PM4_GUI_ACTIVE (1 << 31) +#define R128_PM4_BUFFER_ADDR 0x07f0 +#define R128_PM4_MICRO_CNTL 0x07fc +# define R128_PM4_MICRO_FREERUN (1 << 30) +#define R128_PM4_FIFO_DATA_EVEN 0x1000 +#define R128_PM4_FIFO_DATA_ODD 0x1004 + #define R128_SCALE_3D_CNTL 0x1a00 +# define R128_SCALE_DITHER_ERR_DIFF (0 << 1) +# define R128_SCALE_DITHER_TABLE (1 << 1) +# define R128_TEX_CACHE_SIZE_FULL (0 << 2) +# define R128_TEX_CACHE_SIZE_HALF (1 << 2) +# define R128_DITHER_INIT_CURR (0 << 3) +# define R128_DITHER_INIT_RESET (1 << 3) +# define R128_ROUND_24BIT (1 << 4) +# define R128_TEX_CACHE_DISABLE (1 << 5) +# define R128_SCALE_3D_NOOP (0 << 6) +# define R128_SCALE_3D_SCALE (1 << 6) +# define R128_SCALE_3D_TEXMAP_SHADE (2 << 6) +# define R128_SCALE_PIX_BLEND (0 << 8) +# define R128_SCALE_PIX_REPLICATE (1 << 8) +# define R128_TEX_CACHE_SPLIT (1 << 9) +# define R128_APPLE_YUV_MODE (1 << 10) +# define R128_TEX_CACHE_PALLETE_MODE (1 << 11) +# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12) +# define R128_ALPHA_COMB_ADD_NCLAMP (1 << 12) +# define R128_ALPHA_COMB_SUB_DST_SRC_CLAMP (2 << 12) +# define R128_ALPHA_COMB_SUB_DST_SRC_NCLAMP (3 << 12) +# define R128_FOG_TABLE (1 << 14) +# define R128_SIGNED_DST_CLAMP (1 << 15) +# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16) +# define R128_ALPHA_BLEND_SRC_ONE (1 << 16) +# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16) +# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16) +# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16) +# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16) +# define R128_ALPHA_BLEND_SRC_DSTALPHA (6 << 16) +# define R128_ALPHA_BLEND_SRC_INVDSTALPHA (7 << 16) +# define R128_ALPHA_BLEND_SRC_DSTCOLOR (8 << 16) +# define R128_ALPHA_BLEND_SRC_INVDSTCOLOR (9 << 16) +# define R128_ALPHA_BLEND_SRC_SAT (10 << 16) +# define R128_ALPHA_BLEND_SRC_BLEND (11 << 16) +# define R128_ALPHA_BLEND_SRC_INVBLEND (12 << 16) +# define R128_ALPHA_BLEND_DST_ZERO (0 << 20) +# define R128_ALPHA_BLEND_DST_ONE (1 << 20) +# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20) +# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20) +# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20) +# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20) +# define R128_ALPHA_BLEND_DST_DSTALPHA (6 << 20) +# define R128_ALPHA_BLEND_DST_INVDSTALPHA (7 << 20) +# define R128_ALPHA_BLEND_DST_DSTCOLOR (8 << 20) +# define R128_ALPHA_BLEND_DST_INVDSTCOLOR (9 << 20) +# define R128_ALPHA_TEST_NEVER (0 << 24) +# define R128_ALPHA_TEST_LESS (1 << 24) +# define R128_ALPHA_TEST_LESSEQUAL (2 << 24) +# define R128_ALPHA_TEST_EQUAL (3 << 24) +# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24) +# define R128_ALPHA_TEST_GREATER (5 << 24) +# define R128_ALPHA_TEST_NEQUAL (6 << 24) +# define R128_ALPHA_TEST_ALWAYS (7 << 24) +# define R128_COMPOSITE_SHADOW_CMP_EQUAL (0 << 28) +# define R128_COMPOSITE_SHADOW_CMP_NEQUAL (1 << 28) +# define R128_COMPOSITE_SHADOW (1 << 29) +# define R128_TEX_MAP_ALPHA_IN_TEXTURE (1 << 30) +# define R128_TEX_CACHE_LINE_SIZE_8QW (0 << 31) +# define R128_TEX_CACHE_LINE_SIZE_4QW (1 << 31) + +#define R128_SETUP_CNTL 0x1bc4 +# define R128_DONT_START_TRIANGLE (1 << 0) +# define R128_Z_BIAS (0 << 1) +# define R128_DONT_START_ANY_ON (1 << 2) +# define R128_COLOR_SOLID_COLOR (0 << 3) +# define R128_COLOR_FLAT_VERT_1 (1 << 3) +# define R128_COLOR_FLAT_VERT_2 (2 << 3) +# define R128_COLOR_FLAT_VERT_3 (3 << 3) +# define R128_COLOR_GOURAUD (4 << 3) +# define R128_PRIM_TYPE_TRI (0 << 7) +# define R128_PRIM_TYPE_LINE (1 << 7) +# define R128_PRIM_TYPE_POINT (2 << 7) +# define R128_PRIM_TYPE_POLY_EDGE (3 << 7) +# define R128_TEXTURE_ST_MULT_W (0 << 9) +# define R128_TEXTURE_ST_DIRECT (1 << 9) +# define R128_STARTING_VERTEX_1 (1 << 14) +# define R128_STARTING_VERTEX_2 (2 << 14) +# define R128_STARTING_VERTEX_3 (3 << 14) +# define R128_ENDING_VERTEX_1 (1 << 16) +# define R128_ENDING_VERTEX_2 (2 << 16) +# define R128_ENDING_VERTEX_3 (3 << 16) +# define R128_SU_POLY_LINE_LAST (0 << 18) +# define R128_SU_POLY_LINE_NOT_LAST (1 << 18) +# define R128_SUB_PIX_2BITS (0 << 19) +# define R128_SUB_PIX_4BITS (1 << 19) +# define R128_SET_UP_CONTINUE (1 << 31) + +#define R128_WINDOW_XY_OFFSET 0x1bcc +# define R128_WINDOW_Y_SHIFT 4 +# define R128_WINDOW_X_SHIFT 20 + +#define R128_Z_OFFSET_C 0x1c90 +#define R128_Z_PITCH_C 0x1c94 +#define R128_Z_STEN_CNTL_C 0x1c98 +# define R128_Z_PIX_WIDTH_16 (0 << 1) +# define R128_Z_PIX_WIDTH_24 (1 << 1) +# define R128_Z_PIX_WIDTH_32 (2 << 1) +# define R128_Z_PIX_WIDTH_MASK (3 << 1) +# define R128_Z_TEST_NEVER (0 << 4) +# define R128_Z_TEST_LESS (1 << 4) +# define R128_Z_TEST_LESSEQUAL (2 << 4) +# define R128_Z_TEST_EQUAL (3 << 4) +# define R128_Z_TEST_GREATEREQUAL (4 << 4) +# define R128_Z_TEST_GREATER (5 << 4) +# define R128_Z_TEST_NEQUAL (6 << 4) +# define R128_Z_TEST_ALWAYS (7 << 4) +# define R128_Z_TEST_MASK (7 << 4) +# define R128_STENCIL_TEST_NEVER (0 << 12) +# define R128_STENCIL_TEST_LESS (1 << 12) +# define R128_STENCIL_TEST_LESSEQUAL (2 << 12) +# define R128_STENCIL_TEST_EQUAL (3 << 12) +# define R128_STENCIL_TEST_GREATEREQUAL (4 << 12) +# define R128_STENCIL_TEST_GREATER (5 << 12) +# define R128_STENCIL_TEST_NEQUAL (6 << 12) +# define R128_STENCIL_TEST_ALWAYS (7 << 12) +# define R128_STENCIL_S_FAIL_KEEP (0 << 16) +# define R128_STENCIL_S_FAIL_ZERO (1 << 16) +# define R128_STENCIL_S_FAIL_REPLACE (2 << 16) +# define R128_STENCIL_S_FAIL_INC (3 << 16) +# define R128_STENCIL_S_FAIL_DEC (4 << 16) +# define R128_STENCIL_S_FAIL_INV (5 << 16) +# define R128_STENCIL_ZPASS_KEEP (0 << 20) +# define R128_STENCIL_ZPASS_ZERO (1 << 20) +# define R128_STENCIL_ZPASS_REPLACE (2 << 20) +# define R128_STENCIL_ZPASS_INC (3 << 20) +# define R128_STENCIL_ZPASS_DEC (4 << 20) +# define R128_STENCIL_ZPASS_INV (5 << 20) +# define R128_STENCIL_ZFAIL_KEEP (0 << 24) +# define R128_STENCIL_ZFAIL_ZERO (1 << 24) +# define R128_STENCIL_ZFAIL_REPLACE (2 << 24) +# define R128_STENCIL_ZFAIL_INC (3 << 24) +# define R128_STENCIL_ZFAIL_DEC (4 << 24) +# define R128_STENCIL_ZFAIL_INV (5 << 24) +#define R128_TEX_CNTL_C 0x1c9c +# define R128_Z_ENABLE (1 << 0) +# define R128_Z_WRITE_ENABLE (1 << 1) +# define R128_STENCIL_ENABLE (1 << 3) +# define R128_SHADE_ENABLE (0 << 4) +# define R128_TEXMAP_ENABLE (1 << 4) +# define R128_SEC_TEXMAP_ENABLE (1 << 5) +# define R128_FOG_ENABLE (1 << 7) +# define R128_DITHER_ENABLE (1 << 8) +# define R128_ALPHA_ENABLE (1 << 9) +# define R128_ALPHA_TEST_ENABLE (1 << 10) +# define R128_SPEC_LIGHT_ENABLE (1 << 11) +# define R128_TEX_CHROMA_KEY_ENABLE (1 << 12) +# define R128_ALPHA_IN_TEX_COMPLETE_A (0 << 13) +# define R128_ALPHA_IN_TEX_LSB_A (1 << 13) +# define R128_LIGHT_DIS (0 << 14) +# define R128_LIGHT_COPY (1 << 14) +# define R128_LIGHT_MODULATE (2 << 14) +# define R128_LIGHT_ADD (3 << 14) +# define R128_LIGHT_BLEND_CONSTANT (4 << 14) +# define R128_LIGHT_BLEND_TEXTURE (5 << 14) +# define R128_LIGHT_BLEND_VERTEX (6 << 14) +# define R128_LIGHT_BLEND_CONST_COLOR (7 << 14) +# define R128_ALPHA_LIGHT_DIS (0 << 18) +# define R128_ALPHA_LIGHT_COPY (1 << 18) +# define R128_ALPHA_LIGHT_MODULATE (2 << 18) +# define R128_ALPHA_LIGHT_ADD (3 << 18) +# define R128_ANTI_ALIAS (1 << 21) +# define R128_TEX_CACHE_FLUSH (1 << 23) +# define R128_LOD_BIAS_SHIFT 24 +#define R128_MISC_3D_STATE_CNTL_REG 0x1ca0 +# define R128_REF_ALPHA_MASK 0xff +# define R128_MISC_SCALE_3D_NOOP (0 << 8) +# define R128_MISC_SCALE_3D_SCALE (1 << 8) +# define R128_MISC_SCALE_3D_TEXMAP_SHADE (2 << 8) +# define R128_MISC_SCALE_PIX_BLEND (0 << 10) +# define R128_MISC_SCALE_PIX_REPLICATE (1 << 10) +# define R128_ALPHA_COMB_ADD_CLAMP (0 << 12) +# define R128_ALPHA_COMB_ADD_NO_CLAMP (1 << 12) +# define R128_ALPHA_COMB_SUB_SRC_DST_CLAMP (2 << 12) +# define R128_ALPHA_COMB_SUB_SRC_DST_NO_CLAMP (3 << 12) +# define R128_FOG_VERTEX (0 << 14) +# define R128_FOG_TABLE (1 << 14) +# define R128_ALPHA_BLEND_SRC_ZERO (0 << 16) +# define R128_ALPHA_BLEND_SRC_ONE (1 << 16) +# define R128_ALPHA_BLEND_SRC_SRCCOLOR (2 << 16) +# define R128_ALPHA_BLEND_SRC_INVSRCCOLOR (3 << 16) +# define R128_ALPHA_BLEND_SRC_SRCALPHA (4 << 16) +# define R128_ALPHA_BLEND_SRC_INVSRCALPHA (5 << 16) +# define R128_ALPHA_BLEND_SRC_DESTALPHA (6 << 16) +# define R128_ALPHA_BLEND_SRC_INVDESTALPHA (7 << 16) +# define R128_ALPHA_BLEND_SRC_DESTCOLOR (8 << 16) +# define R128_ALPHA_BLEND_SRC_INVDESTCOLOR (9 << 16) +# define R128_ALPHA_BLEND_SRC_SRCALPHASAT (10 << 16) +# define R128_ALPHA_BLEND_SRC_BOTHSRCALPHA (11 << 16) +# define R128_ALPHA_BLEND_SRC_BOTHINVSRCALPHA (12 << 16) +# define R128_ALPHA_BLEND_SRC_MASK (15 << 16) +# define R128_ALPHA_BLEND_DST_ZERO (0 << 20) +# define R128_ALPHA_BLEND_DST_ONE (1 << 20) +# define R128_ALPHA_BLEND_DST_SRCCOLOR (2 << 20) +# define R128_ALPHA_BLEND_DST_INVSRCCOLOR (3 << 20) +# define R128_ALPHA_BLEND_DST_SRCALPHA (4 << 20) +# define R128_ALPHA_BLEND_DST_INVSRCALPHA (5 << 20) +# define R128_ALPHA_BLEND_DST_DESTALPHA (6 << 20) +# define R128_ALPHA_BLEND_DST_INVDESTALPHA (7 << 20) +# define R128_ALPHA_BLEND_DST_DESTCOLOR (8 << 20) +# define R128_ALPHA_BLEND_DST_INVDESTCOLOR (9 << 20) +# define R128_ALPHA_BLEND_DST_SRCALPHASAT (10 << 20) +# define R128_ALPHA_BLEND_DST_MASK (15 << 20) +# define R128_ALPHA_TEST_NEVER (0 << 24) +# define R128_ALPHA_TEST_LESS (1 << 24) +# define R128_ALPHA_TEST_LESSEQUAL (2 << 24) +# define R128_ALPHA_TEST_EQUAL (3 << 24) +# define R128_ALPHA_TEST_GREATEREQUAL (4 << 24) +# define R128_ALPHA_TEST_GREATER (5 << 24) +# define R128_ALPHA_TEST_NEQUAL (6 << 24) +# define R128_ALPHA_TEST_ALWAYS (7 << 24) +# define R128_ALPHA_TEST_MASK (7 << 24) +#define R128_TEXTURE_CLR_CMP_CLR_C 0x1ca4 +#define R128_TEXTURE_CLR_CMP_MSK_C 0x1ca8 +#define R128_FOG_COLOR_C 0x1cac +# define R128_FOG_BLUE_SHIFT 0 +# define R128_FOG_GREEN_SHIFT 8 +# define R128_FOG_RED_SHIFT 16 +#define R128_PRIM_TEX_CNTL_C 0x1cb0 +# define R128_MIN_BLEND_NEAREST (0 << 1) +# define R128_MIN_BLEND_LINEAR (1 << 1) +# define R128_MIN_BLEND_MIPNEAREST (2 << 1) +# define R128_MIN_BLEND_MIPLINEAR (3 << 1) +# define R128_MIN_BLEND_LINEARMIPNEAREST (4 << 1) +# define R128_MIN_BLEND_LINEARMIPLINEAR (5 << 1) +# define R128_MIN_BLEND_MASK (7 << 1) +# define R128_MAG_BLEND_NEAREST (0 << 4) +# define R128_MAG_BLEND_LINEAR (1 << 4) +# define R128_MAG_BLEND_MASK (7 << 4) +# define R128_MIP_MAP_DISABLE (1 << 7) +# define R128_TEX_CLAMP_S_WRAP (0 << 8) +# define R128_TEX_CLAMP_S_MIRROR (1 << 8) +# define R128_TEX_CLAMP_S_CLAMP (2 << 8) +# define R128_TEX_CLAMP_S_BORDER_COLOR (3 << 8) +# define R128_TEX_CLAMP_S_MASK (3 << 8) +# define R128_TEX_WRAP_S (1 << 10) +# define R128_TEX_CLAMP_T_WRAP (0 << 11) +# define R128_TEX_CLAMP_T_MIRROR (1 << 11) +# define R128_TEX_CLAMP_T_CLAMP (2 << 11) +# define R128_TEX_CLAMP_T_BORDER_COLOR (3 << 11) +# define R128_TEX_CLAMP_T_MASK (3 << 11) +# define R128_TEX_WRAP_T (1 << 13) +# define R128_TEX_PERSPECTIVE_DISABLE (1 << 14) +# define R128_DATATYPE_VQ (0 << 16) +# define R128_DATATYPE_CI4 (1 << 16) +# define R128_DATATYPE_CI8 (2 << 16) +# define R128_DATATYPE_ARGB1555 (3 << 16) +# define R128_DATATYPE_RGB565 (4 << 16) +# define R128_DATATYPE_RGB888 (5 << 16) +# define R128_DATATYPE_ARGB8888 (6 << 16) +# define R128_DATATYPE_RGB332 (7 << 16) +# define R128_DATATYPE_Y8 (8 << 16) +# define R128_DATATYPE_RGB8 (9 << 16) +# define R128_DATATYPE_CI16 (10 << 16) +# define R128_DATATYPE_YUV422 (11 << 16) +# define R128_DATATYPE_YUV422_2 (12 << 16) +# define R128_DATATYPE_AYUV444 (14 << 16) +# define R128_DATATYPE_ARGB4444 (15 << 16) +# define R128_PALLETE_EITHER (0 << 20) +# define R128_PALLETE_1 (1 << 20) +# define R128_PALLETE_2 (2 << 20) +# define R128_PSEUDOCOLOR_DT_RGB565 (0 << 24) +# define R128_PSEUDOCOLOR_DT_ARGB1555 (1 << 24) +# define R128_PSEUDOCOLOR_DT_ARGB4444 (2 << 24) +#define R128_PRIM_TEXTURE_COMBINE_CNTL_C 0x1cb4 +# define R128_COMB_DIS (0 << 0) +# define R128_COMB_COPY (1 << 0) +# define R128_COMB_COPY_INP (2 << 0) +# define R128_COMB_MODULATE (3 << 0) +# define R128_COMB_MODULATE2X (4 << 0) +# define R128_COMB_MODULATE4X (5 << 0) +# define R128_COMB_ADD (6 << 0) +# define R128_COMB_ADD_SIGNED (7 << 0) +# define R128_COMB_BLEND_VERTEX (8 << 0) +# define R128_COMB_BLEND_TEXTURE (9 << 0) +# define R128_COMB_BLEND_CONST (10 << 0) +# define R128_COMB_BLEND_PREMULT (11 << 0) +# define R128_COMB_BLEND_PREV (12 << 0) +# define R128_COMB_BLEND_PREMULT_INV (13 << 0) +# define R128_COMB_ADD_SIGNED2X (14 << 0) +# define R128_COMB_BLEND_CONST_COLOR (15 << 0) +# define R128_COMB_MASK (15 << 0) +# define R128_COLOR_FACTOR_TEX (4 << 4) +# define R128_COLOR_FACTOR_NTEX (5 << 4) +# define R128_COLOR_FACTOR_ALPHA (6 << 4) +# define R128_COLOR_FACTOR_NALPHA (7 << 4) +# define R128_COLOR_FACTOR_MASK (15 << 4) +# define R128_INPUT_FACTOR_CONST_COLOR (2 << 10) +# define R128_INPUT_FACTOR_CONST_ALPHA (3 << 10) +# define R128_INPUT_FACTOR_INT_COLOR (4 << 10) +# define R128_INPUT_FACTOR_INT_ALPHA (5 << 10) +# define R128_INPUT_FACTOR_MASK (15 << 10) +# define R128_COMB_ALPHA_DIS (0 << 14) +# define R128_COMB_ALPHA_COPY (1 << 14) +# define R128_COMB_ALPHA_COPY_INP (2 << 14) +# define R128_COMB_ALPHA_MODULATE (3 << 14) +# define R128_COMB_ALPHA_MODULATE2X (4 << 14) +# define R128_COMB_ALPHA_MODULATE4X (5 << 14) +# define R128_COMB_ALPHA_ADD (6 << 14) +# define R128_COMB_ALPHA_ADD_SIGNED (7 << 14) +# define R128_COMB_ALPHA_ADD_SIGNED2X (14 << 14) +# define R128_COMB_ALPHA_MASK (15 << 14) +# define R128_ALPHA_FACTOR_TEX_ALPHA (6 << 18) +# define R128_ALPHA_FACTOR_NTEX_ALPHA (7 << 18) +# define R128_ALPHA_FACTOR_MASK (15 << 18) +# define R128_INP_FACTOR_A_CONST_ALPHA (1 << 25) +# define R128_INP_FACTOR_A_INT_ALPHA (2 << 25) +# define R128_INP_FACTOR_A_MASK (7 << 25) +#define R128_TEX_SIZE_PITCH_C 0x1cb8 +# define R128_TEX_PITCH_SHIFT 0 +# define R128_TEX_SIZE_SHIFT 4 +# define R128_TEX_HEIGHT_SHIFT 8 +# define R128_TEX_MIN_SIZE_SHIFT 12 +# define R128_SEC_TEX_PITCH_SHIFT 16 +# define R128_SEC_TEX_SIZE_SHIFT 20 +# define R128_SEC_TEX_HEIGHT_SHIFT 24 +# define R128_SEC_TEX_MIN_SIZE_SHIFT 28 +# define R128_TEX_PITCH_MASK (0x0f << 0) +# define R128_TEX_SIZE_MASK (0x0f << 4) +# define R128_TEX_HEIGHT_MASK (0x0f << 8) +# define R128_TEX_MIN_SIZE_MASK (0x0f << 12) +# define R128_SEC_TEX_PITCH_MASK (0x0f << 16) +# define R128_SEC_TEX_SIZE_MASK (0x0f << 20) +# define R128_SEC_TEX_HEIGHT_MASK (0x0f << 24) +# define R128_SEC_TEX_MIN_SIZE_MASK (0x0f << 28) +# define R128_TEX_SIZE_PITCH_SHIFT 0 +# define R128_SEC_TEX_SIZE_PITCH_SHIFT 16 +# define R128_TEX_SIZE_PITCH_MASK (0xffff << 0) +# define R128_SEC_TEX_SIZE_PITCH_MASK (0xffff << 16) +#define R128_PRIM_TEX_0_OFFSET_C 0x1cbc +#define R128_PRIM_TEX_1_OFFSET_C 0x1cc0 +#define R128_PRIM_TEX_2_OFFSET_C 0x1cc4 +#define R128_PRIM_TEX_3_OFFSET_C 0x1cc8 +#define R128_PRIM_TEX_4_OFFSET_C 0x1ccc +#define R128_PRIM_TEX_5_OFFSET_C 0x1cd0 +#define R128_PRIM_TEX_6_OFFSET_C 0x1cd4 +#define R128_PRIM_TEX_7_OFFSET_C 0x1cd8 +#define R128_PRIM_TEX_8_OFFSET_C 0x1cdc +#define R128_PRIM_TEX_9_OFFSET_C 0x1ce0 +#define R128_PRIM_TEX_10_OFFSET_C 0x1ce4 +# define R128_TEX_NO_TILE (0 << 30) +# define R128_TEX_TILED_BY_HOST (1 << 30) +# define R128_TEX_TILED_BY_STORAGE (2 << 30) +# define R128_TEX_TILED_BY_STORAGE2 (3 << 30) + +#define R128_SEC_TEX_CNTL_C 0x1d00 +# define R128_SEC_SELECT_PRIM_ST (0 << 0) +# define R128_SEC_SELECT_SEC_ST (1 << 0) +#define R128_SEC_TEX_COMBINE_CNTL_C 0x1d04 +# define R128_INPUT_FACTOR_PREV_COLOR (8 << 10) +# define R128_INPUT_FACTOR_PREV_ALPHA (9 << 10) +# define R128_INP_FACTOR_A_PREV_ALPHA (4 << 25) +#define R128_SEC_TEX_0_OFFSET_C 0x1d08 +#define R128_SEC_TEX_1_OFFSET_C 0x1d0c +#define R128_SEC_TEX_2_OFFSET_C 0x1d10 +#define R128_SEC_TEX_3_OFFSET_C 0x1d14 +#define R128_SEC_TEX_4_OFFSET_C 0x1d18 +#define R128_SEC_TEX_5_OFFSET_C 0x1d1c +#define R128_SEC_TEX_6_OFFSET_C 0x1d20 +#define R128_SEC_TEX_7_OFFSET_C 0x1d24 +#define R128_SEC_TEX_8_OFFSET_C 0x1d28 +#define R128_SEC_TEX_9_OFFSET_C 0x1d2c +#define R128_SEC_TEX_10_OFFSET_C 0x1d30 +#define R128_CONSTANT_COLOR_C 0x1d34 +# define R128_CONSTANT_BLUE_SHIFT 0 +# define R128_CONSTANT_GREEN_SHIFT 8 +# define R128_CONSTANT_RED_SHIFT 16 +# define R128_CONSTANT_ALPHA_SHIFT 24 +#define R128_PRIM_TEXTURE_BORDER_COLOR_C 0x1d38 +# define R128_PRIM_TEX_BORDER_BLUE_SHIFT 0 +# define R128_PRIM_TEX_BORDER_GREEN_SHIFT 8 +# define R128_PRIM_TEX_BORDER_RED_SHIFT 16 +# define R128_PRIM_TEX_BORDER_ALPHA_SHIFT 24 +#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c +# define R128_SEC_TEX_BORDER_BLUE_SHIFT 0 +# define R128_SEC_TEX_BORDER_GREEN_SHIFT 8 +# define R128_SEC_TEX_BORDER_RED_SHIFT 16 +# define R128_SEC_TEX_BORDER_ALPHA_SHIFT 24 +#define R128_STEN_REF_MASK_C 0x1d40 +# define R128_STEN_REFERENCE_SHIFT 0 +# define R128_STEN_MASK_SHIFT 16 +# define R128_STEN_WRITE_MASK_SHIFT 24 +#define R128_PLANE_3D_MASK_C 0x1d44 + + + /* CCE packet types */ +#define R128_CCE_PACKET0 0x00000000 +#define R128_CCE_PACKET1 0x40000000 +#define R128_CCE_PACKET2 0x80000000 +#define R128_CCE_PACKET3_NOP 0xC0001000 +#define R128_CCE_PACKET3_PAINT 0xC0001100 +#define R128_CCE_PACKET3_BITBLT 0xC0001200 +#define R128_CCE_PACKET3_SMALLTEXT 0xC0001300 +#define R128_CCE_PACKET3_HOSTDATA_BLT 0xC0001400 +#define R128_CCE_PACKET3_POLYLINE 0xC0001500 +#define R128_CCE_PACKET3_SCALING 0xC0001600 +#define R128_CCE_PACKET3_TRANS_SCALING 0xC0001700 +#define R128_CCE_PACKET3_POLYSCANLINES 0xC0001800 +#define R128_CCE_PACKET3_NEXT_CHAR 0xC0001900 +#define R128_CCE_PACKET3_PAINT_MULTI 0xC0001A00 +#define R128_CCE_PACKET3_BITBLT_MULTI 0xC0001B00 +#define R128_CCE_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define R128_CCE_PACKET3_SET_SCISSORS 0xC0001E00 +#define R128_CCE_PACKET3_SET_MODE24BPP 0xC0001F00 +#define R128_CCE_PACKET3_CNTL_PAINT 0xC0009100 +#define R128_CCE_PACKET3_CNTL_BITBLT 0xC0009200 +#define R128_CCE_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define R128_CCE_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define R128_CCE_PACKET3_CNTL_POLYLINE 0xC0009500 +#define R128_CCE_PACKET3_CNTL_SCALING 0xC0009600 +#define R128_CCE_PACKET3_CNTL_TRANS_SCALING 0xC0009700 +#define R128_CCE_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define R128_CCE_PACKET3_CNTL_NEXT_CHAR 0xC0009900 +#define R128_CCE_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define R128_CCE_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define R128_CCE_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 +#define R128_CCE_PACKET3_3D_SAVE_CONTEXT 0xC0002000 +#define R128_CCE_PACKET3_3D_PLAY_CONTEXT 0xC0002100 +#define R128_CCE_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define R128_CCE_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500 +#define R128_CCE_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R128_CCE_PACKET3_PURGE 0xC0002D00 +#define R128_CCE_PACKET3_NEXT_VERTEX_BUNDLE 0xC0002E00 + +#define R128_CCE_VC_FRMT_RHW 0x00000001 +#define R128_CCE_VC_FRMT_DIFFUSE_BGR 0x00000002 +#define R128_CCE_VC_FRMT_DIFFUSE_A 0x00000004 +#define R128_CCE_VC_FRMT_DIFFUSE_ARGB 0x00000008 +#define R128_CCE_VC_FRMT_SPEC_BGR 0x00000010 +#define R128_CCE_VC_FRMT_SPEC_F 0x00000020 +#define R128_CCE_VC_FRMT_SPEC_FRGB 0x00000040 +#define R128_CCE_VC_FRMT_S_T 0x00000080 +#define R128_CCE_VC_FRMT_S2_T2 0x00000100 +#define R128_CCE_VC_FRMT_RHW2 0x00000200 + +#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 +#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define R128_CCE_VC_CNTL_NUM_SHIFT 16 #endif diff --git a/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_sarea.h b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_sarea.h new file mode 100644 index 000000000..2b835472e --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/drivers/r128/r128_sarea.h @@ -0,0 +1,69 @@ +/* $XFree86$ */ +/************************************************************************** + +Copyright 1999, 2000 ATI Technologies Inc. and Precision Insight, Inc., + Cedar Park, Texas. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +ATI, PRECISION INSIGHT AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin <kevin@precisioninsight.com> + * + */ + +#ifndef _R128_SAREA_H_ +#define _R128_SAREA_H_ + +/* Each region is a minimum of 64k, and there are at most 128 of them */ +#define R128_NR_TEX_REGIONS 128 +#define R128_LOG_TEX_GRANULARITY 16 + +typedef struct { + unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char in_use; /* owned by a client, or free? */ + int age; /* tracked by clients to update local LRU's */ +} R128TexRegion; + +typedef struct { + /* Maintain an LRU of contiguous regions of texture space. If you + * think you own a region of texture memory, and it has an age + * different to the one you set, then you are mistaken and it has + * been stolen by another client. If global texAge hasn't changed, + * there is no need to walk the list. + * + * These regions can be used as a proxy for the fine-grained texture + * information of other clients - by maintaining them in the same + * lru which is used to age their own textures, clients have an + * approximate lru for the whole of global texture space, and can + * make informed decisions as to which areas to kick out. There is + * no need to choose whether to kick out your own texture or someone + * else's - simply eject them all in LRU order. + */ + R128TexRegion texList[R128_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + + int ctxOwner; /* last context to upload state */ +} R128SAREAPriv, *R128SAREAPrivPtr; + +#endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.kernel b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.kernel index 44d75c487..a169473af 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.kernel +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.kernel @@ -14,7 +14,8 @@ L_TARGET := libdrm.a L_OBJS := init.o memory.o proc.o auth.o context.o drawable.o bufs.o \ - lists.o lock.o ioctl.o fops.o vm.o dma.o + lists.o lock.o ioctl.o fops.o vm.o dma.o ctxbitmap.o \ + agpsupport.o M_OBJS := @@ -26,6 +27,14 @@ ifdef CONFIG_DRM_TDFX M_OBJS += tdfx.o endif +ifdef CONFIG_DRM_MGA +M_OBJS += mga.o +endif + +ifdef CONFIG_DRM_R128 +M_OBJS += r128.o +endif + include $(TOPDIR)/Rules.make gamma.o: gamma_drv.o gamma_dma.o $(L_TARGET) @@ -33,3 +42,12 @@ gamma.o: gamma_drv.o gamma_dma.o $(L_TARGET) tdfx.o: tdfx_drv.o tdfx_context.o $(L_TARGET) $(LD) $(LD_RFLAG) -r -o $@ tdfx_drv.o tdfx_context.o -L. -ldrm + +i810.o: i810_drv.o i810_context.o $(L_TARGET) + $(LD) $(LD_RFLAG) -r -o $@ i810_drv.o i810_bufs.o i810_dma.o i810_context.o -L. -ldrm + +mga.o: mga_drv.o mga_context.o mga_dma.o mga_bufs.o $(L_TARGET) + $(LD) $(LD_RFLAG) -r -o $@ mga_drv.o mga_bufs.o mga_dma.o mga_context.o mga_state.o -L. -ldrm + +r128.o: r128_drv.o r128_context.o $(L_TARGET) + $(LD) $(LD_RFLAG) -r -o $@ r128_drv.o r128_context.o -L. -ldrm diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.linux b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.linux index 8a41f880b..17c65454c 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.linux +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/Makefile.linux @@ -1,8 +1,7 @@ # Makefile -- For the Direct Rendering Manager module (drm) # Created: Mon Jan 4 09:26:53 1999 by faith@precisioninsight.com -# Revised: Sun Feb 13 23:15:59 2000 by kevin@precisioninsight.com # -# Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. +# Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. # All rights reserved. # # Permission is hereby granted, free of charge, to any person obtaining a @@ -31,12 +30,14 @@ # *** Setup +# **** End of SMP/MODVERSIONS detection + MODS= gamma.o tdfx.o LIBS= libdrm.a PROGS= drmstat DRMOBJS= init.o memory.o proc.o auth.o context.o drawable.o bufs.o \ - lists.o lock.o ioctl.o fops.o vm.o dma.o + lists.o lock.o ioctl.o fops.o vm.o dma.o ctxbitmap.o DRMHEADERS= drm.h drmP.h GAMMAOBJS= gamma_drv.o gamma_dma.o @@ -48,6 +49,8 @@ TDFXHEADERS= tdfx_drv.h $(DRMHEADERS) PROGOBJS= drmstat.po xf86drm.po xf86drmHash.po xf86drmRandom.po sigio.po PROGHEADERS= xf86drm.h $(DRMHEADERS) +INC= /usr/include + CFLAGS= -O2 $(WARNINGS) WARNINGS= -Wall -Wwrite-strings -Wpointer-arith -Wcast-align \ -Wstrict-prototypes -Wshadow -Wnested-externs \ @@ -102,7 +105,30 @@ SMP := $(shell gcc -E -nostdinc -I$(TREE) picker.c 2>/dev/null \ | grep -s 'SMP = ' | cut -d' ' -f3) MODVERSIONS := $(shell gcc -E -I $(TREE) picker.c 2>/dev/null \ | grep -s 'MODVERSIONS = ' | cut -d' ' -f3) -all::;@echo KERNEL HEADERS IN $(TREE): SMP=${SMP} MODVERSIONS=${MODVERSIONS} +AGP := $(shell gcc -E -nostdinc -I$(TREE) picker.c 2>/dev/null \ + | grep -s 'AGP = ' | cut -d' ' -f3) +ifeq ($(AGP),0) +AGP := $(shell gcc -E -nostdinc -I$(TREE) picker.c 2>/dev/null \ + | grep -s 'AGP_MODULE = ' | cut -d' ' -f3) +endif + +ifeq ($(AGP),1) +MODCFLAGS += -DDRM_AGP +DRMOBJS += agpsupport.o +MODS += mga.o i810.o r128.o + +MGAOBJS= mga_drv.o mga_dma.o mga_bufs.o mga_state.o mga_context.o +MGAHEADERS= mga_drv.h mga_drm_public.h $(DRMHEADERS) + +I810OBJS= i810_drv.o i810_dma.o i810_bufs.o i810_context.o +I810HEADERS= i810_drv.h i810_drm_public.h $(DRMHEADERS) + +R128OBJS= r128_drv.o r128_context.o +R128HEADERS= r128_drv.h $(DRMHEADERS) +endif + +all::;@echo KERNEL HEADERS IN $(TREE): SMP=${SMP} MODVERSIONS=${MODVERSIONS} \ + AGP=${AGP} all:: $(LIBS) $(MODS) $(PROGS) endif @@ -116,6 +142,7 @@ ifeq ($(MODVERSIONS),1) MODCFLAGS += -DMODVERSIONS -include $(TREE)/linux/modversions.h endif + # **** End of configuration libdrm.a: $(DRMOBJS) @@ -128,6 +155,17 @@ gamma.o: $(GAMMAOBJS) $(LIBS) tdfx.o: $(TDFXOBJS) $(LIBS) $(LD) -r $^ -o $@ +ifeq ($(AGP),1) +mga.o: $(MGAOBJS) $(LIBS) + $(LD) -r $^ -o $@ + +i810.o: $(I810OBJS) $(LIBS) + $(LD) -r $^ -o $@ + +r128.o: $(R128OBJS) $(LIBS) + $(LD) -r $^ -o $@ +endif + drmstat: $(PROGOBJS) $(CC) $(PRGCFLAGS) $^ $(PRGLIBS) -o $@ @@ -149,8 +187,12 @@ ChangeLog: $(DRMOBJS): $(DRMHEADERS) $(GAMMAOBJS): $(GAMMAHEADERS) $(TDFXOBJS): $(TDFXHEADERS) +ifeq ($(AGP),1) +$(MGAOBJS): $(MGAHEADERS) +$(I810OBJS): $(I810HEADERS) +$(R128OBJS): $(R128HEADERS) +endif $(PROGOBJS): $(PROGHEADERS) clean: - rm -f *.o *.po *~ core $(PROGS) - + rm -f *.o *.a *.po *~ core $(PROGS) diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/agpsupport.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/agpsupport.c index fb58154d6..d60edc2ed 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/agpsupport.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/agpsupport.c @@ -159,6 +159,8 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, unsigned int cmd, -EFAULT); if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) return -ENOMEM; + + memset(entry, 0, sizeof(*entry)); pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; type = (u32) request.type; @@ -253,9 +255,15 @@ int drm_agp_free(struct inode *inode, struct file *filp, unsigned int cmd, -EFAULT); if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; +#if 0 if (entry->bound) drm_unbind_agp(entry->memory); - entry->prev->next = entry->next; - entry->next->prev = entry->prev; +#endif + if(entry->prev) entry->prev->next = entry->next; + if(entry->next) entry->next->prev = entry->prev; + if((entry->next == NULL) && + (entry->prev == NULL)) { + dev->agp->memory = NULL; + } drm_free_agp(entry->memory, entry->pages); drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); return 0; @@ -269,15 +277,12 @@ drm_agp_head_t *drm_agp_init(void) for (fill = &drm_agp_fill[0]; fill->name; fill++) { char *n = (char *)fill->name; -#if 0 - *fill->f = (drm_agp_func_u)get_module_symbol(NULL, n); -#endif *fill->f = (drm_agp_func_u)get_module_symbol(NULL, n); - printk("%s resolves to 0x%08lx\n", n, (*fill->f).address); + DRM_DEBUG("%s resolves to 0x%08lx\n", n, (*fill->f).address); if (!(*fill->f).address) agp_available = 0; } - printk("agp_available = %d\n", agp_available); + DRM_DEBUG("agp_available = %d\n", agp_available); if (agp_available) { if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS))) diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/bufs.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/bufs.c index 85244c7dc..7902f0ccf 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/bufs.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/bufs.c @@ -102,6 +102,11 @@ int drm_addmap(struct inode *inode, struct file *filp, unsigned int cmd, dev->lock.hw_lock = map->handle; /* Pointer to lock */ } break; +#ifdef DRM_AGP + case _DRM_AGP: + map->offset = map->offset + dev->agp->base; + break; +#endif default: drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; @@ -172,7 +177,7 @@ int drm_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; if (dev->queue_count) return -EBUSY; /* Not while in use */ - alignment = (request.flags & DRM_PAGE_ALIGN) ? PAGE_ALIGN(size) :size; + alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size):size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/ctxbitmap.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/ctxbitmap.c index f67209d44..c3e64a316 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/ctxbitmap.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/ctxbitmap.c @@ -53,7 +53,7 @@ int drm_ctxbitmap_next(drm_device_t *dev) bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP); if (bit < DRM_MAX_CTXBITMAP) { set_bit(bit, dev->ctx_bitmap); - printk("drm_ctxbitmap_next bit : %d\n", bit); + DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit); return bit; } return -1; @@ -72,7 +72,7 @@ int drm_ctxbitmap_init(drm_device_t *dev) memset((void *) dev->ctx_bitmap, 0, PAGE_SIZE * 4); for(i = 0; i < DRM_RESERVED_CONTEXTS; i++) { temp = drm_ctxbitmap_next(dev); - printk("drm_ctxbitmap_init : %d\n", temp); + DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp); } return 0; diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/dma.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/dma.c index 8291e52e4..37ab674f8 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/dma.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/dma.c @@ -63,15 +63,24 @@ void drm_dma_takedown(drm_device_t *dev) dma->bufs[i].page_order, DRM_MEM_DMA); } - drm_free(dma->bufs[i].buflist, - dma->buf_count - * sizeof(*dma->bufs[0].buflist), - DRM_MEM_BUFS); drm_free(dma->bufs[i].seglist, - dma->buf_count + dma->bufs[i].seg_count * sizeof(*dma->bufs[0].seglist), DRM_MEM_SEGS); - drm_freelist_destroy(&dma->bufs[i].freelist); + } + if(dma->bufs[i].buf_count) { + for(j = 0; j < dma->bufs[i].buf_count; j++) { + if(dma->bufs[i].buflist[j].dev_private) { + drm_free(dma->bufs[i].buflist[j].dev_private, + dma->bufs[i].buflist[j].dev_priv_size, + DRM_MEM_BUFS); + } + } + drm_free(dma->bufs[i].buflist, + dma->bufs[i].buf_count * + sizeof(*dma->bufs[0].buflist), + DRM_MEM_BUFS); + drm_freelist_destroy(&dma->bufs[i].freelist); } } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drm.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drm.h index 7b8e88265..ebc6f7e79 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drm.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drm.h @@ -101,7 +101,8 @@ typedef struct drm_control { typedef enum drm_map_type { _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */ _DRM_REGISTERS = 1, /* no caching, no core dump */ - _DRM_SHM = 2 /* shared, cached */ + _DRM_SHM = 2, /* shared, cached */ + _DRM_AGP = 3 /* AGP/GART */ } drm_map_type_t; typedef enum drm_map_flags { @@ -165,8 +166,11 @@ typedef struct drm_buf_desc { int low_mark; /* Low water mark */ int high_mark; /* High water mark */ enum { - DRM_PAGE_ALIGN = 0x01 /* Align on page boundaries for DMA */ + _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */ } flags; + unsigned long agp_start; /* Start address of where the agp buffers + * are in the agp aperture */ } drm_buf_desc_t; typedef struct drm_buf_info { @@ -237,6 +241,38 @@ typedef struct drm_irq_busid { int funcnum; } drm_irq_busid_t; +typedef struct drm_agp_mode { + unsigned long mode; +} drm_agp_mode_t; + + /* For drm_agp_alloc -- allocated a buffer */ +typedef struct drm_agp_buffer { + unsigned long size; /* In bytes -- will round to page boundary */ + unsigned long handle; /* Used for BIND/UNBIND ioctls */ + unsigned long type; /* Type of memory to allocate */ + unsigned long physical; /* Physical used by i810 */ +} drm_agp_buffer_t; + + /* For drm_agp_bind */ +typedef struct drm_agp_binding { + unsigned long handle; /* From drm_agp_buffer */ + unsigned long offset; /* In bytes -- will round to page boundary */ +} drm_agp_binding_t; + +typedef struct drm_agp_info { + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ + unsigned short id_vendor; + unsigned short id_device; +} drm_agp_info_t; + #define DRM_IOCTL_BASE 'd' #define DRM_IOCTL_NR(n) _IOC_NR(n) #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) @@ -276,4 +312,14 @@ typedef struct drm_irq_busid { #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) +#define DRM_IOCTL_AGP_ENABLE DRM_IOR( 0x32, drm_agp_mode_t) +#define DRM_IOCTL_AGP_INFO DRM_IOW( 0x33, drm_agp_info_t) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_BIND DRM_IOWR(0x36, drm_agp_binding_t) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) + +/* 0x40 is reserved for mga dma init */ #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmP.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmP.h index 312fba36f..c00d3bb08 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmP.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmP.h @@ -48,8 +48,12 @@ #ifdef CONFIG_MTRR #include <asm/mtrr.h> #endif +#ifdef DRM_AGP +#include <linux/types.h> +#include <linux/agp_backend.h> +#endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,0) -#include <asm/spinlock.h> +#include <linux/spinlock.h> #include <linux/poll.h> #endif #include "drm.h" @@ -69,21 +73,27 @@ #define DRM_FLAG_DEBUG 0x01 #define DRM_FLAG_NOCTX 0x02 -#define DRM_MEM_DMA 0 -#define DRM_MEM_SAREA 1 -#define DRM_MEM_DRIVER 2 -#define DRM_MEM_MAGIC 3 -#define DRM_MEM_IOCTLS 4 -#define DRM_MEM_MAPS 5 -#define DRM_MEM_VMAS 6 -#define DRM_MEM_BUFS 7 -#define DRM_MEM_SEGS 8 -#define DRM_MEM_PAGES 9 -#define DRM_MEM_FILES 10 -#define DRM_MEM_QUEUES 11 -#define DRM_MEM_CMDS 12 -#define DRM_MEM_MAPPINGS 13 -#define DRM_MEM_BUFLISTS 14 +#define DRM_MEM_DMA 0 +#define DRM_MEM_SAREA 1 +#define DRM_MEM_DRIVER 2 +#define DRM_MEM_MAGIC 3 +#define DRM_MEM_IOCTLS 4 +#define DRM_MEM_MAPS 5 +#define DRM_MEM_VMAS 6 +#define DRM_MEM_BUFS 7 +#define DRM_MEM_SEGS 8 +#define DRM_MEM_PAGES 9 +#define DRM_MEM_FILES 10 +#define DRM_MEM_QUEUES 11 +#define DRM_MEM_CMDS 12 +#define DRM_MEM_MAPPINGS 13 +#define DRM_MEM_BUFLISTS 14 +#define DRM_MEM_AGPLISTS 15 +#define DRM_MEM_TOTALAGP 16 +#define DRM_MEM_BOUNDAGP 17 +#define DRM_MEM_CTXBITMAP 18 + +#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 4 * 8) /* Backward compatibility section */ /* _PAGE_WT changed to _PAGE_PWT in 2.2.6 */ @@ -235,6 +245,7 @@ typedef struct drm_buf { int used; /* Amount of buffer in use (for DMA) */ unsigned long offset; /* Byte offset (used internally) */ void *address; /* Address of buffer */ + unsigned long bus_address; /* Bus address of buffer */ struct drm_buf *next; /* Kernel-only: used for free list */ __volatile__ int waiting; /* On kernel DMA queue */ __volatile__ int pending; /* On hardware DMA queue */ @@ -250,6 +261,11 @@ typedef struct drm_buf { DRM_LIST_PRIO = 4, DRM_LIST_RECLAIM = 5 } list; /* Which list we're on */ + + + void *dev_private; + int dev_priv_size; + #if DRM_DMA_HISTOGRAM cycles_t time_queued; /* Queued to kernel DMA queue */ cycles_t time_dispatched; /* Dispatched to hardware */ @@ -376,6 +392,9 @@ typedef struct drm_device_dma { int page_count; unsigned long *pagelist; unsigned long byte_count; + enum { + _DRM_DMA_USE_AGP = 0x01 + } flags; /* DMA support */ drm_buf_t *this_buffer; /* Buffer being sent */ @@ -384,6 +403,41 @@ typedef struct drm_device_dma { wait_queue_head_t waiting; /* Processes waiting on free bufs */ } drm_device_dma_t; +#ifdef DRM_AGP +typedef struct drm_agp_mem { + unsigned long handle; + agp_memory *memory; + unsigned long bound; /* address */ + int pages; + struct drm_agp_mem *prev; + struct drm_agp_mem *next; +} drm_agp_mem_t; + +typedef struct drm_agp_head { + agp_kern_info agp_info; + const char *chipset; + drm_agp_mem_t *memory; + unsigned long mode; + int enabled; + int acquired; + unsigned long base; + int agp_mtrr; +} drm_agp_head_t; + +typedef struct { + void (*free_memory)(agp_memory *); + agp_memory *(*allocate_memory)(size_t, u32); + int (*bind_memory)(agp_memory *, off_t); + int (*unbind_memory)(agp_memory *); + void (*enable)(u32); + int (*acquire)(void); + void (*release)(void); + void (*copy_info)(agp_kern_info *); +} drm_agp_func_t; + +extern drm_agp_func_t drm_agp; +#endif + typedef struct drm_device { const char *name; /* Simple driver name */ char *unique; /* Unique identifier: e.g., busid */ @@ -462,6 +516,12 @@ typedef struct drm_device { struct fasync_struct *buf_async;/* Processes waiting for SIGIO */ wait_queue_head_t buf_readers; /* Processes waiting to read */ wait_queue_head_t buf_writers; /* Processes waiting to ctx switch */ + +#ifdef DRM_AGP + drm_agp_head_t *agp; +#endif + unsigned long *ctx_bitmap; + void *dev_private; } drm_device_t; @@ -533,6 +593,14 @@ extern void drm_free_pages(unsigned long address, int order, extern void *drm_ioremap(unsigned long offset, unsigned long size); extern void drm_ioremapfree(void *pt, unsigned long size); +#ifdef DRM_AGP +extern agp_memory *drm_alloc_agp(int pages, u32 type); +extern int drm_free_agp(agp_memory *handle, int pages); +extern int drm_bind_agp(agp_memory *handle, unsigned int start); +extern int drm_unbind_agp(agp_memory *handle); +#endif + + /* Buffer management support (bufs.c) */ extern int drm_order(unsigned long size); extern int drm_addmap(struct inode *inode, struct file *filp, @@ -642,5 +710,32 @@ extern int drm_flush_unblock(drm_device_t *dev, int context, drm_lock_flags_t flags); extern int drm_flush_block_and_flush(drm_device_t *dev, int context, drm_lock_flags_t flags); + + /* Context Bitmap support (ctxbitmap.c) */ +extern int drm_ctxbitmap_init(drm_device_t *dev); +extern void drm_ctxbitmap_cleanup(drm_device_t *dev); +extern int drm_ctxbitmap_next(drm_device_t *dev); +extern void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle); + +#ifdef DRM_AGP + /* AGP/GART support (agpsupport.c) */ +extern drm_agp_head_t *drm_agp_init(void); +extern int drm_agp_acquire(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_release(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_enable(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_info(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +#endif #endif #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmstat.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmstat.c index 8fe6f7072..a96a38b26 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmstat.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drmstat.c @@ -187,7 +187,7 @@ int main(int argc, char **argv) case 'b': count = strtoul(optarg, &pt, 0); size = strtoul(pt+1, NULL, 0); - if ((r = drmAddBufs(fd, count, size, 0)) < 0) { + if ((r = drmAddBufs(fd, count, size, 0, 65536)) < 0) { drmError(r, argv[0]); return 1; } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/gamma_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/gamma_drv.c index ce970835a..a3c2bd4a0 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/gamma_drv.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/gamma_drv.c @@ -271,6 +271,10 @@ static int gamma_takedown(drm_device_t *dev) - PAGE_SHIFT, DRM_MEM_SAREA); break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; } drm_free(map, sizeof(*map), DRM_MEM_MAPS); } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_bufs.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_bufs.c index 49455b434..be041f141 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_bufs.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_bufs.c @@ -32,6 +32,8 @@ #define __NO_VERSION__ #include "drmP.h" +#include "i810_drv.h" +#include "i810_dma.h" #include "linux/un.h" int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, @@ -99,33 +101,38 @@ int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, entry->buf_size = size; entry->page_order = page_order; + offset = 0; while(entry->buf_count < count) { - for(offset = 0; offset + size <= total && entry->buf_count < count; - offset += alignment, ++entry->buf_count) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - buf->offset = agp_offset - dev->agp->base + offset;/* ?? */ - buf->bus_address = agp_offset + offset; - buf->address = agp_offset + offset + dev->agp->base; - buf->next = NULL; - buf->waiting = 0; - buf->pending = 0; - init_waitqueue_head(&buf->dma_wait); - buf->pid = 0; + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = offset; + buf->bus_address = dev->agp->base + agp_offset + offset; + buf->address = (void *)(agp_offset + offset + dev->agp->base); + buf->next = NULL; + buf->waiting = 0; + buf->pending = 0; + init_waitqueue_head(&buf->dma_wait); + buf->pid = 0; + + buf->dev_private = drm_alloc(sizeof(drm_i810_buf_priv_t), DRM_MEM_BUFS); + buf->dev_priv_size = sizeof(drm_i810_buf_priv_t); + #if DRM_DMA_HISTOGRAM - buf->time_queued = 0; - buf->time_dispatched = 0; - buf->time_completed = 0; - buf->time_freed = 0; + buf->time_queued = 0; + buf->time_dispatched = 0; + buf->time_completed = 0; + buf->time_freed = 0; #endif - DRM_DEBUG("buffer %d @ %p\n", - entry->buf_count, buf->address); - } + offset = offset + alignment; + entry->buf_count++; byte_count += PAGE_SIZE << page_order; + + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); } dma->buflist = drm_realloc(dma->buflist, @@ -137,8 +144,7 @@ int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, dma->buflist[i] = &entry->buflist[i - dma->buf_count]; dma->buf_count += entry->buf_count; - dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); - + dma->byte_count += byte_count; drm_freelist_create(&entry->freelist, entry->buf_count); for (i = 0; i < entry->buf_count; i++) { drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); @@ -155,170 +161,10 @@ int i810_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, -EFAULT); atomic_dec(&dev->buf_alloc); + dma->flags = _DRM_DMA_USE_AGP; return 0; } -int i810_addbufs_pci(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) -{ - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_device_dma_t *dma = dev->dma; - drm_buf_desc_t request; - int count; - int order; - int size; - int total; - int page_order; - drm_buf_entry_t *entry; - unsigned long page; - drm_buf_t *buf; - int alignment; - unsigned long offset; - int i; - int byte_count; - int page_count; - - if (!dma) return -EINVAL; - - copy_from_user_ret(&request, - (drm_buf_desc_t *)arg, - sizeof(request), - -EFAULT); - - count = request.count; - order = drm_order(request.size); - size = 1 << order; - - DRM_DEBUG("count = %d, size = %d (%d), order = %d, queue_count = %d\n", - request.count, request.size, size, order, dev->queue_count); - - if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) return -EINVAL; - if (dev->queue_count) return -EBUSY; /* Not while in use */ - - alignment = (request.flags & _DRM_PAGE_ALIGN) ? PAGE_ALIGN(size) :size; - page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; - total = PAGE_SIZE << page_order; - - spin_lock(&dev->count_lock); - if (dev->buf_use) { - spin_unlock(&dev->count_lock); - return -EBUSY; - } - atomic_inc(&dev->buf_alloc); - spin_unlock(&dev->count_lock); - - down(&dev->struct_sem); - entry = &dma->bufs[order]; - if (entry->buf_count) { - up(&dev->struct_sem); - atomic_dec(&dev->buf_alloc); - return -ENOMEM; /* May only call once for each order */ - } - - entry->buflist = drm_alloc(count * sizeof(*entry->buflist), - DRM_MEM_BUFS); - if (!entry->buflist) { - up(&dev->struct_sem); - atomic_dec(&dev->buf_alloc); - return -ENOMEM; - } - memset(entry->buflist, 0, count * sizeof(*entry->buflist)); - - entry->seglist = drm_alloc(count * sizeof(*entry->seglist), - DRM_MEM_SEGS); - if (!entry->seglist) { - drm_free(entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS); - up(&dev->struct_sem); - atomic_dec(&dev->buf_alloc); - return -ENOMEM; - } - memset(entry->seglist, 0, count * sizeof(*entry->seglist)); - - dma->pagelist = drm_realloc(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES); - DRM_DEBUG("pagelist: %d entries\n", - dma->page_count + (count << page_order)); - - - entry->buf_size = size; - entry->page_order = page_order; - byte_count = 0; - page_count = 0; - while (entry->buf_count < count) { - if (!(page = drm_alloc_pages(page_order, DRM_MEM_DMA))) break; - entry->seglist[entry->seg_count++] = page; - for (i = 0; i < (1 << page_order); i++) { - DRM_DEBUG("page %d @ 0x%08lx\n", - dma->page_count + page_count, - page + PAGE_SIZE * i); - dma->pagelist[dma->page_count + page_count++] - = page + PAGE_SIZE * i; - } - for (offset = 0; - offset + size <= total && entry->buf_count < count; - offset += alignment, ++entry->buf_count) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - buf->offset = (dma->byte_count + byte_count + offset); - buf->address = (void *)(page + offset); - buf->next = NULL; - buf->waiting = 0; - buf->pending = 0; - init_waitqueue_head(&buf->dma_wait); - buf->pid = 0; -#if DRM_DMA_HISTOGRAM - buf->time_queued = 0; - buf->time_dispatched = 0; - buf->time_completed = 0; - buf->time_freed = 0; -#endif - DRM_DEBUG("buffer %d @ %p\n", - entry->buf_count, buf->address); - } - byte_count += PAGE_SIZE << page_order; - } - - dma->buflist = drm_realloc(dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS); - for (i = dma->buf_count; i < dma->buf_count + entry->buf_count; i++) - dma->buflist[i] = &entry->buflist[i - dma->buf_count]; - - dma->buf_count += entry->buf_count; - dma->seg_count += entry->seg_count; - dma->page_count += entry->seg_count << page_order; - dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); - - drm_freelist_create(&entry->freelist, entry->buf_count); - for (i = 0; i < entry->buf_count; i++) { - drm_freelist_put(dev, &entry->freelist, &entry->buflist[i]); - } - - up(&dev->struct_sem); - - request.count = entry->buf_count; - request.size = size; - - copy_to_user_ret((drm_buf_desc_t *)arg, - &request, - sizeof(request), - -EFAULT); - - atomic_dec(&dev->buf_alloc); - return 0; -} - int i810_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { @@ -332,7 +178,7 @@ int i810_addbufs(struct inode *inode, struct file *filp, unsigned int cmd, if(request.flags & _DRM_AGP_BUFFER) return i810_addbufs_agp(inode, filp, cmd, arg); else - return i810_addbufs_pci(inode, filp, cmd, arg); + return -EINVAL; } int i810_infobufs(struct inode *inode, struct file *filp, unsigned int cmd, @@ -506,6 +352,7 @@ int i810_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, spin_lock(&dev->count_lock); if (atomic_read(&dev->buf_alloc)) { spin_unlock(&dev->count_lock); + DRM_DEBUG("Busy\n"); return -EBUSY; } ++dev->buf_use; /* Can't allocate more after this call */ @@ -515,70 +362,79 @@ int i810_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, (drm_buf_map_t *)arg, sizeof(request), -EFAULT); - - if (request.count >= dma->buf_count) { + DRM_DEBUG("dma->flags : %lx\n", dma->flags); + if (request.count >= dma->buf_count) { if(dma->flags & _DRM_DMA_USE_AGP) { - /* This is an ugly vicious hack */ + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; drm_map_t *map = NULL; - for(i = 0; i < dev->map_count; i++) { - map = dev->maplist[i]; - if(map->type == _DRM_AGP) break; - } - if (i >= dev->map_count || !map) { + + map = dev->maplist[dev_priv->buffer_map_idx]; + if (!map) { + DRM_DEBUG("map is null\n"); retcode = -EINVAL; goto done; } - + DRM_DEBUG("map->offset : %lx\n", map->offset); + DRM_DEBUG("map->size : %lx\n", map->size); + DRM_DEBUG("map->type : %d\n", map->type); + DRM_DEBUG("map->flags : %x\n", map->flags); + DRM_DEBUG("map->handle : %lx\n", map->handle); + DRM_DEBUG("map->mtrr : %d\n", map->mtrr); + down(¤t->mm->mmap_sem); virtual = do_mmap(filp, 0, map->size, PROT_READ|PROT_WRITE, - MAP_SHARED, (unsigned long)map->handle); - } - else { + MAP_SHARED, (unsigned long)map->offset); + up(¤t->mm->mmap_sem); + } else { + down(¤t->mm->mmap_sem); virtual = do_mmap(filp, 0, dma->byte_count, PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up(¤t->mm->mmap_sem); + } + if (virtual > -1024UL) { + /* Real error */ + DRM_DEBUG("mmap error\n"); + retcode = (signed long)virtual; + goto done; + } + request.virtual = (void *)virtual; + + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { + retcode = -EFAULT; + goto done; + } + if (copy_to_user(&request.list[i].used, + &zero, + sizeof(zero))) { + retcode = -EFAULT; + goto done; + } + address = virtual + dma->buflist[i]->offset; + if (copy_to_user(&request.list[i].address, + &address, + sizeof(address))) { + retcode = -EFAULT; + goto done; + } } - if (virtual > -1024UL) { - /* Real error */ - retcode = (signed long)virtual; - goto done; - } - request.virtual = (void *)virtual; - - for (i = 0; i < dma->buf_count; i++) { - if (copy_to_user(&request.list[i].idx, - &dma->buflist[i]->idx, - sizeof(request.list[0].idx))) { - retcode = -EFAULT; - goto done; - } - if (copy_to_user(&request.list[i].total, - &dma->buflist[i]->total, - sizeof(request.list[0].total))) { - retcode = -EFAULT; - goto done; - } - if (copy_to_user(&request.list[i].used, - &zero, - sizeof(zero))) { - retcode = -EFAULT; - goto done; - } - address = virtual + dma->buflist[i]->offset; - if (copy_to_user(&request.list[i].address, - &address, - sizeof(address))) { - retcode = -EFAULT; - goto done; - } - } } -done: - request.count = dma->buf_count; - DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); - - copy_to_user_ret((drm_buf_map_t *)arg, - &request, - sizeof(request), - -EFAULT); + done: + request.count = dma->buf_count; + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); + + copy_to_user_ret((drm_buf_map_t *)arg, + &request, + sizeof(request), + -EFAULT); - return retcode; + DRM_DEBUG("retcode : %d\n", retcode); + return retcode; } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_context.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_context.c new file mode 100644 index 000000000..5503edf24 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_context.c @@ -0,0 +1,205 @@ +/* i810_context.c -- IOCTLs for i810 contexts -*- linux-c -*- + * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * + * $XFree86$ + * + */ + +#include <linux/sched.h> + +#define __NO_VERSION__ +#include "drmP.h" +#include "i810_drv.h" + +static int i810_alloc_queue(drm_device_t *dev) +{ + int temp = drm_ctxbitmap_next(dev); + DRM_DEBUG("i810_alloc_queue: %d\n", temp); + return temp; +} + +int i810_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + i810_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int i810_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + +int i810_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + copy_from_user_ret(&res, (drm_ctx_res_t *)arg, sizeof(res), -EFAULT); + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + copy_to_user_ret(&res.contexts[i], + &i, + sizeof(i), + -EFAULT); + } + } + res.count = DRM_RESERVED_CONTEXTS; + copy_to_user_ret((drm_ctx_res_t *)arg, &res, sizeof(res), -EFAULT); + return 0; +} + +int i810_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + if ((ctx.handle = i810_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = i810_alloc_queue(dev); + } + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + DRM_DEBUG("%d\n", ctx.handle); + copy_to_user_ret((drm_ctx_t *)arg, &ctx, sizeof(ctx), -EFAULT); + return 0; +} + +int i810_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + /* This does nothing for the i810 */ + return 0; +} + +int i810_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t*)arg, sizeof(ctx), -EFAULT); + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + copy_to_user_ret((drm_ctx_t*)arg, &ctx, sizeof(ctx), -EFAULT); + return 0; +} + +int i810_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + return i810_context_switch(dev, dev->last_context, ctx.handle); +} + +int i810_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + i810_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int i810_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + if(ctx.handle != DRM_KERNEL_CONTEXT) { + drm_ctxbitmap_free(dev, ctx.handle); + } + + return 0; +} diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.c index 09959b657..e79f7ff5d 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.c @@ -24,7 +24,8 @@ * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith <faith@precisioninsight.com> - * Jeff Hartmann <jhartmann@precisioninsight.com> + * Jeff Hartmann <jhartmann@precisioninsight.com> + * Keith Whitwell <keithw@precisioninsight.com> * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.c,v 1.1 2000/02/11 17:26:04 dawes Exp $ * @@ -32,9 +33,15 @@ #define __NO_VERSION__ #include "drmP.h" +#include "i810_drm_public.h" #include "i810_drv.h" +#include "i810_dma.h" #include <linux/interrupt.h> /* For task queue support */ +#include <linux/time.h> /* For do_gettimeofday */ + +#define I810_BUF_FREE 1 +#define I810_BUF_USED 0 #define I810_REG(reg) 2 #define I810_BASE(reg) ((unsigned long) \ @@ -43,544 +50,460 @@ #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) #define I810_READ(reg) I810_DEREF(reg) #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) - -void i810_dma_init(drm_device_t *dev) +#define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) +#define I810_READ16(reg) I810_DEREF16(reg) +#define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) + +#define RING_LOCALS unsigned int outring, ringmask; volatile char *virt; + +#define BEGIN_LP_RING(n) do { \ + if (I810_VERBOSE) \ + DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__); \ + if (dev_priv->ring.space < n*4) i810_wait_ring(dev, n*4, 0); \ + dev_priv->ring.space -= n*4; \ + outring = dev_priv->ring.tail; \ + ringmask = dev_priv->ring.tail_mask; \ + virt = dev_priv->ring.virtual_start; \ +} while (0) + +#define ADVANCE_LP_RING() do { \ + if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ + dev_priv->ring.tail = outring; \ + I810_WRITE(LP_RING + RING_TAIL, outring); \ +} while(0) + +#define OUT_RING(n) do { \ + if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ + *(volatile unsigned int *)(virt + outring) = n; \ + outring += 4; \ + outring &= ringmask; \ +} while (0); + +static inline void i810_print_status_page(drm_device_t *dev) { - printk(KERN_INFO "i810_dma_init\n"); + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = dev->dev_private; + u32 *temp = (u32 *)dev_priv->hw_status_page; + int i; + + DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]); + DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]); + DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]); + DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]); + DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]); + for(i = 6; i < dma->buf_count + 6; i++) { + DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]); + } } -void i810_dma_cleanup(drm_device_t *dev) +static drm_buf_t *i810_freelist_get(drm_device_t *dev) { - printk(KERN_INFO "i810_dma_cleanup\n"); + drm_device_dma_t *dma = dev->dma; + int i; + int used; + + /* Linear search might not be the best solution */ + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, + I810_BUF_USED); + if(used == I810_BUF_FREE) { + return buf; + } + } + return NULL; } -static inline void i810_dma_dispatch(drm_device_t *dev, unsigned long address, - unsigned long length) +/* This should only be called if the buffer is not sent to the hardware + * yet, the hardware updates in use for us once its on the ring buffer. + */ + +static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) { - printk(KERN_INFO "i810_dma_dispatch\n"); + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_USED, I810_BUF_FREE); + if(used != I810_BUF_USED) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; + } + + return 0; } -static inline void i810_dma_quiescent(drm_device_t *dev) +static int i810_dma_get_buffers(drm_device_t *dev, drm_dma_t *d) { + int i; + drm_buf_t *buf; + + for (i = d->granted_count; i < d->request_count; i++) { + buf = i810_freelist_get(dev); + if (!buf) break; + buf->pid = current->pid; + copy_to_user_ret(&d->request_indices[i], + &buf->idx, + sizeof(buf->idx), + -EFAULT); + copy_to_user_ret(&d->request_sizes[i], + &buf->total, + sizeof(buf->total), + -EFAULT); + ++d->granted_count; + } + return 0; } -static inline void i810_dma_ready(drm_device_t *dev) +static unsigned long i810_alloc_page(drm_device_t *dev) { - i810_dma_quiescent(dev); - printk(KERN_INFO "i810_dma_ready\n"); + unsigned long address; + + address = __get_free_page(GFP_KERNEL); + if(address == 0UL) { + return 0; + } + atomic_inc(&mem_map[MAP_NR((void *) address)].count); + set_bit(PG_locked, &mem_map[MAP_NR((void *) address)].flags); + + return address; } -static inline int i810_dma_is_ready(drm_device_t *dev) +static void i810_free_page(drm_device_t *dev, unsigned long page) { - - i810_dma_quiescent(dev); - - printk(KERN_INFO "i810_dma_is_ready\n"); - return 1; + if(page == 0UL) { + return; + } + atomic_dec(&mem_map[MAP_NR((void *) page)].count); + clear_bit(PG_locked, &mem_map[MAP_NR((void *) page)].flags); + wake_up(&mem_map[MAP_NR((void *) page)].wait); + free_page(page); + return; } - -static void i810_dma_service(int irq, void *device, struct pt_regs *regs) +static int i810_dma_cleanup(drm_device_t *dev) { - drm_device_t *dev = (drm_device_t *)device; - drm_device_dma_t *dma = dev->dma; - - atomic_inc(&dev->total_irq); - if (i810_dma_is_ready(dev)) { - /* Free previous buffer */ - if (test_and_set_bit(0, &dev->dma_flag)) { - atomic_inc(&dma->total_missed_free); - return; + if(dev->dev_private) { + drm_i810_private_t *dev_priv = + (drm_i810_private_t *) dev->dev_private; + + if(dev_priv->ring.virtual_start) { + drm_ioremapfree((void *) dev_priv->ring.virtual_start, + dev_priv->ring.Size); } - if (dma->this_buffer) { - drm_free_buffer(dev, dma->this_buffer); - dma->this_buffer = NULL; + if(dev_priv->hw_status_page != 0UL) { + i810_free_page(dev, dev_priv->hw_status_page); + /* Need to rewrite hardware status page */ + I810_WRITE(0x02080, 0x1ffff000); } - clear_bit(0, &dev->dma_flag); - - /* Dispatch new buffer */ - queue_task(&dev->tq, &tq_immediate); - mark_bh(IMMEDIATE_BH); + drm_free(dev->dev_private, sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; } + return 0; } -/* Only called by i810_dma_schedule. */ -static int i810_do_dma(drm_device_t *dev, int locked) +static int __gettimeinmillis(void) { - unsigned long address; - unsigned long length; - drm_buf_t *buf; - int retcode = 0; - drm_device_dma_t *dma = dev->dma; -#if DRM_DMA_HISTOGRAM - cycles_t dma_start, dma_stop; -#endif - - if (test_and_set_bit(0, &dev->dma_flag)) { - atomic_inc(&dma->total_missed_dma); - return -EBUSY; - } - -#if DRM_DMA_HISTOGRAM - dma_start = get_cycles(); -#endif - - if (!dma->next_buffer) { - DRM_ERROR("No next_buffer\n"); - clear_bit(0, &dev->dma_flag); - return -EINVAL; - } - - buf = dma->next_buffer; - address = (unsigned long)buf->bus_address; - length = buf->used; - - - DRM_DEBUG("context %d, buffer %d (%ld bytes)\n", - buf->context, buf->idx, length); - - if (buf->list == DRM_LIST_RECLAIM) { - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - clear_bit(0, &dev->dma_flag); - return -EINVAL; - } + int millis; + + millis = ((jiffies / HZ) * 1000) + ((jiffies % HZ) * (1000 / HZ)); + return millis; +} - if (!length) { - DRM_ERROR("0 length buffer\n"); - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - clear_bit(0, &dev->dma_flag); - return 0; - } +static int i810_wait_ring(drm_device_t *dev, int n, int timeout_millis) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + int startTime = 0; + int curTime = 0; + + if (timeout_millis == 0) timeout_millis = 3000; + + while (ring->space < n) { + int i; - if (!i810_dma_is_ready(dev)) { - clear_bit(0, &dev->dma_flag); - return -EBUSY; - } - - if (buf->while_locked) { - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("Dispatching buffer %d from pid %d" - " \"while locked\", but no lock held\n", - buf->idx, buf->pid); + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail+8); + + if (ring->space < 0) ring->space += ring->Size; + + iters++; + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; } - } else { - if (!locked && !drm_lock_take(&dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - atomic_inc(&dma->total_missed_lock); - clear_bit(0, &dev->dma_flag); - return -EBUSY; - } - } - - if (dev->last_context != buf->context - && !(dev->queuelist[buf->context]->flags - & _DRM_CONTEXT_PRESERVED)) { - /* PRE: dev->last_context != buf->context */ - if (drm_context_switch(dev, dev->last_context, buf->context)) { - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - } - retcode = -EBUSY; - goto cleanup; - - /* POST: we will wait for the context - switch and will dispatch on a later call - when dev->last_context == buf->context. - NOTE WE HOLD THE LOCK THROUGHOUT THIS - TIME! */ - } - - drm_clear_next_buffer(dev); - buf->pending = 1; - buf->waiting = 0; - buf->list = DRM_LIST_PEND; -#if DRM_DMA_HISTOGRAM - buf->time_dispatched = get_cycles(); -#endif - - i810_dma_dispatch(dev, address, length); - drm_free_buffer(dev, dma->this_buffer); - dma->this_buffer = buf; - - atomic_add(length, &dma->total_bytes); - atomic_inc(&dma->total_dmas); - if (!buf->while_locked && !dev->context_flag && !locked) { - if (drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - DRM_ERROR("\n"); - } + for (i = 0 ; i < 2000 ; i++) ; } -cleanup: - - clear_bit(0, &dev->dma_flag); - -#if DRM_DMA_HISTOGRAM - dma_stop = get_cycles(); - atomic_inc(&dev->histo.dma[drm_histogram_slot(dma_stop - dma_start)]); -#endif - - return retcode; -} - -static void i810_dma_schedule_timer_wrapper(unsigned long dev) -{ - i810_dma_schedule((drm_device_t *)dev, 0); +out_wait_ring: + + return iters; } -static void i810_dma_schedule_tq_wrapper(void *dev) +static void i810_kernel_lost_context(drm_device_t *dev) { - i810_dma_schedule(dev, 0); + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I810_READ(LP_RING + RING_TAIL); + ring->space = ring->head - (ring->tail+8); + if (ring->space < 0) ring->space += ring->Size; } -int i810_dma_schedule(drm_device_t *dev, int locked) +static int i810_freelist_init(drm_device_t *dev) { - int next; - drm_queue_t *q; - drm_buf_t *buf; - int retcode = 0; - int processed = 0; - int missed; - int expire = 20; - drm_device_dma_t *dma = dev->dma; -#if DRM_DMA_HISTOGRAM - cycles_t schedule_start; -#endif - - if (test_and_set_bit(0, &dev->interrupt_flag)) { - /* Not reentrant */ - atomic_inc(&dma->total_missed_sched); - return -EBUSY; - } - missed = atomic_read(&dma->total_missed_sched); - -#if DRM_DMA_HISTOGRAM - schedule_start = get_cycles(); -#endif - -again: - if (dev->context_flag) { - clear_bit(0, &dev->interrupt_flag); - return -EBUSY; - } - if (dma->next_buffer) { - /* Unsent buffer that was previously - selected, but that couldn't be sent - because the lock could not be obtained - or the DMA engine wasn't ready. Try - again. */ - atomic_inc(&dma->total_tried); - if (!(retcode = i810_do_dma(dev, locked))) { - atomic_inc(&dma->total_hit); - ++processed; - } - } else { - do { - next = drm_select_queue(dev, - i810_dma_schedule_timer_wrapper); - if (next >= 0) { - q = dev->queuelist[next]; - buf = drm_waitlist_get(&q->waitlist); - dma->next_buffer = buf; - dma->next_queue = q; - if (buf && buf->list == DRM_LIST_RECLAIM) { - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - } - } - } while (next >= 0 && !dma->next_buffer); - if (dma->next_buffer) { - if (!(retcode = i810_do_dma(dev, locked))) { - ++processed; - } - } + drm_device_dma_t *dma = dev->dma; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u8 *hw_status = (u8 *)dev_priv->hw_status_page; + int i; + int my_idx = 24; + + if(dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; } - if (--expire) { - if (missed != atomic_read(&dma->total_missed_sched)) { - atomic_inc(&dma->total_lost); - if (i810_dma_is_ready(dev)) goto again; - } - if (processed && i810_dma_is_ready(dev)) { - atomic_inc(&dma->total_lost); - processed = 0; - goto again; - } + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + buf_priv->in_use = hw_status + my_idx; + DRM_DEBUG("buf_priv->in_use : %p\n", buf_priv->in_use); + *buf_priv->in_use = I810_BUF_FREE; + buf_priv->my_use_idx = my_idx; + my_idx += 4; } - - clear_bit(0, &dev->interrupt_flag); - -#if DRM_DMA_HISTOGRAM - atomic_inc(&dev->histo.schedule[drm_histogram_slot(get_cycles() - - schedule_start)]); -#endif - return retcode; + return 0; } -static int i810_dma_priority(drm_device_t *dev, drm_dma_t *d) +static int i810_dma_initialize(drm_device_t *dev, + drm_i810_private_t *dev_priv, + drm_i810_init_t *init) { - unsigned long address; - unsigned long length; - int must_free = 0; - int retcode = 0; - int i; - int idx; - drm_buf_t *buf; - drm_buf_t *last_buf = NULL; - drm_device_dma_t *dma = dev->dma; - DECLARE_WAITQUEUE(entry, current); - - /* Turn off interrupt handling */ - while (test_and_set_bit(0, &dev->interrupt_flag)) { - schedule(); - if (signal_pending(current)) return -EINTR; - } - if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) { - while (!drm_lock_take(&dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - schedule(); - if (signal_pending(current)) { - clear_bit(0, &dev->interrupt_flag); - return -EINTR; - } - } - ++must_free; - } - atomic_inc(&dma->total_prio); - - for (i = 0; i < d->send_count; i++) { - idx = d->send_indices[i]; - if (idx < 0 || idx >= dma->buf_count) { - DRM_ERROR("Index %d (of %d max)\n", - d->send_indices[i], dma->buf_count - 1); - continue; - } - buf = dma->buflist[ idx ]; - if (buf->pid != current->pid) { - DRM_ERROR("Process %d using buffer owned by %d\n", - current->pid, buf->pid); - retcode = -EINVAL; - goto cleanup; - } - if (buf->list != DRM_LIST_NONE) { - DRM_ERROR("Process %d using %d's buffer on list %d\n", - current->pid, buf->pid, buf->list); - retcode = -EINVAL; - goto cleanup; - } - /* This isn't a race condition on - buf->list, since our concern is the - buffer reclaim during the time the - process closes the /dev/drm? handle, so - it can't also be doing DMA. */ - buf->list = DRM_LIST_PRIO; - buf->used = d->send_sizes[i]; - buf->context = d->context; - buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED; - address = (unsigned long)buf->address; - length = buf->used; - if (!length) { - DRM_ERROR("0 length buffer\n"); - } - if (buf->pending) { - DRM_ERROR("Sending pending buffer:" - " buffer %d, offset %d\n", - d->send_indices[i], i); - retcode = -EINVAL; - goto cleanup; - } - if (buf->waiting) { - DRM_ERROR("Sending waiting buffer:" - " buffer %d, offset %d\n", - d->send_indices[i], i); - retcode = -EINVAL; - goto cleanup; - } - buf->pending = 1; - - if (dev->last_context != buf->context - && !(dev->queuelist[buf->context]->flags - & _DRM_CONTEXT_PRESERVED)) { - add_wait_queue(&dev->context_wait, &entry); - current->state = TASK_INTERRUPTIBLE; - /* PRE: dev->last_context != buf->context */ - drm_context_switch(dev, dev->last_context, - buf->context); - /* POST: we will wait for the context - switch and will dispatch on a later call - when dev->last_context == buf->context. - NOTE WE HOLD THE LOCK THROUGHOUT THIS - TIME! */ - schedule(); - current->state = TASK_RUNNING; - remove_wait_queue(&dev->context_wait, &entry); - if (signal_pending(current)) { - retcode = -EINTR; - goto cleanup; - } - if (dev->last_context != buf->context) { - DRM_ERROR("Context mismatch: %d %d\n", - dev->last_context, - buf->context); - } - } - -#if DRM_DMA_HISTOGRAM - buf->time_queued = get_cycles(); - buf->time_dispatched = buf->time_queued; -#endif - i810_dma_dispatch(dev, address, length); - if (drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - DRM_ERROR("\n"); - } - - atomic_add(length, &dma->total_bytes); - atomic_inc(&dma->total_dmas); - - if (last_buf) { - drm_free_buffer(dev, last_buf); - } - last_buf = buf; - } + drm_map_t *sarea_map; + dev->dev_private = (void *) dev_priv; + memset(dev_priv, 0, sizeof(drm_i810_private_t)); -cleanup: - if (last_buf) { - i810_dma_ready(dev); - drm_free_buffer(dev, last_buf); + if (init->ring_map_idx >= dev->map_count || + init->buffer_map_idx >= dev->map_count) { + i810_dma_cleanup(dev); + DRM_ERROR("ring_map or buffer_map are invalid\n"); + return -EINVAL; } - - if (must_free && !dev->context_flag) { - if (drm_lock_free(dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT)) { - DRM_ERROR("\n"); - } + + dev_priv->ring_map_idx = init->ring_map_idx; + dev_priv->buffer_map_idx = init->buffer_map_idx; + sarea_map = dev->maplist[0]; + dev_priv->sarea_priv = (drm_i810_sarea_t *) + ((u8 *)sarea_map->handle + + init->sarea_priv_offset); + + atomic_set(&dev_priv->flush_done, 0); + init_waitqueue_head(&dev_priv->flush_queue); + + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size); + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + + if (dev_priv->ring.virtual_start == NULL) { + i810_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" + " ring buffer\n"); + return -ENOMEM; } - clear_bit(0, &dev->interrupt_flag); - return retcode; + + /* Program Hardware Status Page */ + dev_priv->hw_status_page = i810_alloc_page(dev); + memset((void *) dev_priv->hw_status_page, 0, PAGE_SIZE); + if(dev_priv->hw_status_page == 0UL) { + i810_dma_cleanup(dev); + DRM_ERROR("Can not allocate hardware status page\n"); + return -ENOMEM; + } + DRM_DEBUG("hw status page @ %lx\n", dev_priv->hw_status_page); + + I810_WRITE(0x02080, virt_to_bus((void *)dev_priv->hw_status_page)); + DRM_DEBUG("Enabled hardware status page\n"); + + /* Now we need to init our freelist */ + if(i810_freelist_init(dev) != 0) { + i810_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" + " the freelist\n"); + return -ENOMEM; + } + return 0; } -static int i810_dma_send_buffers(drm_device_t *dev, drm_dma_t *d) +int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - DECLARE_WAITQUEUE(entry, current); - drm_buf_t *last_buf = NULL; - int retcode = 0; - drm_device_dma_t *dma = dev->dma; - - if (d->flags & _DRM_DMA_BLOCK) { - last_buf = dma->buflist[d->send_indices[d->send_count-1]]; - add_wait_queue(&last_buf->dma_wait, &entry); - } - - if ((retcode = drm_dma_enqueue(dev, d))) { - if (d->flags & _DRM_DMA_BLOCK) - remove_wait_queue(&last_buf->dma_wait, &entry); - return retcode; - } + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv; + drm_i810_init_t init; + int retcode = 0; - i810_dma_schedule(dev, 0); + copy_from_user_ret(&init, (drm_i810_init_t *)arg, + sizeof(init), -EFAULT); - if (d->flags & _DRM_DMA_BLOCK) { - DRM_DEBUG("%d waiting\n", current->pid); - current->state = TASK_INTERRUPTIBLE; - for (;;) { - if (!last_buf->waiting - && !last_buf->pending) - break; /* finished */ - schedule(); - if (signal_pending(current)) { - retcode = -EINTR; /* Can't restart */ - break; - } - } - current->state = TASK_RUNNING; - DRM_DEBUG("%d running\n", current->pid); - remove_wait_queue(&last_buf->dma_wait, &entry); - if (!retcode - || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) { - if (!waitqueue_active(&last_buf->dma_wait)) { - drm_free_buffer(dev, last_buf); - } - } - if (retcode) { - DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n", - d->context, - last_buf->waiting, - last_buf->pending, - DRM_WAITCOUNT(dev, d->context), - last_buf->idx, - last_buf->list, - last_buf->pid, - current->pid); - } + switch(init.func) { + case I810_INIT_DMA: + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if(dev_priv == NULL) return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + case I810_CLEANUP_DMA: + retcode = i810_dma_cleanup(dev); + break; + default: + retcode = -EINVAL; + break; } - return retcode; + + return retcode; } -int i810_dma(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) +static inline void i810_dma_dispatch_general(drm_device_t *dev, drm_buf_t *buf) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_device_dma_t *dma = dev->dma; - int retcode = 0; - drm_dma_t d; - - printk("i810_dma start\n"); - copy_from_user_ret(&d, (drm_dma_t *)arg, sizeof(d), -EFAULT); - DRM_DEBUG("%d %d: %d send, %d req\n", - current->pid, d.context, d.send_count, d.request_count); - - if (d.context == DRM_KERNEL_CONTEXT || d.context >= dev->queue_slots) { - DRM_ERROR("Process %d using context %d\n", - current->pid, d.context); - return -EINVAL; - } - - if (d.send_count < 0 || d.send_count > dma->buf_count) { - DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n", - current->pid, d.send_count, dma->buf_count); - return -EINVAL; - } - if (d.request_count < 0 || d.request_count > dma->buf_count) { - DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", - current->pid, d.request_count, dma->buf_count); - return -EINVAL; - } + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + unsigned long address = (unsigned long)buf->bus_address; + unsigned long start = address - dev->agp->base; + int length = buf->used; + RING_LOCALS; + + dev_priv->counter++; + DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG( "i810_dma_dispatch\n"); + DRM_DEBUG( "start : 0x%lx\n", start); + DRM_DEBUG( "length : 0x%x\n", length); + DRM_DEBUG( "start + length - 4 : 0x%lx\n", start + length - 4); + i810_kernel_lost_context(dev); + + BEGIN_LP_RING(10); + OUT_RING( CMD_OP_BATCH_BUFFER ); + OUT_RING( start | BB1_PROTECTED ); + OUT_RING( start + length - 4 ); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 20 ); + OUT_RING( dev_priv->counter ); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I810_BUF_FREE ); + OUT_RING( CMD_REPORT_HEAD ); + ADVANCE_LP_RING(); +} - if (d.send_count) { -#if 0 - if (d.flags & _DRM_DMA_PRIORITY) - retcode = i810_dma_priority(dev, &d); - else - retcode = i810_dma_send_buffers(dev, &d); -#endif - printk("i810_dma priority\n"); +static inline void i810_dma_dispatch_vertex(drm_device_t *dev, drm_buf_t *buf) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_buf_t *real_buf = dev->dma->buflist[ buf_priv->vertex_real_idx ]; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + xf86drmClipRectRec *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; + unsigned long address = (unsigned long)real_buf->bus_address; + unsigned long start = address - dev->agp->base; + int length = buf->used; + int i = 0; + RING_LOCALS; - retcode = i810_dma_priority(dev, &d); - } + + if(nbox > I810_NR_SAREA_CLIPRECTS) nbox = I810_NR_SAREA_CLIPRECTS; + + DRM_DEBUG("dispatch vertex addr 0x%lx, length 0x%x nbox %d\n", + address, length, buf_priv->nbox); + + dev_priv->counter++; + DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG( "i810_dma_dispatch\n"); + DRM_DEBUG( "start : %lx\n", start); + DRM_DEBUG( "length : %d\n", length); + DRM_DEBUG( "start + length - 4 : %ld\n", start + length - 4); + i810_kernel_lost_context(dev); + + if (!buf_priv->vertex_discard) { + do { + if (i < nbox) { + BEGIN_LP_RING(4); + OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | + SC_ENABLE ); + OUT_RING( GFX_OP_SCISSOR_INFO ); + OUT_RING( box[i].x1 | (box[i].y1 << 16) ); + OUT_RING( (box[i].x2-1) | ((box[i].y2-1) << 16) ); + ADVANCE_LP_RING(); + } + + BEGIN_LP_RING(4); + OUT_RING( CMD_OP_BATCH_BUFFER ); + OUT_RING( start | BB1_PROTECTED ); + OUT_RING( start + length - 4 ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); + + } while (++i < nbox); + } + + BEGIN_LP_RING(8); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( 20 ); + OUT_RING( dev_priv->counter ); + OUT_RING( CMD_STORE_DWORD_IDX ); + OUT_RING( buf_priv->my_use_idx ); + OUT_RING( I810_BUF_FREE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); +} - d.granted_count = 0; - if (!retcode && d.request_count) { - retcode = drm_dma_get_buffers(dev, &d); - } +/* Interrupts are only for flushing */ +static void i810_dma_service(int irq, void *device, struct pt_regs *regs) +{ + drm_device_t *dev = (drm_device_t *)device; + u16 temp; + + atomic_inc(&dev->total_irq); + temp = I810_READ16(I810REG_INT_IDENTITY_R); + temp = temp & ~(0x6000); + if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, + temp); /* Clear all interrupts */ + + queue_task(&dev->tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); +} - DRM_DEBUG("%d returning, granted = %d\n", - current->pid, d.granted_count); - copy_to_user_ret((drm_dma_t *)arg, &d, sizeof(d), -EFAULT); +static void i810_dma_task_queue(void *device) +{ + drm_device_t *dev = (drm_device_t *) device; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - printk("i810_dma end (granted)\n"); - return retcode; + atomic_set(&dev_priv->flush_done, 1); + wake_up_interruptible(&dev_priv->flush_queue); } int i810_irq_install(drm_device_t *dev, int irq) { int retcode; - + u16 temp; + if (!irq) return -EINVAL; down(&dev->struct_sem); @@ -591,6 +514,7 @@ int i810_irq_install(drm_device_t *dev, int irq) dev->irq = irq; up(&dev->struct_sem); + DRM_DEBUG( "Interrupt Install : %d\n", irq); DRM_DEBUG("%d\n", irq); dev->context_flag = 0; @@ -603,12 +527,21 @@ int i810_irq_install(drm_device_t *dev, int irq) dev->tq.next = NULL; dev->tq.sync = 0; - dev->tq.routine = i810_dma_schedule_tq_wrapper; + dev->tq.routine = i810_dma_task_queue; dev->tq.data = dev; - /* Before installing handler */ - /* TODO */ + temp = I810_READ16(I810REG_HWSTAM); + temp = temp & 0x6000; + I810_WRITE16(I810REG_HWSTAM, temp); + + temp = I810_READ16(I810REG_INT_MASK_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_MASK_R, temp); /* Unmask interrupts */ + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_ENABLE_R, temp); /* Disable all interrupts */ + /* Install handler */ if ((retcode = request_irq(dev->irq, i810_dma_service, @@ -620,15 +553,18 @@ int i810_irq_install(drm_device_t *dev, int irq) up(&dev->struct_sem); return retcode; } - - /* After installing handler */ - /* TODO */ + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + temp = temp | 0x0003; + I810_WRITE16(I810REG_INT_ENABLE_R, + temp); /* Enable bp & user interrupts */ return 0; } int i810_irq_uninstall(drm_device_t *dev) { int irq; + u16 temp; down(&dev->struct_sem); irq = dev->irq; @@ -636,16 +572,25 @@ int i810_irq_uninstall(drm_device_t *dev) up(&dev->struct_sem); if (!irq) return -EINVAL; - + + DRM_DEBUG( "Interrupt UnInstall: %d\n", irq); DRM_DEBUG("%d\n", irq); - - /* TODO : Disable interrupts */ + + temp = I810_READ16(I810REG_INT_IDENTITY_R); + temp = temp & ~(0x6000); + if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R, + temp); /* Clear all interrupts */ + + temp = I810_READ16(I810REG_INT_ENABLE_R); + temp = temp & 0x6000; + I810_WRITE16(I810REG_INT_ENABLE_R, + temp); /* Disable all interrupts */ + free_irq(irq, dev); return 0; } - int i810_control(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { @@ -654,8 +599,7 @@ int i810_control(struct inode *inode, struct file *filp, unsigned int cmd, drm_control_t ctl; int retcode; - printk(KERN_INFO "i810_control\n"); - i810_dma_init(dev); + DRM_DEBUG( "i810_control\n"); copy_from_user_ret(&ctl, (drm_control_t *)arg, sizeof(ctl), -EFAULT); @@ -674,20 +618,143 @@ int i810_control(struct inode *inode, struct file *filp, unsigned int cmd, return 0; } +static inline void i810_dma_emit_flush(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + i810_kernel_lost_context(dev); + BEGIN_LP_RING(2); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( GFX_OP_USER_INTERRUPT ); + ADVANCE_LP_RING(); +} + +static inline void i810_dma_quiescent_emit(drm_device_t *dev) +{ + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; + + i810_kernel_lost_context(dev); + BEGIN_LP_RING(4); + + OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); + OUT_RING( CMD_REPORT_HEAD ); + OUT_RING( GFX_OP_USER_INTERRUPT ); + OUT_RING( 0 ); + ADVANCE_LP_RING(); +} + +static void i810_dma_quiescent(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + int startTime = 0; + int curTime = 0; + int timeout_millis = 3000; + + + if(dev_priv == NULL) { + return; + } + atomic_set(&dev_priv->flush_done, 0); + current->state = TASK_INTERRUPTIBLE; + add_wait_queue(&dev_priv->flush_queue, &entry); + for (;;) { + i810_dma_quiescent_emit(dev); + if (atomic_read(&dev_priv->flush_done) == 1) break; + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("lockup\n"); + break; + } + schedule_timeout(HZ*3); + if (signal_pending(current)) { + break; + } + } + + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + + return; +} + +static int i810_flush_queue(drm_device_t *dev) +{ + DECLARE_WAITQUEUE(entry, current); + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + int ret = 0; + int startTime = 0; + int curTime = 0; + int timeout_millis = 3000; + + + if(dev_priv == NULL) { + return 0; + } + atomic_set(&dev_priv->flush_done, 0); + current->state = TASK_INTERRUPTIBLE; + add_wait_queue(&dev_priv->flush_queue, &entry); + for (;;) { + i810_dma_emit_flush(dev); + if (atomic_read(&dev_priv->flush_done) == 1) break; + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("lockup\n"); + break; + } + schedule_timeout(HZ*3); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + break; + } + } + + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + + return ret; +} + +/* Must be called with the lock held */ +void i810_reclaim_buffers(drm_device_t *dev, pid_t pid) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if(dev->dev_private == NULL) return; + + i810_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + + if (buf->pid == pid) { + /* Only buffers that need to get reclaimed ever + * get set to free */ + if(buf_priv == NULL) return; + cmpxchg(buf_priv->in_use, + I810_BUF_USED, I810_BUF_FREE); + } + } +} + int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); int ret = 0; drm_lock_t lock; - drm_queue_t *q; -#if DRM_DMA_HISTOGRAM - cycles_t start; - - dev->lck_start = start = get_cycles(); -#endif copy_from_user_ret(&lock, (drm_lock_t *)arg, sizeof(lock), -EFAULT); @@ -696,16 +763,20 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, current->pid, lock.context); return -EINVAL; } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); - if (lock.context < 0 || lock.context >= dev->queue_count) { + if (lock.context < 0) { return -EINVAL; } - q = dev->queuelist[lock.context]; - - ret = drm_flush_block_and_flush(dev, lock.context, lock.flags); + /* Only one queue: + */ if (!ret) { - if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) +#if 0 + if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) != lock.context) { long j = jiffies - dev->lock.lock_time; @@ -716,6 +787,7 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, schedule_timeout(j); } } +#endif add_wait_queue(&dev->lock.lock_queue, &entry); for (;;) { if (!dev->lock.hw_lock) { @@ -728,13 +800,13 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, dev->lock.pid = current->pid; dev->lock.lock_time = jiffies; atomic_inc(&dev->total_locks); - atomic_inc(&q->total_locks); break; /* Got lock */ } /* Contention */ atomic_inc(&dev->total_sleeps); current->state = TASK_INTERRUPTIBLE; + DRM_DEBUG("Calling lock schedule\n"); schedule(); if (signal_pending(current)) { ret = -ERESTARTSYS; @@ -744,19 +816,183 @@ int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, current->state = TASK_RUNNING; remove_wait_queue(&dev->lock.lock_queue, &entry); } - - drm_flush_unblock(dev, lock.context, lock.flags); /* cleanup phase */ if (!ret) { - if (lock.flags & _DRM_LOCK_READY) - i810_dma_ready(dev); - if (lock.flags & _DRM_LOCK_QUIESCENT) - i810_dma_quiescent(dev); + if (lock.flags & _DRM_LOCK_QUIESCENT) { + DRM_DEBUG("_DRM_LOCK_QUIESCENT\n"); + DRM_DEBUG("fred\n"); + i810_dma_quiescent(dev); + } } + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + return ret; +} -#if DRM_DMA_HISTOGRAM - atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); -#endif +int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + + DRM_DEBUG("i810_flush_ioctl\n"); + i810_flush_queue(dev); + return 0; +} + +static int i810DmaGeneral(drm_device_t *dev, drm_i810_general_t *args) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf = dma->buflist[ args->idx ]; + + buf->used = args->used; + + DRM_DEBUG("i810DmaGeneral idx %d used %d\n", args->idx, buf->used); + + if (!buf->used) { + DRM_ERROR("0 length buffer\n"); + i810_freelist_put(dev, buf); + return 0; + } + + i810_dma_dispatch_general( dev, buf ); + atomic_add(buf->used, &dma->total_bytes); + atomic_inc(&dma->total_dmas); + + return 0; +} + +static int i810DmaVertex(drm_device_t *dev, drm_i810_vertex_t *args) +{ + drm_device_dma_t *dma = dev->dma; + drm_i810_buf_priv_t *buf_priv; + drm_buf_t *buf; + + + buf = dma->buflist[ args->idx ]; + buf->used = args->real_used; + + DRM_DEBUG("i810DmaVertex idx %d used %d\n", args->idx, buf->used); + + buf_priv = buf->dev_private; + buf_priv->vertex_real_idx = args->real_idx; + buf_priv->vertex_discard = args->discard; + + i810_dma_dispatch_vertex( dev, buf); + atomic_add(buf->used, &dma->total_bytes); + atomic_inc(&dma->total_dmas); + return 0; +} + +int i810_dma_general(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_general_t general; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + int retcode = 0; - return ret; + copy_from_user_ret(&general, (drm_i810_general_t *)arg, sizeof(general), + -EFAULT); + + DRM_DEBUG("i810 dma general idx %d used %d\n", + general.idx, general.used); + + retcode = i810DmaGeneral(dev, &general); + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; +} + +int i810_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + drm_i810_vertex_t vertex; + int retcode = 0; + + copy_from_user_ret(&vertex, (drm_i810_vertex_t *)arg, sizeof(vertex), + -EFAULT); + + DRM_DEBUG("i810 dma vertex, idx %d used %d real_idx %d discard %d\n", + vertex.idx, vertex.real_used, vertex.real_idx, + vertex.discard); + + retcode = i810DmaVertex(dev, &vertex); + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; + +} + +int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int) hw_status[5]; + return 0; +} + +int i810_dma(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + int retcode = 0; + drm_dma_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + u32 *hw_status = (u32 *)dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + + copy_from_user_ret(&d, (drm_dma_t *)arg, sizeof(d), -EFAULT); + DRM_DEBUG("%d %d: %d send, %d req\n", + current->pid, d.context, d.send_count, d.request_count); + + /* Please don't send us buffers. + */ + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + current->pid, d.send_count); + return -EINVAL; + } + + /* We'll send you buffers. + */ + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count); + return -EINVAL; + } + + d.granted_count = 0; + + if (!retcode && d.request_count) { + retcode = i810_dma_get_buffers(dev, &d); + } + + DRM_DEBUG("i810_dma: %d returning, granted = %d\n", + current->pid, d.granted_count); + + copy_to_user_ret((drm_dma_t *)arg, &d, sizeof(d), -EFAULT); + sarea_priv->last_dispatch = (int) hw_status[5]; + + return retcode; } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.h new file mode 100644 index 000000000..0f79b6ab4 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_dma.h @@ -0,0 +1,118 @@ +/* i810_dma.h -- DMA support for the i810 -*- linux-c -*- + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Keith Whitwell <keithw@precisioninsight.com> + * + * $XFree86$ + * + */ + + +#ifndef I810_DMA_H +#define I810_DMA_H + +#include "i810_drm_public.h" + + +/* Copy the outstanding cliprects for every I810_DMA_VERTEX buffer. + * This can be fixed by emitting directly to the ringbuffer in the + * 'vertex_dma' ioctl. +*/ +typedef struct { + int vertex_real_idx; + int vertex_discard; + u32 *in_use; + int my_use_idx; + unsigned int nbox; + xf86drmClipRectRec boxes[I810_NR_SAREA_CLIPRECTS]; +} drm_i810_buf_priv_t; + + +#define I810_DMA_GENERAL 0 +#define I810_DMA_VERTEX 1 +#define I810_DMA_DISCARD 2 /* not used */ + +#define I810_VERBOSE 0 + + +int i810_dma_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +int i810_dma_general(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + +#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) +#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) +#define CMD_REPORT_HEAD (7<<23) +#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) +#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) + +#define INST_PARSER_CLIENT 0x00000000 +#define INST_OP_FLUSH 0x02000000 +#define INST_FLUSH_MAP_CACHE 0x00000001 + + +#define BB1_START_ADDR_MASK (~0x7) +#define BB1_PROTECTED (1<<0) +#define BB1_UNPROTECTED (0<<0) +#define BB2_END_ADDR_MASK (~0x7) + +#define I810REG_HWSTAM 0x02098 +#define I810REG_INT_IDENTITY_R 0x020a4 +#define I810REG_INT_MASK_R 0x020a8 +#define I810REG_INT_ENABLE_R 0x020a0 + +#define LP_RING 0x2030 +#define HP_RING 0x2040 +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x000FFFF8 +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_START 0x08 +#define START_ADDR 0x00FFFFF8 +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x000FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) + +#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) + +#endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drm_public.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drm_public.h new file mode 100644 index 000000000..7213def17 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drm_public.h @@ -0,0 +1,139 @@ +/* i810_drm_public.h -- Public header for the i810 driver -*- linux-c -*- + * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Jeff Hartmann <jhartmann@precisioninsight.com> + * Keith Whitwell <keithw@precisioninsight.com> + * + * $XFree86$ + */ + +#ifndef _I810_DRM_H_ +#define _I810_DRM_H_ + +typedef struct drm_i810_init { + enum { + I810_INIT_DMA = 0x01, + I810_CLEANUP_DMA = 0x02 + } func; + int ring_map_idx; + int buffer_map_idx; + int sarea_priv_offset; + unsigned long ring_start; + unsigned long ring_end; + unsigned long ring_size; + +} drm_i810_init_t; + +typedef struct _xf86drmClipRectRec { + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; +} xf86drmClipRectRec; + +/* Might one day want to support the client-side ringbuffer code again. + */ + +#define I810_USE_BATCH 1 + +#define I810_DMA_BUF_ORDER 12 +#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) +#define I810_DMA_BUF_NR 256 + +#define I810_NR_SAREA_CLIPRECTS 2 + +/* Each region is a minimum of 64k, and there are at most 64 of them. + */ +#define I810_NR_TEX_REGIONS 64 +#define I810_LOG_MIN_TEX_REGION_SIZE 16 + +typedef struct { + unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char in_use; /* owned by a client, or free? */ + int age; /* tracked by clients to update local LRU's */ +} i810TexRegion; + +typedef struct { + unsigned int nbox; + xf86drmClipRectRec boxes[I810_NR_SAREA_CLIPRECTS]; + + /* Maintain an LRU of contiguous regions of texture space. If + * you think you own a region of texture memory, and it has an + * age different to the one you set, then you are mistaken and + * it has been stolen by another client. If global texAge + * hasn't changed, there is no need to walk the list. + * + * These regions can be used as a proxy for the fine-grained + * texture information of other clients - by maintaining them + * in the same lru which is used to age their own textures, + * clients have an approximate lru for the whole of global + * texture space, and can make informed decisions as to which + * areas to kick out. There is no need to choose whether to + * kick out your own texture or someone else's - simply eject + * them all in LRU order. + */ + i810TexRegion texList[I810_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ + + int texAge; /* last time texture was uploaded */ + + int last_enqueue; /* last time a buffer was enqueued */ + int last_dispatch; /* age of the most recently dispatched buffer */ + int last_quiescent; /* */ + + int ctxOwner; /* last context to upload state */ +} drm_i810_sarea_t; + + +typedef struct { + int idx; + int used; + int age; +} drm_i810_general_t; + + +/* These may be placeholders if we have more cliprects than + * I810_NR_SAREA_CLIPRECTS. In that case, idx != real_idx; idx is the + * number of a placeholder buffer, real_idx is the real buffer to be + * rendered multiple times. + * + * This is a hack to work around the fact that the drm considers + * buffers to be only in a single state (ie on a single queue). + */ +typedef struct { + int idx; /* buffer to queue and free on completion */ + int real_idx; /* buffer to execute */ + int real_used; /* buf->used in for real buffer */ + int discard; /* don't execute the commands */ + int age; +} drm_i810_vertex_t; + + + +#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) +#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) +#define DRM_IOCTL_I810_DMA DRM_IOW( 0x42, drm_i810_general_t) +#define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43) +#define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44) +#endif /* _I810_DRM_H_ */ diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.c index f33153a36..179b8714f 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.c @@ -33,11 +33,14 @@ #define EXPORT_SYMTAB #include "drmP.h" #include "i810_drv.h" +#include "i810_dma.h" + + EXPORT_SYMBOL(i810_init); EXPORT_SYMBOL(i810_cleanup); #define I810_NAME "i810" -#define I810_DESC "Matrox g200/g400" +#define I810_DESC "Intel I810" #define I810_DATE "19991213" #define I810_MAJOR 0 #define I810_MINOR 0 @@ -54,6 +57,7 @@ static struct file_operations i810_fops = { mmap: drm_mmap, read: drm_read, fasync: drm_fasync, + poll: drm_poll, }; static struct miscdevice i810_misc = { @@ -80,13 +84,13 @@ static drm_ioctl_desc_t i810_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { i810_mapbufs, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { i810_freebufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { i810_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { i810_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { i810_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { i810_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { i810_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { i810_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { i810_resctx, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, @@ -104,6 +108,11 @@ static drm_ioctl_desc_t i810_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)] = { i810_dma_init, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_DMA)] = { i810_dma_general,1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)] = { i810_flush_ioctl,1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage, 1, 0 }, }; #define I810_IOCTL_COUNT DRM_ARRAY_SIZE(i810_ioctls) @@ -121,7 +130,7 @@ MODULE_PARM(i810, "s"); int init_module(void) { - printk("doing i810_init()\n"); + DRM_DEBUG("doing i810_init()\n"); return i810_init(); } @@ -364,7 +373,7 @@ int i810_init(void) #ifdef MODULE drm_parse_options(i810); #endif - printk("doing misc_register\n"); + DRM_DEBUG("doing misc_register\n"); if ((retcode = misc_register(&i810_misc))) { DRM_ERROR("Cannot register \"%s\"\n", I810_NAME); return retcode; @@ -372,13 +381,22 @@ int i810_init(void) dev->device = MKDEV(MISC_MAJOR, i810_misc.minor); dev->name = I810_NAME; - printk("doing mem init\n"); + DRM_DEBUG("doing mem init\n"); drm_mem_init(); - printk("doing proc init\n"); + DRM_DEBUG("doing proc init\n"); drm_proc_init(dev); - printk("doing agp init\n"); + DRM_DEBUG("doing agp init\n"); dev->agp = drm_agp_init(); - printk("doing ctxbitmap init\n"); + if(dev->agp == NULL) { + DRM_INFO("The i810 drm module requires the agpgart module" + " to function correctly\nPlease load the agpgart" + " module before you load the i810 module\n"); + drm_proc_cleanup(); + misc_deregister(&i810_misc); + i810_takedown(dev); + return -ENOMEM; + } + DRM_DEBUG("doing ctxbitmap init\n"); if((retcode = drm_ctxbitmap_init(dev))) { DRM_ERROR("Cannot allocate memory for context bitmap.\n"); drm_proc_cleanup(); @@ -386,10 +404,6 @@ int i810_init(void) i810_takedown(dev); return retcode; } -#if 0 - printk("doing i810_dma_init\n"); - i810_dma_init(dev); -#endif DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", I810_NAME, @@ -417,7 +431,6 @@ void i810_cleanup(void) DRM_INFO("Module unloaded\n"); } drm_ctxbitmap_cleanup(dev); - i810_dma_cleanup(dev); i810_takedown(dev); if (dev->agp) { drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); @@ -484,24 +497,82 @@ int i810_release(struct inode *inode, struct file *filp) drm_device_t *dev = priv->dev; int retcode = 0; - DRM_DEBUG("open_count = %d\n", dev->open_count); - if (!(retcode = drm_release(inode, filp))) { - MOD_DEC_USE_COUNT; - atomic_inc(&dev->total_close); - spin_lock(&dev->count_lock); - if (!--dev->open_count) { - if (atomic_read(&dev->ioctl_count) || dev->blocked) { - DRM_ERROR("Device busy: %d %d\n", - atomic_read(&dev->ioctl_count), - dev->blocked); - spin_unlock(&dev->count_lock); - return -EBUSY; + DRM_DEBUG("pid = %d, device = 0x%x, open_count = %d\n", + current->pid, dev->device, dev->open_count); + + if (_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) + && dev->lock.pid == current->pid) { + i810_reclaim_buffers(dev, priv->pid); + DRM_ERROR("Process %d dead, freeing lock for context %d\n", + current->pid, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + drm_lock_free(dev, + &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } else { + /* The lock is required to reclaim buffers */ + DECLARE_WAITQUEUE(entry, current); + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + retcode = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + dev->lock.pid = priv->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + /* Contention */ + atomic_inc(&dev->total_sleeps); + current->state = TASK_INTERRUPTIBLE; + schedule(); + if (signal_pending(current)) { + retcode = -ERESTARTSYS; + break; } - spin_unlock(&dev->count_lock); - return i810_takedown(dev); } - spin_unlock(&dev->count_lock); + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + if(!retcode) { + i810_reclaim_buffers(dev, priv->pid); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); + } + } + drm_fasync(-1, filp, 0); + + down(&dev->struct_sem); + if (priv->prev) priv->prev->next = priv->next; + else dev->file_first = priv->next; + if (priv->next) priv->next->prev = priv->prev; + else dev->file_last = priv->prev; + up(&dev->struct_sem); + + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); + MOD_DEC_USE_COUNT; + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + return i810_takedown(dev); } + spin_unlock(&dev->count_lock); return retcode; } @@ -566,8 +637,7 @@ int i810_unlock(struct inode *inode, struct file *filp, unsigned int cmd, atomic_inc(&dev->total_unlocks); if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) atomic_inc(&dev->total_contends); - drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); - i810_dma_schedule(dev, 1); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); if (!dev->context_flag) { if (drm_lock_free(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) { diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.h index 0f5f42bb6..d3dc69062 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/i810_drv.h @@ -31,6 +31,32 @@ #ifndef _I810_DRV_H_ #define _I810_DRV_H_ +#include "i810_drm_public.h" + +typedef struct _drm_i810_ring_buffer{ + int tail_mask; + unsigned long Start; + unsigned long End; + unsigned long Size; + u8 *virtual_start; + int head; + int tail; + int space; +} drm_i810_ring_buffer_t; + +typedef struct drm_i810_private { + int ring_map_idx; + int buffer_map_idx; + + drm_i810_ring_buffer_t ring; + drm_i810_sarea_t *sarea_priv; + + unsigned long hw_status_page; + unsigned long counter; + + atomic_t flush_done; + wait_queue_head_t flush_queue; /* Processes waiting until flush */ +} drm_i810_private_t; /* i810_drv.c */ extern int i810_init(void); @@ -54,8 +80,13 @@ extern int i810_control(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int i810_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern void i810_dma_init(drm_device_t *dev); -extern void i810_dma_cleanup(drm_device_t *dev); +extern int i810_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern void i810_reclaim_buffers(drm_device_t *dev, pid_t pid); +extern int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg); /* i810_bufs.c */ @@ -72,5 +103,25 @@ extern int i810_mapbufs(struct inode *inode, struct file *filp, extern int i810_addmap(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); + /* i810_context.c */ +extern int i810_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i810_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int i810_context_switch(drm_device_t *dev, int old, int new); +extern int i810_context_switch_complete(drm_device_t *dev, int new); + + #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/memory.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/memory.c index a8a81abd8..559ac7391 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/memory.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/memory.c @@ -44,21 +44,25 @@ static spinlock_t drm_mem_lock = SPIN_LOCK_UNLOCKED; static unsigned long drm_ram_available = 0; /* In pages */ static unsigned long drm_ram_used = 0; static drm_mem_stats_t drm_mem_stats[] = { - [DRM_MEM_DMA] = { "dmabufs" }, - [DRM_MEM_SAREA] = { "sareas" }, - [DRM_MEM_DRIVER] = { "driver" }, - [DRM_MEM_MAGIC] = { "magic" }, - [DRM_MEM_IOCTLS] = { "ioctltab" }, - [DRM_MEM_MAPS] = { "maplist" }, - [DRM_MEM_VMAS] = { "vmalist" }, - [DRM_MEM_BUFS] = { "buflist" }, - [DRM_MEM_SEGS] = { "seglist" }, - [DRM_MEM_PAGES] = { "pagelist" }, - [DRM_MEM_FILES] = { "files" }, - [DRM_MEM_QUEUES] = { "queues" }, - [DRM_MEM_CMDS] = { "commands" }, - [DRM_MEM_MAPPINGS] = { "mappings" }, - [DRM_MEM_BUFLISTS] = { "buflists" }, + [DRM_MEM_DMA] = { "dmabufs" }, + [DRM_MEM_SAREA] = { "sareas" }, + [DRM_MEM_DRIVER] = { "driver" }, + [DRM_MEM_MAGIC] = { "magic" }, + [DRM_MEM_IOCTLS] = { "ioctltab" }, + [DRM_MEM_MAPS] = { "maplist" }, + [DRM_MEM_VMAS] = { "vmalist" }, + [DRM_MEM_BUFS] = { "buflist" }, + [DRM_MEM_SEGS] = { "seglist" }, + [DRM_MEM_PAGES] = { "pagelist" }, + [DRM_MEM_FILES] = { "files" }, + [DRM_MEM_QUEUES] = { "queues" }, + [DRM_MEM_CMDS] = { "commands" }, + [DRM_MEM_MAPPINGS] = { "mappings" }, + [DRM_MEM_BUFLISTS] = { "buflists" }, + [DRM_MEM_AGPLISTS] = { "agplist" }, + [DRM_MEM_TOTALAGP] = { "totalagp" }, + [DRM_MEM_BOUNDAGP] = { "boundagp" }, + [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, { NULL, 0, } /* Last entry must be null */ }; @@ -324,3 +328,120 @@ void drm_ioremapfree(void *pt, unsigned long size) free_count, alloc_count); } } + +#ifdef DRM_AGP +agp_memory *drm_alloc_agp(int pages, u32 type) +{ + agp_memory *handle; + + if (!pages) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n"); + return NULL; + } + + if (drm_agp.allocate_memory) { + if ((handle = (*drm_agp.allocate_memory)(pages, + type))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; + drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated + += pages << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + return handle; + } + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count; + spin_unlock(&drm_mem_lock); + return NULL; +} + +int drm_free_agp(agp_memory *handle, int pages) +{ + int alloc_count; + int free_count; + int retval = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Attempt to free NULL AGP handle\n"); + return retval;; + } + + if (drm_agp.free_memory) { + (*drm_agp.free_memory)(handle); + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count; + alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count; + drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed + += pages << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_TOTALAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + return 0; + } + return retval; +} + +int drm_bind_agp(agp_memory *handle, unsigned int start) +{ + int retcode = -EINVAL; + + DRM_DEBUG("drm_bind_agp called\n"); + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to bind NULL AGP handle\n"); + return retcode; + } + + DRM_DEBUG("drm_agp.bind_memory : %p\n", drm_agp.bind_memory); + if (drm_agp.bind_memory) { + if (!(retcode = (*drm_agp.bind_memory)(handle, start))) { + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; + drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated + += handle->page_count << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + DRM_DEBUG("drm_agp.bind_memory: retcode %d\n", retcode); + return retcode; + } + } + spin_lock(&drm_mem_lock); + ++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count; + spin_unlock(&drm_mem_lock); + return retcode; +} + +int drm_unbind_agp(agp_memory *handle) +{ + int alloc_count; + int free_count; + int retcode = -EINVAL; + + if (!handle) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Attempt to unbind NULL AGP handle\n"); + return retcode; + } + + if (drm_agp.unbind_memory) { + int c = handle->page_count; + if ((retcode = (*drm_agp.unbind_memory)(handle))) + return retcode; + spin_lock(&drm_mem_lock); + free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count; + alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count; + drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed += c << PAGE_SHIFT; + spin_unlock(&drm_mem_lock); + if (free_count > alloc_count) { + DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, + "Excess frees: %d frees, %d allocs\n", + free_count, alloc_count); + } + } + return retcode; +} +#endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_bufs.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_bufs.c index 34f1112a6..89e4090d7 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_bufs.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_bufs.c @@ -76,7 +76,7 @@ int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("count: %d\n", count); DRM_DEBUG("order: %d\n", order); DRM_DEBUG("size: %d\n", size); - DRM_DEBUG("agp_offset: %d\n", agp_offset); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); DRM_DEBUG("alignment: %d\n", alignment); DRM_DEBUG("page_order: %d\n", page_order); DRM_DEBUG("total: %d\n", total); @@ -121,7 +121,7 @@ int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, buf->order = order; buf->used = 0; - DRM_DEBUG("offset : %d\n", offset); + DRM_DEBUG("offset : %ld\n", offset); buf->offset = offset; /* Hrm */ buf->bus_address = dev->agp->base + agp_offset + offset; @@ -185,7 +185,7 @@ int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("count: %d\n", count); DRM_DEBUG("order: %d\n", order); DRM_DEBUG("size: %d\n", size); - DRM_DEBUG("agp_offset: %d\n", agp_offset); + DRM_DEBUG("agp_offset: %ld\n", agp_offset); DRM_DEBUG("alignment: %d\n", alignment); DRM_DEBUG("page_order: %d\n", page_order); DRM_DEBUG("total: %d\n", total); @@ -193,7 +193,7 @@ int mga_addbufs_agp(struct inode *inode, struct file *filp, unsigned int cmd, dma->flags = _DRM_DMA_USE_AGP; - DRM_DEBUG("dma->flags : %lx\n", dma->flags); + DRM_DEBUG("dma->flags : %x\n", dma->flags); return 0; } @@ -546,7 +546,7 @@ int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, spin_lock(&dev->count_lock); if (atomic_read(&dev->buf_alloc)) { spin_unlock(&dev->count_lock); - DRM_DEBUG("Buzy\n"); + DRM_DEBUG("Busy\n"); return -EBUSY; } ++dev->buf_use; /* Can't allocate more after this call */ @@ -558,7 +558,7 @@ int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, -EFAULT); DRM_DEBUG("mga_mapbufs\n"); - DRM_DEBUG("dma->flags : %lx\n", dma->flags); + DRM_DEBUG("dma->flags : %x\n", dma->flags); if (request.count >= dma->buf_count) { if(dma->flags & _DRM_DMA_USE_AGP) { @@ -576,14 +576,17 @@ int mga_mapbufs(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("map->size : %lx\n", map->size); DRM_DEBUG("map->type : %d\n", map->type); DRM_DEBUG("map->flags : %x\n", map->flags); - DRM_DEBUG("map->handle : %lx\n", map->handle); + DRM_DEBUG("map->handle : %p\n", map->handle); DRM_DEBUG("map->mtrr : %d\n", map->mtrr); - + down(¤t->mm->mmap_sem); virtual = do_mmap(filp, 0, map->size, PROT_READ|PROT_WRITE, MAP_SHARED, (unsigned long)map->offset); + up(¤t->mm->mmap_sem); } else { - virtual = do_mmap(filp, 0, dma->byte_count, - PROT_READ|PROT_WRITE, MAP_SHARED, 0); + down(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ|PROT_WRITE, MAP_SHARED, 0); + up(¤t->mm->mmap_sem); } if (virtual > -1024UL) { /* Real error */ diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_context.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_context.c index fb0d336fa..2459b35bb 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_context.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_context.c @@ -38,7 +38,7 @@ static int mga_alloc_queue(drm_device_t *dev) { int temp = drm_ctxbitmap_next(dev); - printk("mga_alloc_queue: %d\n", temp); + DRM_DEBUG("mga_alloc_queue: %d\n", temp); return temp; } @@ -57,7 +57,7 @@ int mga_context_switch(drm_device_t *dev, int old, int new) dev->ctx_start = get_cycles(); #endif - printk("Context switch from %d to %d\n", old, new); + DRM_DEBUG("Context switch from %d to %d\n", old, new); if (new == dev->last_context) { clear_bit(0, &dev->context_flag); @@ -104,7 +104,7 @@ int mga_resctx(struct inode *inode, struct file *filp, unsigned int cmd, drm_ctx_t ctx; int i; - printk("%d\n", DRM_RESERVED_CONTEXTS); + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); copy_from_user_ret(&res, (drm_ctx_res_t *)arg, sizeof(res), -EFAULT); if (res.count >= DRM_RESERVED_CONTEXTS) { memset(&ctx, 0, sizeof(ctx)); @@ -134,11 +134,11 @@ int mga_addctx(struct inode *inode, struct file *filp, unsigned int cmd, ctx.handle = mga_alloc_queue(dev); } if (ctx.handle == -1) { - printk("Not enough free contexts.\n"); + DRM_DEBUG("Not enough free contexts.\n"); /* Should this return -EBUSY instead? */ return -ENOMEM; } - printk("%d\n", ctx.handle); + DRM_DEBUG("%d\n", ctx.handle); copy_to_user_ret((drm_ctx_t *)arg, &ctx, sizeof(ctx), -EFAULT); return 0; } @@ -170,7 +170,7 @@ int mga_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, drm_ctx_t ctx; copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); - printk("%d\n", ctx.handle); + DRM_DEBUG("%d\n", ctx.handle); return mga_context_switch(dev, dev->last_context, ctx.handle); } @@ -182,7 +182,7 @@ int mga_newctx(struct inode *inode, struct file *filp, unsigned int cmd, drm_ctx_t ctx; copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); - printk("%d\n", ctx.handle); + DRM_DEBUG("%d\n", ctx.handle); mga_context_switch_complete(dev, ctx.handle); return 0; @@ -194,51 +194,11 @@ int mga_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->dev; drm_ctx_t ctx; - drm_queue_t *q; - drm_buf_t *buf; copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); - printk("%d\n", ctx.handle); - if(ctx.handle == DRM_KERNEL_CONTEXT) { - q = dev->queuelist[ctx.handle]; - atomic_inc(&q->use_count); - if (atomic_read(&q->use_count) == 1) { - /* No longer in use */ - atomic_dec(&q->use_count); - return -EINVAL; - } - atomic_inc(&q->finalization); /* Mark queue in finalization state */ - atomic_sub(2, &q->use_count); - /* Mark queue as unused (pending finalization) */ - - while (test_and_set_bit(0, &dev->interrupt_flag)) { - printk("Calling schedule from rmctx\n"); - schedule(); - if (signal_pending(current)) { - clear_bit(0, &dev->interrupt_flag); - return -EINTR; - } - } - - /* Remove queued buffers */ - while ((buf = drm_waitlist_get(&q->waitlist))) { - drm_free_buffer(dev, buf); - } - clear_bit(0, &dev->interrupt_flag); - - /* Wakeup blocked processes */ - wake_up_interruptible(&q->read_queue); - wake_up_interruptible(&q->write_queue); - wake_up_interruptible(&q->flush_queue); - - /* Finalization over. Queue is made - available when both use_count and - finalization become 0, which won't - happen until all the waiting processes - stop waiting. */ - atomic_dec(&q->finalization); - } else { - drm_ctxbitmap_free(dev, ctx.handle); + DRM_DEBUG("%d\n", ctx.handle); + if(ctx.handle != DRM_KERNEL_CONTEXT) { + drm_ctxbitmap_free(dev, ctx.handle); } return 0; diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.c index 2e24e5b48..70cd98b16 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.c @@ -24,7 +24,8 @@ * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith <faith@precisioninsight.com> - * Jeff Hartmann <jhartmann@precisioninsight.com> + * Jeff Hartmann <jhartmann@precisioninsight.com> + * Keith Whitwell <keithw@precisioninsight.com> * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.c,v 1.1 2000/02/11 17:26:07 dawes Exp $ * @@ -35,7 +36,6 @@ #include "mga_drv.h" #include "mgareg_flags.h" #include "mga_dma.h" -#include "mga_state.h" #include <linux/interrupt.h> /* For task queue support */ @@ -48,643 +48,614 @@ #define MGA_WRITE(reg,val) do { MGA_DEREF(reg) = val; } while (0) #define PDEA_pagpxfer_enable 0x2 -#define MGA_SYNC_TAG 0x423f4200 -typedef enum { - TT_GENERAL, - TT_BLIT, - TT_VECTOR, - TT_VERTEX -} transferType_t; +static int mga_flush_queue(drm_device_t *dev); +static unsigned long mga_alloc_page(drm_device_t *dev) +{ + unsigned long address; + + address = __get_free_page(GFP_KERNEL); + if(address == 0UL) { + return 0; + } + atomic_inc(&mem_map[MAP_NR((void *) address)].count); + set_bit(PG_locked, &mem_map[MAP_NR((void *) address)].flags); + + return address; +} + +static void mga_free_page(drm_device_t *dev, unsigned long page) +{ + if(page == 0UL) { + return; + } + atomic_dec(&mem_map[MAP_NR((void *) page)].count); + clear_bit(PG_locked, &mem_map[MAP_NR((void *) page)].flags); + wake_up(&mem_map[MAP_NR((void *) page)].wait); + free_page(page); + return; +} static void mga_delay(void) { return; } -int mga_dma_cleanup(drm_device_t *dev) +static void mga_flush_write_combine(void) { - if(dev->dev_private) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *) dev->dev_private; - - if(dev_priv->ioremap) { - int temp = (dev_priv->warp_ucode_size + - dev_priv->primary_size + - PAGE_SIZE - 1) / PAGE_SIZE * PAGE_SIZE; - - drm_ioremapfree((void *) dev_priv->ioremap, temp); - } - - drm_free(dev->dev_private, sizeof(drm_mga_private_t), - DRM_MEM_DRIVER); - dev->dev_private = NULL; - } - - return 0; + int xchangeDummy; + __asm__ volatile(" push %%eax ; xchg %%eax, %0 ; pop %%eax" : : "m" (xchangeDummy)); + __asm__ volatile(" push %%eax ; push %%ebx ; push %%ecx ; push %%edx ;" + " movl $0,%%eax ; cpuid ; pop %%edx ; pop %%ecx ; pop %%ebx ;" + " pop %%eax" : /* no outputs */ : /* no inputs */ ); } +/* These are two age tags that will never be sent to + * the hardware */ +#define MGA_BUF_USED 0xffffffff +#define MGA_BUF_FREE 0 -static int mga_alloc_kernel_queue(drm_device_t *dev) +static void mga_freelist_debug(drm_mga_freelist_t *item) { - drm_queue_t *queue = NULL; - /* Allocate a new queue */ - down(&dev->struct_sem); - - if(dev->queue_count != 0) { - /* Reseting the kernel context here is not - * a race, since it can only happen when that - * queue is empty. - */ - queue = dev->queuelist[DRM_KERNEL_CONTEXT]; - printk("Kernel queue already allocated\n"); + if(item->buf != NULL) { + DRM_DEBUG("buf index : %d\n", item->buf->idx); } else { - queue = drm_alloc(sizeof(*queue), DRM_MEM_QUEUES); - if(!queue) { - up(&dev->struct_sem); - printk("out of memory\n"); - return -ENOMEM; - } - ++dev->queue_count; - dev->queuelist = drm_alloc(sizeof(*dev->queuelist), - DRM_MEM_QUEUES); - if(!dev->queuelist) { - up(&dev->struct_sem); - drm_free(queue, sizeof(*queue), DRM_MEM_QUEUES); - printk("out of memory\n"); - return -ENOMEM; - } + DRM_DEBUG("Freelist head\n"); } - - memset(queue, 0, sizeof(*queue)); - atomic_set(&queue->use_count, 1); - atomic_set(&queue->finalization, 0); - atomic_set(&queue->block_count, 0); - atomic_set(&queue->block_read, 0); - atomic_set(&queue->block_write, 0); - atomic_set(&queue->total_queued, 0); - atomic_set(&queue->total_flushed, 0); - atomic_set(&queue->total_locks, 0); - - init_waitqueue_head(&queue->write_queue); - init_waitqueue_head(&queue->read_queue); - init_waitqueue_head(&queue->flush_queue); - - queue->flags = 0; - - drm_waitlist_create(&queue->waitlist, dev->dma->buf_count); - - dev->queue_slots = 1; - dev->queuelist[DRM_KERNEL_CONTEXT] = queue; - dev->queue_count--; - - up(&dev->struct_sem); - printk("%d (new)\n", dev->queue_count - 1); - return DRM_KERNEL_CONTEXT; + DRM_DEBUG("item->age : %x\n", item->age); + DRM_DEBUG("item->next : %p\n", item->next); + DRM_DEBUG("item->prev : %p\n", item->prev); } -static int mga_dma_initialize(drm_device_t *dev, drm_mga_init_t *init) { - drm_mga_private_t *dev_priv; - drm_map_t *prim_map = NULL; - drm_map_t *sarea_map = NULL; - int temp; - - - dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); - if(dev_priv == NULL) return -ENOMEM; - dev->dev_private = (void *) dev_priv; - - printk("dev_private\n"); - - memset(dev_priv, 0, sizeof(drm_mga_private_t)); - atomic_set(&dev_priv->pending_bufs, 0); - - if((init->reserved_map_idx >= dev->map_count) || - (init->buffer_map_idx >= dev->map_count)) { - mga_dma_cleanup(dev); - printk("reserved_map or buffer_map are invalid\n"); - return -EINVAL; +static int mga_freelist_init(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_freelist_t *item; + int i; + + dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if(dev_priv->head == NULL) return -ENOMEM; + memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); + dev_priv->head->age = MGA_BUF_USED; + + for (i = 0; i < dma->buf_count; i++) { + buf = dma->buflist[ i ]; + buf_priv = buf->dev_private; + item = drm_alloc(sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER); + if(item == NULL) return -ENOMEM; + memset(item, 0, sizeof(drm_mga_freelist_t)); + item->age = MGA_BUF_FREE; + item->prev = dev_priv->head; + item->next = dev_priv->head->next; + if(dev_priv->head->next != NULL) + dev_priv->head->next->prev = item; + if(item->next == NULL) dev_priv->tail = item; + item->buf = buf; + buf_priv->my_freelist = item; + dev_priv->head->next = item; } - if(mga_alloc_kernel_queue(dev) != DRM_KERNEL_CONTEXT) { - mga_dma_cleanup(dev); - DRM_ERROR("Kernel context queue not present\n"); + item = dev_priv->head; + while(item) { + mga_freelist_debug(item); + item = item->next; } - - dev_priv->reserved_map_idx = init->reserved_map_idx; - dev_priv->buffer_map_idx = init->buffer_map_idx; - sarea_map = dev->maplist[0]; - dev_priv->sarea_priv = (drm_mga_sarea_t *) - ((u8 *)sarea_map->handle + - init->sarea_priv_offset); - printk("sarea_priv\n"); - - /* Scale primary size to the next page */ - dev_priv->primary_size = ((init->primary_size + PAGE_SIZE - 1) / - PAGE_SIZE) * PAGE_SIZE; - dev_priv->warp_ucode_size = init->warp_ucode_size; - dev_priv->chipset = init->chipset; - dev_priv->fbOffset = init->fbOffset; - dev_priv->backOffset = init->backOffset; - dev_priv->depthOffset = init->depthOffset; - dev_priv->textureOffset = init->textureOffset; - dev_priv->textureSize = init->textureSize; - dev_priv->cpp = init->cpp; - dev_priv->sgram = init->sgram; - dev_priv->stride = init->stride; - - dev_priv->frontOrg = init->frontOrg; - dev_priv->backOrg = init->backOrg; - dev_priv->depthOrg = init->depthOrg; - dev_priv->mAccess = init->mAccess; - + DRM_DEBUG("Head\n"); + mga_freelist_debug(dev_priv->head); + DRM_DEBUG("Tail\n"); + mga_freelist_debug(dev_priv->tail); - printk("memcpy\n"); - memcpy(&dev_priv->WarpIndex, &init->WarpIndex, - sizeof(mgaWarpIndex) * MGA_MAX_WARP_PIPES); - printk("memcpy done\n"); - prim_map = dev->maplist[init->reserved_map_idx]; - dev_priv->prim_phys_head = dev->agp->base + init->reserved_map_agpstart; - temp = init->warp_ucode_size + dev_priv->primary_size; - temp = ((temp + PAGE_SIZE - 1) / - PAGE_SIZE) * PAGE_SIZE; - printk("temp : %x\n", temp); - printk("dev->agp->base: %lx\n", dev->agp->base); - printk("init->reserved_map_agpstart: %x\n", init->reserved_map_agpstart); - + return 0; +} - dev_priv->ioremap = drm_ioremap(dev->agp->base + init->reserved_map_agpstart, - temp); - if(dev_priv->ioremap == NULL) { - printk("Ioremap failed\n"); - mga_dma_cleanup(dev); - return -ENOMEM; +static void mga_freelist_cleanup(drm_device_t *dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_freelist_t *item; + drm_mga_freelist_t *prev; + + item = dev_priv->head; + while(item) { + prev = item; + item = item->next; + drm_free(prev, + sizeof(drm_mga_freelist_t), + DRM_MEM_DRIVER); } - - - - dev_priv->prim_head = (u32 *)dev_priv->ioremap; - printk("dev_priv->prim_head : %p\n", dev_priv->prim_head); - dev_priv->current_dma_ptr = dev_priv->prim_head; - dev_priv->prim_num_dwords = 0; - dev_priv->prim_max_dwords = dev_priv->primary_size / 4; - printk("dma initialization\n"); - - /* Private is now filled in, initialize the hardware */ - { - PRIMLOCALS; - PRIMRESET( dev_priv ); - PRIMGETPTR( dev_priv ); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0); - PRIMOUTREG(MGAREG_SOFTRAP, 0); - PRIMADVANCE( dev_priv ); + dev_priv->head = dev_priv->tail = NULL; +} - /* Poll for the first buffer to insure that - * the status register will be correct - */ - printk("phys_head : %lx\n", phys_head); +static int __gettimeinmillis(void) +{ + int millis; - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) { - int i; - for(i = 0 ; i < 4096; i++) mga_delay(); - } - - MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); - - MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) | - PDEA_pagpxfer_enable)); - - while(MGA_READ(MGAREG_DWGSYNC) == MGA_SYNC_TAG) { - int i; - for(i = 0; i < 4096; i++) mga_delay(); - } + millis = ((jiffies / HZ) * 1000) + ((jiffies % HZ) * (1000 / HZ)); + return millis; +} +/* Frees dispatch lock */ +static inline void mga_dma_quiescent(drm_device_t *dev) +{ + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + int startTime = 0; + int curTime = 0; + int timeout_millis = 3000; + int i; + + while(1) { + if(!test_and_set_bit(0, &dev_priv->dispatch_lock)) { + break; + } + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup\n"); + goto out_nolock; + } + for (i = 0 ; i < 2000 ; i++) mga_delay(); } + startTime = 0; - printk("dma init was successful\n"); - return 0; + DRM_DEBUG("quiescent status : %x\n", MGA_READ(MGAREG_STATUS)); + while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup\n"); + goto out_status; + } + for (i = 0 ; i < 2000 ; i++) mga_delay(); + } + DRM_DEBUG("status[1] : %x last_sync_tag : %x\n", status[1], + dev_priv->last_sync_tag); + sarea_priv->dirty |= MGA_DMA_FLUSH; +out_status: + clear_bit(0, &dev_priv->dispatch_lock); +out_nolock: } -int mga_dma_init(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) +#define FREELIST_INITIAL (MGA_DMA_BUF_NR * 2) +#define FREELIST_COMPARE(age) ((age >> 2)) + +unsigned int mga_create_sync_tag(drm_device_t *dev) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_mga_init_t init; + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + unsigned int temp; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_device_dma_t *dma = dev->dma; + int i; - copy_from_user_ret(&init, (drm_mga_init_t *)arg, sizeof(init), -EFAULT); + dev_priv->sync_tag++; - switch(init.func) { - case MGA_INIT_DMA: - return mga_dma_initialize(dev, &init); - case MGA_CLEANUP_DMA: - return mga_dma_cleanup(dev); + if(dev_priv->sync_tag < FREELIST_INITIAL) { + dev_priv->sync_tag = FREELIST_INITIAL; } + if(dev_priv->sync_tag > 0x3fffffff) { + mga_flush_queue(dev); + mga_dma_quiescent(dev); + + for (i = 0; i < dma->buf_count; i++) { + buf = dma->buflist[ i ]; + buf_priv = buf->dev_private; + buf_priv->my_freelist->age = MGA_BUF_FREE; + } + + dev_priv->sync_tag = FREELIST_INITIAL; + } + temp = dev_priv->sync_tag << 2; - return -EINVAL; -} - -#define MGA_ILOAD_CMD (DC_opcod_iload | DC_atype_rpl | \ - DC_linear_linear | DC_bltmod_bfcol | \ - (0xC << DC_bop_SHIFT) | DC_sgnzero_enable | \ - DC_shftzero_enable | DC_clipdis_enable) - -static void __mga_iload_small(drm_device_t *dev, - drm_buf_t *buf, - int use_agp) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned long address = (unsigned long)buf->bus_address; - int length = buf->used; - int y1 = buf_priv->boxes[0].y1; - int x1 = buf_priv->boxes[0].x1; - int y2 = buf_priv->boxes[0].y2; - int x2 = buf_priv->boxes[0].x2; - int dstorg = buf_priv->ContextState[MGA_CTXREG_DSTORG]; - int maccess = buf_priv->ContextState[MGA_CTXREG_MACCESS]; - PRIMLOCALS; - - PRIMRESET(dev_priv); - PRIMGETPTR(dev_priv); - - PRIMOUTREG(MGAREG_DSTORG, dstorg | use_agp); - PRIMOUTREG(MGAREG_MACCESS, maccess); - PRIMOUTREG(MGAREG_PITCH, (1 << 15)); - PRIMOUTREG(MGAREG_YDST, y1 * (x2 - x1)); - PRIMOUTREG(MGAREG_LEN, 1); - PRIMOUTREG(MGAREG_FXBNDRY, ((x2 - x1) * (y2 - y1) - 1) << 16); - PRIMOUTREG(MGAREG_AR0, (x2 - x1) * (y2 - y1) - 1); - PRIMOUTREG(MGAREG_AR3, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, MGA_ILOAD_CMD); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SECADDRESS, address | TT_BLIT); - PRIMOUTREG(MGAREG_SECEND, (address + length) | use_agp); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0); - PRIMOUTREG(MGAREG_SOFTRAP, 0); - PRIMADVANCE(dev_priv); -#if 0 - /* For now we need to set this in the ioctl */ - sarea_priv->dirty |= MGASAREA_NEW_CONTEXT; -#endif - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) ; + dev_priv->sarea_priv->last_enqueue = temp; - MGA_WRITE(MGAREG_PRIMADDRESS, dev_priv->prim_phys_head | TT_GENERAL); - MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); + DRM_DEBUG("sync_tag : %x\n", temp); + return temp; } -static void __mga_iload_xy(drm_device_t *dev, - drm_buf_t *buf, - int use_agp) +/* Least recently used : + * These operations are not atomic b/c they are protected by the + * hardware lock */ + +drm_buf_t *mga_freelist_get(drm_device_t *dev) { - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned long address = (unsigned long)buf->bus_address; - int length = buf->used; - int y1 = buf_priv->boxes[0].y1; - int x1 = buf_priv->boxes[0].x1; - int y2 = buf_priv->boxes[0].y2; - int x2 = buf_priv->boxes[0].x2; - int dstorg = buf_priv->ContextState[MGA_CTXREG_DSTORG]; - int maccess = buf_priv->ContextState[MGA_CTXREG_MACCESS]; - int pitch = buf_priv->ServerState[MGA_2DREG_PITCH]; - int width, height; - int texperdword = 0; - PRIMLOCALS; - - width = (x2 - x1); - height = (y2 - y1); - switch((maccess & 0x00000003)) { - case 0: - texperdword = 4; - break; - case 1: - texperdword = 2; - break; - case 2: - texperdword = 1; - break; - default: - DRM_ERROR("Invalid maccess value passed to __mga_iload_xy\n"); - return; - } - - x2 = x1 + width; - x2 = (x2 + (texperdword - 1)) & ~(texperdword - 1); - x1 = (x1 + (texperdword - 1)) & ~(texperdword - 1); - width = x2 - x1; - - PRIMRESET(dev_priv); - PRIMGETPTR(dev_priv); - PRIMOUTREG(MGAREG_DSTORG, dstorg | use_agp); - PRIMOUTREG(MGAREG_MACCESS, maccess); - PRIMOUTREG(MGAREG_PITCH, pitch); - PRIMOUTREG(MGAREG_YDSTLEN, (y1 << 16) | height); - - PRIMOUTREG(MGAREG_FXBNDRY, ((x1+width-1) << 16) | x1); - PRIMOUTREG(MGAREG_AR0, width * height - 1); - PRIMOUTREG(MGAREG_AR3, 0 ); - PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, MGA_ILOAD_CMD); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_SECADDRESS, address | TT_BLIT); - PRIMOUTREG(MGAREG_SECEND, (address + length) | use_agp); - - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DMAPAD, 0); - PRIMOUTREG(MGAREG_DWGSYNC, 0); - PRIMOUTREG(MGAREG_SOFTRAP, 0); - PRIMADVANCE(dev_priv); + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + drm_mga_freelist_t *prev; + drm_mga_freelist_t *next; + + if((dev_priv->tail->age >> 2) <= FREELIST_COMPARE(status[1])) { + drm_mga_buf_priv_t *buf_priv; + prev = dev_priv->tail->prev; + next = dev_priv->tail; + prev->next = NULL; + next->prev = next->next = NULL; + dev_priv->tail = prev; + next->age = MGA_BUF_USED; + return next->buf; + } #if 0 - /* For now we need to set this in the ioctl */ - sarea_priv->dirty |= MGASAREA_NEW_CONTEXT; + else { + mga_freelist_debug(dev_priv->tail); + DRM_DEBUG("sarea->last_dispatch %x\n", sarea_priv->last_dispatch); + mga_freelist_debug(dev_priv->tail->prev); + } #endif - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) ; - - MGA_WRITE(MGAREG_PRIMADDRESS, dev_priv->prim_phys_head | TT_GENERAL); - MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); + return NULL; } -static void mga_dma_dispatch_iload(drm_device_t *dev, drm_buf_t *buf) +int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; - - int use_agp = PDEA_pagpxfer_enable; - int x1 = buf_priv->boxes[0].x1; - int x2 = buf_priv->boxes[0].x2; - - if((x2 - x1) < 32) { - printk("using iload small\n"); - __mga_iload_small(dev, buf, use_agp); + drm_mga_freelist_t *prev; + drm_mga_freelist_t *head; + drm_mga_freelist_t *next; + + if(buf_priv->my_freelist->age == MGA_BUF_USED) { + /* Discarded buffer, put it on the tail */ + next = buf_priv->my_freelist; + next->age = MGA_BUF_FREE; + prev = dev_priv->tail; + prev->next = next; + next->prev = prev; + next->next = NULL; + dev_priv->tail = next; + DRM_DEBUG("Discarded\n"); } else { - printk("using iload xy\n"); - __mga_iload_xy(dev, buf, use_agp); - } + /* Normally aged buffer, put it on the head + 1, + * as the real head is a sentinal element + */ + next = buf_priv->my_freelist; + head = dev_priv->head; + prev = head->next; + head->next = next; + prev->prev = next; + next->prev = head; + next->next = prev; + } + + return 0; } -static void mga_dma_dispatch_vertex(drm_device_t *dev, drm_buf_t *buf) +static void mga_print_all_primary(drm_device_t *dev) { - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - unsigned long address = (unsigned long)buf->bus_address; - int length = buf->used; - int use_agp = PDEA_pagpxfer_enable; - int i, count; - PRIMLOCALS; - - PRIMRESET(dev_priv); - - count = buf_priv->nbox; - if (count == 0) - count = 1; - - mgaEmitState( dev_priv, buf_priv ); - - for (i = 0 ; i < count ; i++) { - if (i < buf_priv->nbox) - mgaEmitClipRect( dev_priv, &buf_priv->boxes[i] ); - - PRIMGETPTR(dev_priv); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_SECADDRESS, address | TT_VERTEX); - PRIMOUTREG( MGAREG_SECEND, (address + length) | use_agp); - - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DWGSYNC, 0); - PRIMOUTREG( MGAREG_SOFTRAP, 0); - PRIMADVANCE(dev_priv); + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_prim_buf_t *prim; + int i; + + DRM_DEBUG("Full list of primarys\n"); + for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { + prim = dev_priv->prim_bufs[i]; + DRM_DEBUG("index : %d num_dwords : %d max_dwords : %d phy_head : %lx\n", + prim->idx, prim->num_dwords, prim->max_dwords, prim->phys_head); + DRM_DEBUG("sec_used : %d swap_pending : %x in_use : %lx force_fire : %d\n", + prim->sec_used, prim->swap_pending, prim->in_use, atomic_read(&prim->force_fire)); + DRM_DEBUG("needs_overflow : %d\n", atomic_read(&prim->needs_overflow)); } - - PRIMGETPTR( dev_priv ); - - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) ; - - MGA_WRITE(MGAREG_PRIMADDRESS, dev_priv->prim_phys_head | TT_GENERAL); - MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); + + DRM_DEBUG("current_idx : %d, next_idx : %d, last_idx : %d\n", + dev_priv->next_prim->idx, dev_priv->last_prim->idx, + dev_priv->current_prim->idx); } - -/* Used internally for the small buffers generated from client state - * information. - */ -static void mga_dma_dispatch_general(drm_device_t *dev, drm_buf_t *buf) +static int mga_init_primary_bufs(drm_device_t *dev, drm_mga_init_t *init) { drm_mga_private_t *dev_priv = dev->dev_private; - unsigned long address = (unsigned long)buf->bus_address; - int length = buf->used; - int use_agp = PDEA_pagpxfer_enable; - PRIMLOCALS; - - PRIMRESET(dev_priv); - PRIMGETPTR(dev_priv); - - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_SECADDRESS, address | TT_GENERAL); - PRIMOUTREG( MGAREG_SECEND, (address + length) | use_agp); - - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DMAPAD, 0); - PRIMOUTREG( MGAREG_DWGSYNC, 0); - PRIMOUTREG( MGAREG_SOFTRAP, 0); - PRIMADVANCE(dev_priv); + drm_mga_prim_buf_t *prim_buffer; + int i, temp, size_of_buf; + int offset = init->reserved_map_agpstart; - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) ; - - MGA_WRITE(MGAREG_PRIMADDRESS, dev_priv->prim_phys_head | TT_GENERAL); - MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); -} - -/* Frees dispatch lock */ -static inline void mga_dma_quiescent(drm_device_t *dev) -{ - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - - while(1) { - atomic_inc(&dev_priv->dispatch_lock); - if(atomic_read(&dev_priv->dispatch_lock) == 1) { - break; - } else { - atomic_dec(&dev_priv->dispatch_lock); - } + DRM_DEBUG("mga_init_primary_bufs\n"); + dev_priv->primary_size = ((init->primary_size + PAGE_SIZE - 1) / + PAGE_SIZE) * PAGE_SIZE; + DRM_DEBUG("primary_size\n"); + size_of_buf = dev_priv->primary_size / MGA_NUM_PRIM_BUFS; + dev_priv->warp_ucode_size = init->warp_ucode_size; + dev_priv->prim_bufs = drm_alloc(sizeof(drm_mga_prim_buf_t *) * + (MGA_NUM_PRIM_BUFS + 1), + DRM_MEM_DRIVER); + if(dev_priv->prim_bufs == NULL) { + DRM_ERROR("Unable to allocate memory for prim_buf\n"); + return -ENOMEM; } - while((MGA_READ(MGAREG_STATUS) & 0x00020001) != 0x00020000) ; -#if 0 - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); -#endif - while(MGA_READ(MGAREG_DWGSYNC) == MGA_SYNC_TAG) ; - MGA_WRITE(MGAREG_DWGSYNC, MGA_SYNC_TAG); - while(MGA_READ(MGAREG_DWGSYNC) != MGA_SYNC_TAG) ; - atomic_dec(&dev_priv->dispatch_lock); + DRM_DEBUG("memset\n"); + memset(dev_priv->prim_bufs, + 0, sizeof(drm_mga_prim_buf_t *) * (MGA_NUM_PRIM_BUFS + 1)); + + temp = init->warp_ucode_size + dev_priv->primary_size; + temp = ((temp + PAGE_SIZE - 1) / + PAGE_SIZE) * PAGE_SIZE; + + DRM_DEBUG("temp : %x\n", temp); + DRM_DEBUG("dev->agp->base: %lx\n", dev->agp->base); + DRM_DEBUG("init->reserved_map_agpstart: %x\n", + init->reserved_map_agpstart); + DRM_DEBUG("ioremap\n"); + dev_priv->ioremap = drm_ioremap(dev->agp->base + offset, + temp); + if(dev_priv->ioremap == NULL) { + DRM_DEBUG("Ioremap failed\n"); + return -ENOMEM; + } + init_waitqueue_head(&dev_priv->wait_queue); + + for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { + DRM_DEBUG("For loop\n"); + prim_buffer = drm_alloc(sizeof(drm_mga_prim_buf_t), DRM_MEM_DRIVER); + if(prim_buffer == NULL) return -ENOMEM; + DRM_DEBUG("memset\n"); + memset(prim_buffer, 0, sizeof(drm_mga_prim_buf_t)); + prim_buffer->phys_head = offset + dev->agp->base; + prim_buffer->current_dma_ptr = prim_buffer->head = (u32 *) + (dev_priv->ioremap + (offset - init->reserved_map_agpstart)); + prim_buffer->num_dwords = 0; + prim_buffer->max_dwords = size_of_buf / sizeof(u32); + prim_buffer->max_dwords -= 5; /* Leave room for the softrap */ + prim_buffer->sec_used = 0; + prim_buffer->idx = i; + offset = offset + size_of_buf; + dev_priv->prim_bufs[i] = prim_buffer; + DRM_DEBUG("Looping\n"); + } + dev_priv->current_prim_idx = 0; + dev_priv->next_prim = dev_priv->last_prim = dev_priv->current_prim = + dev_priv->prim_bufs[0]; + set_bit(0, &dev_priv->current_prim->in_use); + DRM_DEBUG("init done\n"); + return 0; } -/* Keeps dispatch lock held */ - -static inline int mga_dma_is_ready(drm_device_t *dev) +void mga_fire_primary(drm_device_t *dev, drm_mga_prim_buf_t *prim) { - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = dev->dev_private; + drm_device_dma_t *dma = dev->dma; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + int use_agp = PDEA_pagpxfer_enable; + int startTime = 0; + int curTime = 0; + int timeout_millis = 3000; + int i; + int next_idx; + PRIMLOCALS; - atomic_inc(&dev_priv->dispatch_lock); - if(atomic_read(&dev_priv->dispatch_lock) == 1) { - /* We got the lock */ - return 1; + DRM_DEBUG("mga_fire_primary\n"); + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + dev_priv->last_prim = prim; + + /* We never check for overflow, b/c there is always room */ + PRIMPTR(prim); + if(num_dwords <= 0) { + DRM_DEBUG("num_dwords == 0 when dispatched\n"); + goto out_prim_wait; + } + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMOUTREG( MGAREG_SOFTRAP, 0); + PRIMFINISH(prim); + + if(sarea_priv->dirty & MGA_DMA_FLUSH) { + DRM_DEBUG("Dma top flush\n"); + while((MGA_READ(MGAREG_STATUS) & 0x00030001) != 0x00020000) { + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup in fire primary (Dma Top Flush)\n"); + goto out_prim_wait; + } + + for (i = 0 ; i < 4096 ; i++) mga_delay(); + } + sarea_priv->dirty &= ~(MGA_DMA_FLUSH); } else { - atomic_dec(&dev_priv->dispatch_lock); - return 0; + DRM_DEBUG("Status wait\n"); + while((MGA_READ(MGAREG_STATUS) & 0x00020001) != 0x00020000) { + curTime = __gettimeinmillis(); + if (startTime == 0 || curTime < startTime /*wrap case*/) { + startTime = curTime; + } else if (curTime - startTime > timeout_millis) { + DRM_ERROR("irqs: %d wanted %d\n", + atomic_read(&dev->total_irq), + atomic_read(&dma->total_lost)); + DRM_ERROR("lockup in fire primary (Status Wait)\n"); + goto out_prim_wait; + } + + for (i = 0 ; i < 4096 ; i++) mga_delay(); + } + } + + mga_flush_write_combine(); + atomic_inc(&dev_priv->pending_bufs); + atomic_inc(&dma->total_lost); + MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); + MGA_WRITE(MGAREG_PRIMEND, (phys_head + num_dwords * 4) | use_agp); + DRM_DEBUG("Primarys at fire\n"); + prim->num_dwords = 0; + + next_idx = prim->idx + 1; + if(next_idx >= MGA_NUM_PRIM_BUFS) { + next_idx = 0; + } + dev_priv->next_prim = dev_priv->prim_bufs[next_idx]; + +/* mga_print_all_primary(dev); */ + return; + +out_prim_wait: + { + prim->num_dwords = 0; + prim->sec_used = 0; + clear_bit(0, &prim->in_use); + clear_bit(0, &prim->swap_pending); + clear_bit(0, &dev_priv->dispatch_lock); + atomic_dec(&dev_priv->pending_bufs); } } -static inline int mga_dma_is_ready_no_hold(drm_device_t *dev) +int mga_advance_primary(drm_device_t *dev) { - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + DECLARE_WAITQUEUE(entry, current); + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_prim_buf_t *prim_buffer; + drm_device_dma_t *dma = dev->dma; + int next_prim_idx; + int ret = 0; - atomic_inc(&dev_priv->dispatch_lock); - if(atomic_read(&dev_priv->dispatch_lock) == 1) { - /* We got the lock, but free it */ - atomic_dec(&dev_priv->dispatch_lock); - return 1; - } else { - atomic_dec(&dev_priv->dispatch_lock); - return 0; + /* This needs to reset the primary buffer if available, + * we should collect stats on how many times it bites + * it's tail */ + + next_prim_idx = dev_priv->current_prim_idx + 1; + if(next_prim_idx >= MGA_NUM_PRIM_BUFS) + next_prim_idx = 0; + prim_buffer = dev_priv->prim_bufs[next_prim_idx]; + atomic_set(&dev_priv->in_wait, 1); + + /* In use is cleared in interrupt handler */ + + if(test_and_set_bit(0, &prim_buffer->in_use)) { + add_wait_queue(&dev_priv->wait_queue, &entry); + for (;;) { + current->state = TASK_INTERRUPTIBLE; + mga_dma_schedule(dev, 0); + if(!test_and_set_bit(0, &prim_buffer->in_use)) break; + atomic_inc(&dev->total_sleeps); + atomic_inc(&dma->total_missed_sched); + mga_print_all_primary(dev); + DRM_DEBUG("Schedule in advance\n"); + /* Three second delay */ + schedule_timeout(HZ*3); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->wait_queue, &entry); + if(ret) return ret; } + atomic_set(&dev_priv->in_wait, 0); + /* This primary buffer is now free to use */ + prim_buffer->current_dma_ptr = prim_buffer->head; + prim_buffer->num_dwords = 0; + prim_buffer->sec_used = 0; + atomic_set(&prim_buffer->needs_overflow, 0); + dev_priv->current_prim = prim_buffer; + dev_priv->current_prim_idx = next_prim_idx; + DRM_DEBUG("Primarys at advance\n"); + mga_print_all_primary(dev); + return 0; } -static void mga_dma_service(int irq, void *device, struct pt_regs *regs) +/* More dynamic performance decisions */ +static inline int mga_decide_to_fire(drm_device_t *dev) { - drm_device_t *dev = (drm_device_t *)device; - drm_device_dma_t *dma = dev->dma; drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - - atomic_dec(&dev_priv->dispatch_lock); - atomic_inc(&dev->total_irq); - MGA_WRITE(MGAREG_ICLEAR, 0xfa7); - - /* Free previous buffer */ - if (test_and_set_bit(0, &dev->dma_flag)) { - atomic_inc(&dma->total_missed_free); - return; + drm_device_dma_t *dma = dev->dma; + + if(atomic_read(&dev_priv->next_prim->force_fire) || + (atomic_read(&dev_priv->in_flush) && dev_priv->next_prim->num_dwords)) { + atomic_inc(&dma->total_prio); + return 1; + } + if(atomic_read(&dev_priv->pending_bufs) <= (MGA_NUM_PRIM_BUFS - 1)) { + + if(test_bit(0, &dev_priv->next_prim->swap_pending)) { + atomic_inc(&dma->total_dmas); + return 1; + } + } + if(atomic_read(&dev_priv->pending_bufs) <= (MGA_NUM_PRIM_BUFS / 2)) { + if(dev_priv->next_prim->sec_used >= (MGA_DMA_BUF_NR / 8)) { + atomic_inc(&dma->total_hit); + return 1; + } } - if (dma->this_buffer) { - drm_free_buffer(dev, dma->this_buffer); - dma->this_buffer = NULL; + if(atomic_read(&dev_priv->pending_bufs) >= (MGA_NUM_PRIM_BUFS / 2)) { + if(dev_priv->next_prim->sec_used >= (MGA_DMA_BUF_NR / 4)) { + atomic_inc(&dma->total_missed_free); + return 1; + } } - clear_bit(0, &dev->dma_flag); - - /* Dispatch new buffer */ - queue_task(&dev->tq, &tq_immediate); - mark_bh(IMMEDIATE_BH); + atomic_inc(&dma->total_tried); + return 0; } -/* Only called by mga_dma_schedule. */ -static int mga_do_dma(drm_device_t *dev, int locked) +int mga_dma_schedule(drm_device_t *dev, int locked) { - drm_buf_t *buf; - int retcode = 0; - drm_device_dma_t *dma = dev->dma; drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_mga_buf_priv_t *buf_priv; + drm_device_dma_t *dma = dev->dma; - printk("mga_do_dma\n"); - if (test_and_set_bit(0, &dev->dma_flag)) { + if (test_and_set_bit(0, &dev->dma_flag)) { atomic_inc(&dma->total_missed_dma); return -EBUSY; } - - if (!dma->next_buffer) { - DRM_ERROR("No next_buffer\n"); - clear_bit(0, &dev->dma_flag); - return -EINVAL; - } - - buf = dma->next_buffer; - - printk("context %d, buffer %d\n", buf->context, buf->idx); - - if (buf->list == DRM_LIST_RECLAIM) { - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - clear_bit(0, &dev->dma_flag); - return -EINVAL; - } + + DRM_DEBUG("mga_dma_schedule\n"); - if (!buf->used) { - DRM_ERROR("0 length buffer\n"); - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); - clear_bit(0, &dev->dma_flag); - return 0; - } - - if (mga_dma_is_ready(dev) == 0) { - clear_bit(0, &dev->dma_flag); - return -EBUSY; + if(atomic_read(&dev_priv->in_flush) || + atomic_read(&dev_priv->in_wait)) { + locked = 1; } - /* Always hold the hardware lock while dispatching. - */ - if (!locked && !drm_lock_take(&dev->lock.hw_lock->lock, + if (!locked && + !drm_lock_take(&dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) { - atomic_inc(&dma->total_missed_lock); - clear_bit(0, &dev->dma_flag); - atomic_dec(&dev_priv->dispatch_lock); - return -EBUSY; + atomic_inc(&dma->total_missed_lock); + clear_bit(0, &dev->dma_flag); + return -EBUSY; } + DRM_DEBUG("I'm locked\n"); - dma->next_queue = dev->queuelist[DRM_KERNEL_CONTEXT]; - drm_clear_next_buffer(dev); - buf->pending = 1; - buf->waiting = 0; - buf->list = DRM_LIST_PEND; - - buf_priv = buf->dev_private; - - printk("dispatch!\n"); - switch (buf_priv->dma_type) { - case MGA_DMA_GENERAL: - mga_dma_dispatch_general(dev, buf); - break; - case MGA_DMA_VERTEX: - mga_dma_dispatch_vertex(dev, buf); - break; -/* case MGA_DMA_SETUP: */ -/* mga_dma_dispatch_setup(dev, address, length); */ -/* break; */ - case MGA_DMA_ILOAD: - mga_dma_dispatch_iload(dev, buf); - break; - default: - printk("bad buffer type %x in dispatch\n", buf_priv->dma_type); - break; + + if(!test_and_set_bit(0, &dev_priv->dispatch_lock)) { + /* Fire dma buffer */ + if(mga_decide_to_fire(dev)) { + DRM_DEBUG("mga_fire_primary\n"); + DRM_DEBUG("idx :%d\n", dev_priv->next_prim->idx); + atomic_set(&dev_priv->next_prim->force_fire, 0); + if(dev_priv->current_prim == dev_priv->next_prim && + dev_priv->next_prim->num_dwords != 0) { + /* Schedule overflow for a later time */ + atomic_set(&dev_priv->current_prim->needs_overflow, + 1); + } + mga_fire_primary(dev, + dev_priv->next_prim); + } else { + clear_bit(0, &dev_priv->dispatch_lock); + } + } else { + DRM_DEBUG("I can't get the dispatch lock\n"); } - atomic_dec(&dev_priv->pending_bufs); - - drm_free_buffer(dev, dma->this_buffer); - dma->this_buffer = buf; - - atomic_add(buf->used, &dma->total_bytes); - atomic_inc(&dma->total_dmas); - + if (!locked) { if (drm_lock_free(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) { @@ -692,90 +663,247 @@ static int mga_do_dma(drm_device_t *dev, int locked) } } - clear_bit(0, &dev->dma_flag); - - if(!atomic_read(&dev_priv->pending_bufs)) { - wake_up_interruptible(&dev->queuelist[DRM_KERNEL_CONTEXT]->flush_queue); - } - -#if 0 - wake_up_interruptible(&dev->lock.lock_queue); -#endif + clear_bit(0, &dev->dma_flag); - /* We hold the dispatch lock until the interrupt handler - * frees it - */ - return retcode; + if(atomic_read(&dev_priv->in_flush) == 1 && + dev_priv->next_prim->num_dwords == 0) { + /* Everything is on the hardware */ + DRM_DEBUG("Primarys at Flush\n"); + mga_print_all_primary(dev); + atomic_set(&dev_priv->in_flush, 0); + wake_up_interruptible(&dev_priv->flush_queue); + } + + return 0; } -static void mga_dma_schedule_timer_wrapper(unsigned long dev) +static void mga_dma_service(int irq, void *device, struct pt_regs *regs) { - mga_dma_schedule((drm_device_t *)dev, 0); + drm_device_t *dev = (drm_device_t *)device; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_prim_buf_t *last_prim_buffer; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + + atomic_inc(&dev->total_irq); + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); + last_prim_buffer = dev_priv->last_prim; + last_prim_buffer->num_dwords = 0; + last_prim_buffer->sec_used = 0; + clear_bit(0, &last_prim_buffer->in_use); + clear_bit(0, &last_prim_buffer->swap_pending); + clear_bit(0, &dev_priv->dispatch_lock); + atomic_dec(&dev_priv->pending_bufs); + dev_priv->sarea_priv->last_dispatch = status[1]; + queue_task(&dev->tq, &tq_immediate); + mark_bh(IMMEDIATE_BH); } -static void mga_dma_schedule_tq_wrapper(void *dev) +static void mga_dma_task_queue(void *device) { + drm_device_t *dev = (drm_device_t *) device; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + mga_dma_schedule(dev, 0); + wake_up_interruptible(&dev_priv->wait_queue); } -int mga_dma_schedule(drm_device_t *dev, int locked) +int mga_dma_cleanup(drm_device_t *dev) { - drm_queue_t *q; - drm_buf_t *buf; - int retcode = 0; - int processed = 0; - int missed; - int expire = 20; - drm_device_dma_t *dma = dev->dma; - - printk("mga_dma_schedule\n"); - - if (test_and_set_bit(0, &dev->interrupt_flag)) { - /* Not reentrant */ - atomic_inc(&dma->total_missed_sched); - return -EBUSY; - } - missed = atomic_read(&dma->total_missed_sched); + if(dev->dev_private) { + drm_mga_private_t *dev_priv = + (drm_mga_private_t *) dev->dev_private; + + if(dev_priv->ioremap) { + int temp = (dev_priv->warp_ucode_size + + dev_priv->primary_size + + PAGE_SIZE - 1) / PAGE_SIZE * PAGE_SIZE; -again: - /* There is only one queue: - */ - if (!dma->next_buffer && DRM_WAITCOUNT(dev, DRM_KERNEL_CONTEXT)) { - q = dev->queuelist[DRM_KERNEL_CONTEXT]; - buf = drm_waitlist_get(&q->waitlist); - dma->next_buffer = buf; - dma->next_queue = q; - if (buf && buf->list == DRM_LIST_RECLAIM) { - drm_clear_next_buffer(dev); - drm_free_buffer(dev, buf); + drm_ioremapfree((void *) dev_priv->ioremap, temp); + } + if(dev_priv->status_page != NULL) { + iounmap(dev_priv->status_page); } + if(dev_priv->real_status_page != 0UL) { + mga_free_page(dev, dev_priv->real_status_page); + } + if(dev_priv->prim_bufs != NULL) { + int i; + for(i = 0; i < MGA_NUM_PRIM_BUFS; i++) { + if(dev_priv->prim_bufs[i] != NULL) { + drm_free(dev_priv->prim_bufs[i], + sizeof(drm_mga_prim_buf_t), + DRM_MEM_DRIVER); + } + } + drm_free(dev_priv->prim_bufs, sizeof(void *) * + (MGA_NUM_PRIM_BUFS + 1), + DRM_MEM_DRIVER); + } + if(dev_priv->head != NULL) { + mga_freelist_cleanup(dev); + } + + + drm_free(dev->dev_private, sizeof(drm_mga_private_t), + DRM_MEM_DRIVER); + dev->dev_private = NULL; } - if (dma->next_buffer) { - if (!(retcode = mga_do_dma(dev, locked))) - ++processed; + return 0; +} + +static int mga_dma_initialize(drm_device_t *dev, drm_mga_init_t *init) { + drm_mga_private_t *dev_priv; + drm_map_t *sarea_map = NULL; + int i; + + dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); + if(dev_priv == NULL) return -ENOMEM; + dev->dev_private = (void *) dev_priv; + + DRM_DEBUG("dev_private\n"); + + memset(dev_priv, 0, sizeof(drm_mga_private_t)); + atomic_set(&dev_priv->in_flush, 0); + + if((init->reserved_map_idx >= dev->map_count) || + (init->buffer_map_idx >= dev->map_count)) { + mga_dma_cleanup(dev); + DRM_DEBUG("reserved_map or buffer_map are invalid\n"); + return -EINVAL; } + + dev_priv->reserved_map_idx = init->reserved_map_idx; + dev_priv->buffer_map_idx = init->buffer_map_idx; + sarea_map = dev->maplist[0]; + dev_priv->sarea_priv = (drm_mga_sarea_t *) + ((u8 *)sarea_map->handle + + init->sarea_priv_offset); + DRM_DEBUG("sarea_priv\n"); - /* Try again if we succesfully dispatched a buffer, or if someone - * tried to schedule while we were working. - */ - if (--expire) { - if (missed != atomic_read(&dma->total_missed_sched)) { - atomic_inc(&dma->total_lost); - if (mga_dma_is_ready_no_hold(dev)) - goto again; - } + /* Scale primary size to the next page */ + dev_priv->chipset = init->chipset; + dev_priv->frontOffset = init->frontOffset; + dev_priv->backOffset = init->backOffset; + dev_priv->depthOffset = init->depthOffset; + dev_priv->textureOffset = init->textureOffset; + dev_priv->textureSize = init->textureSize; + dev_priv->cpp = init->cpp; + dev_priv->sgram = init->sgram; + dev_priv->stride = init->stride; - if (processed && mga_dma_is_ready_no_hold(dev)) { - atomic_inc(&dma->total_lost); - processed = 0; - goto again; - } + dev_priv->mAccess = init->mAccess; + init_waitqueue_head(&dev_priv->flush_queue); + dev_priv->WarpPipe = -1; + + DRM_DEBUG("chipset: %d ucode_size: %d backOffset: %x depthOffset: %x\n", + dev_priv->chipset, dev_priv->warp_ucode_size, + dev_priv->backOffset, dev_priv->depthOffset); + DRM_DEBUG("cpp: %d sgram: %d stride: %d maccess: %x\n", + dev_priv->cpp, dev_priv->sgram, dev_priv->stride, + dev_priv->mAccess); + + memcpy(&dev_priv->WarpIndex, &init->WarpIndex, + sizeof(mgaWarpIndex) * MGA_MAX_WARP_PIPES); + + for (i = 0 ; i < MGA_MAX_WARP_PIPES ; i++) + DRM_DEBUG("warp pipe %d: installed: %d phys_addr: %lx size: %x\n", + i, + dev_priv->WarpIndex[i].installed, + dev_priv->WarpIndex[i].phys_addr, + dev_priv->WarpIndex[i].size); + + DRM_DEBUG("Doing init prim buffers\n"); + if(mga_init_primary_bufs(dev, init) != 0) { + DRM_ERROR("Can not initialize primary buffers\n"); + mga_dma_cleanup(dev); + return -ENOMEM; } - - clear_bit(0, &dev->interrupt_flag); - - return retcode; + DRM_DEBUG("Done with init prim buffers\n"); + dev_priv->real_status_page = mga_alloc_page(dev); + if(dev_priv->real_status_page == 0UL) { + mga_dma_cleanup(dev); + DRM_ERROR("Can not allocate status page\n"); + return -ENOMEM; + } + DRM_DEBUG("Status page at %lx\n", dev_priv->real_status_page); + dev_priv->status_page = ioremap_nocache(virt_to_bus((void *) dev_priv->real_status_page), + PAGE_SIZE); + if(dev_priv->status_page == NULL) { + mga_dma_cleanup(dev); + DRM_ERROR("Can not remap status page\n"); + return -ENOMEM; + } + + DRM_DEBUG("Status page remapped to %p\n", dev_priv->status_page); + /* Write status page when secend or softrap occurs */ + MGA_WRITE(MGAREG_PRIMPTR, virt_to_bus((void *)dev_priv->real_status_page) | 0x00000003); + + dev_priv->device = pci_find_device(0x102b, 0x0525, NULL); + if(dev_priv->device == NULL) { + DRM_ERROR("Could not find pci device for card\n"); + mga_dma_cleanup(dev); + return -EINVAL; + } + + DRM_DEBUG("dma initialization\n"); + + /* Private is now filled in, initialize the hardware */ + { + __volatile__ unsigned int *status = (unsigned int *)dev_priv->status_page; + PRIMLOCALS; + PRIMGETPTR( dev_priv ); + + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMOUTREG(MGAREG_SOFTRAP, 0); + /* Poll for the first buffer to insure that + * the status register will be correct + */ + DRM_DEBUG("phys_head : %lx\n", (unsigned long)phys_head); + status[1] = 0; + + mga_flush_write_combine(); + MGA_WRITE(MGAREG_PRIMADDRESS, phys_head | TT_GENERAL); + + MGA_WRITE(MGAREG_PRIMEND, ((phys_head + num_dwords * 4) | + PDEA_pagpxfer_enable)); + + while(MGA_READ(MGAREG_DWGSYNC) != dev_priv->last_sync_tag) ; + DRM_DEBUG("status[0] after initialization : %x\n", status[0]); + DRM_DEBUG("status[1] after initialization : %x\n", status[1]); + } + + if(mga_freelist_init(dev) != 0) { + DRM_ERROR("Could not initialize freelist\n"); + mga_dma_cleanup(dev); + return -ENOMEM; + } + DRM_DEBUG("dma init was successful\n"); + return 0; +} + +int mga_dma_init(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_init_t init; + + copy_from_user_ret(&init, (drm_mga_init_t *)arg, sizeof(init), -EFAULT); + + switch(init.func) { + case MGA_INIT_DMA: + return mga_dma_initialize(dev, &init); + case MGA_CLEANUP_DMA: + return mga_dma_cleanup(dev); + } + + return -EINVAL; } int mga_irq_install(drm_device_t *dev, int irq) @@ -792,7 +920,7 @@ int mga_irq_install(drm_device_t *dev, int irq) dev->irq = irq; up(&dev->struct_sem); - printk("install irq handler %d\n", irq); + DRM_DEBUG("install irq handler %d\n", irq); dev->context_flag = 0; dev->interrupt_flag = 0; @@ -802,13 +930,11 @@ int mga_irq_install(drm_device_t *dev, int irq) dev->dma->this_buffer = NULL; dev->tq.next = NULL; dev->tq.sync = 0; - dev->tq.routine = mga_dma_schedule_tq_wrapper; + dev->tq.routine = mga_dma_task_queue; dev->tq.data = dev; /* Before installing handler */ - MGA_WRITE(MGAREG_ICLEAR, 0xfa7); MGA_WRITE(MGAREG_IEN, 0); - /* Install handler */ if ((retcode = request_irq(dev->irq, mga_dma_service, @@ -820,11 +946,9 @@ int mga_irq_install(drm_device_t *dev, int irq) up(&dev->struct_sem); return retcode; } - /* After installing handler */ - MGA_WRITE(MGAREG_ICLEAR, 0xfa7); + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); MGA_WRITE(MGAREG_IEN, 0x00000001); - return 0; } @@ -838,19 +962,13 @@ int mga_irq_uninstall(drm_device_t *dev) up(&dev->struct_sem); if (!irq) return -EINVAL; - - printk("remove irq handler %d\n", irq); - - MGA_WRITE(MGAREG_ICLEAR, 0xfa7); + DRM_DEBUG("remove irq handler %d\n", irq); + MGA_WRITE(MGAREG_ICLEAR, 0x00000001); MGA_WRITE(MGAREG_IEN, 0); - MGA_WRITE(MGAREG_ICLEAR, 0xfa7); - free_irq(irq, dev); - return 0; } - int mga_control(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { @@ -870,36 +988,64 @@ int mga_control(struct inode *inode, struct file *filp, unsigned int cmd, } } -int mga_flush_queue(drm_device_t *dev) +static int mga_flush_queue(drm_device_t *dev) { DECLARE_WAITQUEUE(entry, current); - drm_queue_t *q = dev->queuelist[DRM_KERNEL_CONTEXT]; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; int ret = 0; - - printk("mga_flush_queue\n"); - if(atomic_read(&dev_priv->pending_bufs) != 0) { - current->state = TASK_INTERRUPTIBLE; - add_wait_queue(&q->flush_queue, &entry); - for (;;) { - if (!atomic_read(&dev_priv->pending_bufs)) break; - printk("Calling schedule from flush_queue : %d\n", - atomic_read(&dev_priv->pending_bufs)); - mga_dma_schedule(dev, 1); - schedule(); - if (signal_pending(current)) { - ret = -EINTR; /* Can't restart */ - break; - } - } - printk("Exited out of schedule from flush_queue\n"); - current->state = TASK_RUNNING; - remove_wait_queue(&q->flush_queue, &entry); + + if(dev_priv == NULL) { + return 0; } + if(dev_priv->next_prim->num_dwords != 0) { + atomic_set(&dev_priv->in_flush, 1); + current->state = TASK_INTERRUPTIBLE; + add_wait_queue(&dev_priv->flush_queue, &entry); + for (;;) { + mga_dma_schedule(dev, 0); + if (atomic_read(&dev_priv->in_flush) == 0 || + dev_priv->next_prim->num_dwords == 0) break; + atomic_inc(&dev->total_sleeps); + DRM_DEBUG("Schedule in flush_queue\n"); + schedule_timeout(HZ/60); + if (signal_pending(current)) { + ret = -EINTR; /* Can't restart */ + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev_priv->flush_queue, &entry); + } + atomic_set(&dev_priv->in_flush, 0); return ret; } +/* Must be called with the lock held */ +void mga_reclaim_buffers(drm_device_t *dev, pid_t pid) +{ + drm_device_dma_t *dma = dev->dma; + int i; + + if (!dma) return; + if(dev->dev_private == NULL) return; + + mga_flush_queue(dev); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[ i ]; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + + if (buf->pid == pid) { + if(buf_priv == NULL) return; + /* Only buffers that need to get reclaimed ever + * get set to free */ + if(buf_priv->my_freelist->age == MGA_BUF_USED) + buf_priv->my_freelist->age = MGA_BUF_FREE; + } + } +} + int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { @@ -916,16 +1062,15 @@ int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, current->pid, lock.context); return -EINVAL; } - - printk("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", - lock.context, current->pid, dev->lock.hw_lock->lock, - lock.flags); - + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); if (lock.context < 0) { return -EINVAL; } - + /* Only one queue: */ @@ -948,8 +1093,7 @@ int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, /* Contention */ atomic_inc(&dev->total_sleeps); current->state = TASK_INTERRUPTIBLE; - current->policy |= SCHED_YIELD; - printk("Calling lock schedule\n"); + DRM_DEBUG("Calling lock schedule\n"); schedule(); if (signal_pending(current)) { ret = -ERESTARTSYS; @@ -962,17 +1106,48 @@ int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, if (!ret) { if (lock.flags & _DRM_LOCK_QUIESCENT) { - printk("_DRM_LOCK_QUIESCENT\n"); - ret = mga_flush_queue(dev); - if(ret != 0) { - drm_lock_free(dev, &dev->lock.hw_lock->lock, - lock.context); - } else { - mga_dma_quiescent(dev); - } + DRM_DEBUG("_DRM_LOCK_QUIESCENT\n"); + mga_flush_queue(dev); + mga_dma_quiescent(dev); } } - printk("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); return ret; } +int mga_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_lock_t lock; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + int i; + + copy_from_user_ret(&lock, (drm_lock_t *)arg, sizeof(lock), -EFAULT); + + if(lock.flags & _DRM_LOCK_FLUSH || lock.flags & _DRM_LOCK_FLUSH_ALL) { + mga_flush_queue(dev); + if((MGA_READ(MGAREG_STATUS) & 0x00030001) == 0x00020000 && + status[1] != dev_priv->last_sync_tag) { + DRM_DEBUG("Reseting hardware status\n"); + MGA_WRITE(MGAREG_DWGSYNC, dev_priv->last_sync_tag); + while(MGA_READ(MGAREG_DWGSYNC) != dev_priv->last_sync_tag) { + for(i = 0; i < 4096; i++) mga_delay(); + } + status[1] = sarea_priv->last_dispatch = dev_priv->last_sync_tag; + } else { + sarea_priv->last_dispatch = status[1]; + } + } + if(lock.flags & _DRM_LOCK_QUIESCENT) { + mga_dma_quiescent(dev); + } + + return 0; +} diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.h index 7f1c57957..97d830054 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_dma.h @@ -2,30 +2,24 @@ #define MGA_DMA_H #include "mga_drm_public.h" +typedef enum { + TT_GENERAL, + TT_BLIT, + TT_VECTOR, + TT_VERTEX +} transferType_t; - -/* Isn't this fun. This has to be fixed asap by emitting primary - * dma commands in the 'do_dma' ioctl. - */ typedef struct { - int dma_type; - - unsigned int ContextState[MGA_CTX_SETUP_SIZE]; - unsigned int ServerState[MGA_2D_SETUP_SIZE]; - unsigned int TexState[2][MGA_TEX_SETUP_SIZE]; - unsigned int WarpPipe; - unsigned int dirty; - - unsigned int nbox; - xf86drmClipRectRec boxes[MGA_NR_SAREA_CLIPRECTS]; + drm_mga_freelist_t *my_freelist; } drm_mga_buf_priv_t; - -#define MGA_DMA_GENERAL 0 +#define MGA_DMA_GENERAL 0 /* not used */ #define MGA_DMA_VERTEX 1 #define MGA_DMA_SETUP 2 #define MGA_DMA_ILOAD 3 - +#define MGA_DMA_CLEAR 4 /* placeholder */ +#define MGA_DMA_SWAP 5 /* placeholder */ +#define MGA_DMA_DISCARD 6 #define DWGREG0 0x1c00 #define DWGREG0_END 0x1dff @@ -37,76 +31,102 @@ typedef struct { #define ADRINDEX1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) #define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r)) +#define MGA_VERBOSE 0 -/* Macros for inserting commands into a secondary dma buffer. +#define MGA_NUM_PRIM_BUFS 8 +/* Primary buffer versions of above -- pretty similar really. */ -#define DMALOCALS u8 tempIndex[4]; u32 *dma_ptr; \ - int outcount, num_dwords; +#define PRIMLOCALS u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \ + int outcount, num_dwords -#define DMAGETPTR(buf) do { \ - dma_ptr = (u32 *)((u8 *)buf->address + buf->used); \ - outcount = 0; \ - num_dwords = buf->used / 4; \ +#define PRIM_OVERFLOW(dev, dev_priv, length) do { \ +drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ +if( (tmp_buf->max_dwords - tmp_buf->num_dwords) < length || \ +tmp_buf->sec_used > (MGA_DMA_BUF_NR / 2)) { \ + atomic_set(&tmp_buf->force_fire, 1); \ + mga_advance_primary(dev); \ + mga_dma_schedule(dev, 1); \ + } else if( atomic_read(&tmp_buf->needs_overflow)) { \ + mga_advance_primary(dev); \ + mga_dma_schedule(dev, 1); \ +} \ } while(0) -#define DMAADVANCE(buf) do { \ - buf->used = num_dwords * 4; \ +#define PRIMGETPTR(dev_priv) do { \ +drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ +if(MGA_VERBOSE) \ +DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \ +dma_ptr = tmp_buf->current_dma_ptr; \ +num_dwords = tmp_buf->num_dwords; \ +phys_head = tmp_buf->phys_head; \ +outcount = 0; \ } while(0) -#define DMAOUTREG(reg, val) do { \ - tempIndex[outcount]=ADRINDEX(reg); \ - dma_ptr[++outcount] = val; \ - if (outcount == 4) { \ - outcount = 0; \ - dma_ptr[0] = *(u32 *)tempIndex; \ - dma_ptr+=5; \ - num_dwords += 5; \ - } \ -}while (0) - - - -#define VERBO 0 - +#define PRIMPTR(prim_buf) do { \ +if(MGA_VERBOSE) \ +DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \ +dma_ptr = prim_buf->current_dma_ptr; \ +num_dwords = prim_buf->num_dwords; \ +phys_head = prim_buf->phys_head; \ +outcount = 0; \ +} while(0) -/* Primary buffer versions of above -- pretty similar really. - */ -#define PRIMLOCALS u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \ - int outcount, num_dwords +#define PRIMFINISH(prim_buf) do { \ + if (MGA_VERBOSE) { \ + DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \ + if (outcount & 3) \ + DRM_DEBUG(" --- truncation\n"); \ + } \ + prim_buf->num_dwords = num_dwords; \ + prim_buf->current_dma_ptr = dma_ptr; \ +} while(0) -#define PRIMRESET(dev_priv) do { \ - dev_priv->prim_num_dwords = 0; \ - dev_priv->current_dma_ptr = dev_priv->prim_head; \ -} while (0) - -#define PRIMGETPTR(dev_priv) do { \ - dma_ptr = dev_priv->current_dma_ptr; \ - phys_head = dev_priv->prim_phys_head; \ - num_dwords = dev_priv->prim_num_dwords; \ - outcount = 0; \ +#define PRIMADVANCE(dev_priv) do { \ +drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + if (MGA_VERBOSE) { \ + DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \ + if (outcount & 3) \ + DRM_DEBUG(" --- truncation\n"); \ + } \ + tmp_buf->num_dwords = num_dwords; \ + tmp_buf->current_dma_ptr = dma_ptr; \ } while (0) -#define PRIMADVANCE(dev_priv) do { \ - dev_priv->prim_num_dwords = num_dwords; \ - dev_priv->current_dma_ptr = dma_ptr; \ +#define PRIMUPDATE(dev_priv) do { \ +drm_mga_prim_buf_t *tmp_buf = \ + dev_priv->prim_bufs[dev_priv->current_prim_idx]; \ + tmp_buf->sec_used++; \ } while (0) #define PRIMOUTREG(reg, val) do { \ tempIndex[outcount]=ADRINDEX(reg); \ dma_ptr[1+outcount] = val; \ + if (MGA_VERBOSE) \ + DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \ + num_dwords + 1 + outcount, ADRINDEX(reg), val); \ if( ++outcount == 4) { \ outcount = 0; \ dma_ptr[0] = *(u32 *)tempIndex; \ dma_ptr+=5; \ num_dwords += 5; \ } \ - if (VERBO) \ - printk(KERN_INFO \ - "OUT %x val %x dma_ptr %p nr_dwords %d\n", \ - outcount, ADRINDEX(reg), dma_ptr, \ - num_dwords); \ }while (0) +#define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \ + DC_sgnzero_enable | DC_shftzero_enable | \ + (0xC << DC_bop_SHIFT) | DC_clipdis_enable | \ + DC_solid_enable | DC_transc_enable) + + +#define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \ + DC_solid_disable | DC_arzero_disable | \ + DC_sgnzero_enable | DC_shftzero_enable | \ + (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \ + DC_pattern_disable | DC_transc_disable | \ + DC_clipdis_enable) \ #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drm_public.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drm_public.h index 8b21df11f..0e91656cd 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drm_public.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drm_public.h @@ -54,11 +54,9 @@ #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) - #define MGA_MAX_G400_PIPES 16 #define MGA_MAX_G200_PIPES 8 /* no multitex */ - #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES #define MGA_CARD_TYPE_G200 1 @@ -82,22 +80,18 @@ typedef struct drm_mga_init { int sarea_priv_offset; int primary_size; int warp_ucode_size; - int fbOffset; + int frontOffset; int backOffset; int depthOffset; int textureOffset; int textureSize; + int agpTextureOffset; + int agpTextureSize; int cpp; int stride; int sgram; int chipset; mgaWarpIndex WarpIndex[MGA_MAX_WARP_PIPES]; - - /* Redundant? - */ - int frontOrg; - int backOrg; - int depthOrg; int mAccess; } drm_mga_init_t; @@ -108,12 +102,12 @@ typedef struct _xf86drmClipRectRec { unsigned short y2; } xf86drmClipRectRec; -#define MGA_CLEAR_FRONT 0x1 -#define MGA_CLEAR_BACK 0x2 -#define MGA_CLEAR_DEPTH 0x4 +#define MGA_FRONT 0x1 +#define MGA_BACK 0x2 +#define MGA_DEPTH 0x4 -/* Each context has a state: +/* 3d state excluding texture units: */ #define MGA_CTXREG_DSTORG 0 /* validated */ #define MGA_CTXREG_MACCESS 1 @@ -124,7 +118,8 @@ typedef struct _xf86drmClipRectRec { #define MGA_CTXREG_WFLAG 6 #define MGA_CTXREG_TDUAL0 7 #define MGA_CTXREG_TDUAL1 8 -#define MGA_CTX_SETUP_SIZE 9 +#define MGA_CTXREG_FCOL 9 +#define MGA_CTX_SETUP_SIZE 10 /* 2d state */ @@ -146,33 +141,59 @@ typedef struct _xf86drmClipRectRec { #define MGA_TEXREG_HEIGHT 10 #define MGA_TEX_SETUP_SIZE 11 - /* What needs to be changed for the current vertex dma buffer? */ -#define MGASAREA_NEW_CONTEXT 0x1 -#define MGASAREA_NEW_TEX0 0x2 -#define MGASAREA_NEW_TEX1 0x4 -#define MGASAREA_NEW_PIPE 0x8 -#define MGASAREA_NEW_2D 0x10 +#define MGA_UPLOAD_CTX 0x1 +#define MGA_UPLOAD_TEX0 0x2 +#define MGA_UPLOAD_TEX1 0x4 +#define MGA_UPLOAD_PIPE 0x8 +#define MGA_UPLOAD_TEX0IMAGE 0x10 +#define MGA_UPLOAD_TEX1IMAGE 0x20 +#define MGA_UPLOAD_2D 0x40 +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ + + +/* 64 buffers of 16k each, total 1 meg. + */ +#define MGA_DMA_BUF_ORDER 14 +#define MGA_DMA_BUF_SZ (1<<MGA_DMA_BUF_ORDER) +#define MGA_DMA_BUF_NR 63 -/* Keep this small for testing +/* Keep these small for testing. */ -#define MGA_NR_SAREA_CLIPRECTS 2 +#define MGA_NR_SAREA_CLIPRECTS 8 + + -/* Upto 128 regions. Minimum region size of 256k. +/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 + * regions, subject to a minimum region size of (1<<16) == 64k. + * + * Clients may subdivide regions internally, but when sharing between + * clients, the region size is the minimum granularity. */ -#define MGA_NR_TEX_REGIONS 128 -#define MGA_MIN_LOG_TEX_GRANULARITY 18 +#define MGA_CARD_HEAP 0 +#define MGA_AGP_HEAP 1 +#define MGA_NR_TEX_HEAPS 2 +#define MGA_NR_TEX_REGIONS 16 +#define MGA_LOG_MIN_TEX_REGION_SIZE 16 typedef struct { - unsigned char next, prev; - unsigned char in_use; - int age; + unsigned char next, prev; + unsigned char in_use; + int age; } mgaTexRegion; + + typedef struct { + /* The channel for communication of state information to the kernel + * on firing a vertex dma buffer. + */ unsigned int ContextState[MGA_CTX_SETUP_SIZE]; unsigned int ServerState[MGA_2D_SETUP_SIZE]; unsigned int TexState[2][MGA_TEX_SETUP_SIZE]; @@ -182,37 +203,88 @@ typedef struct unsigned int nbox; xf86drmClipRectRec boxes[MGA_NR_SAREA_CLIPRECTS]; - /* kernel doesn't touch from here down */ + + /* Information about the most recently used 3d drawable. The + * client fills in the req_* fields, the server fills in the + * exported_ fields and puts the cliprects into boxes, above. + * + * The client clears the exported_drawable field before + * clobbering the boxes data. + */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ + + unsigned int exported_drawable; + unsigned int exported_index; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; + int exported_back_x, exported_front_x, exported_w; + int exported_back_y, exported_front_y, exported_h; + xf86drmClipRectRec exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + + /* Counters for aging textures and for client-side throttling. + */ + int last_enqueue; /* last time a buffer was enqueued */ + int last_dispatch; /* age of the most recently dispatched buffer */ + int last_quiescent; /* */ + + + /* LRU lists for texture memory in agp space and on the card + */ + mgaTexRegion texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; + unsigned int texAge[MGA_NR_TEX_HEAPS]; + + /* Mechanism to validate card state. + */ int ctxOwner; - mgaTexRegion texList[MGA_NR_TEX_REGIONS+1]; - int texAge; + + } drm_mga_sarea_t; /* Device specific ioctls: */ typedef struct { + int idx; int clear_color; int clear_depth; int flags; } drm_mga_clear_t; - typedef struct { - int flags; /* not actually used? */ + int idx; } drm_mga_swap_t; typedef struct { unsigned int destOrg; - unsigned int mAccess; - unsigned int pitch; - xf86drmClipRectRec texture; - int idx; + int idx; + int length; } drm_mga_iload_t; +/* These may be placeholders if we have more cliprects than + * MGA_NR_SAREA_CLIPRECTS. In that case, idx != real_idx; idx is + * the number of a bogus buffer, real_idx is the real buffer to be + * rendered multiple times. + * + * This is a hack to work around assumptions built into the drm, and + * may shortly be removed. + */ +typedef struct { + int idx; /* buffer to queue and free on completion */ + int real_idx; /* buffer to execute */ + int real_used; /* buf->used in for real buffer */ + int discard; /* */ +} drm_mga_vertex_t; + + #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) #define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t) #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t) #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t ) + #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.c index 8bc25617e..480413549 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.c @@ -54,6 +54,7 @@ static struct file_operations mga_fops = { mmap: drm_mmap, read: drm_read, fasync: drm_fasync, + poll: drm_poll, }; static struct miscdevice mga_misc = { @@ -105,9 +106,11 @@ static drm_ioctl_desc_t mga_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, [DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_clear_bufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_swap_bufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_iload, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_swap_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_clear_bufs, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_iload, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_vertex, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_flush_ioctl, 1, 0 }, }; #define MGA_IOCTL_COUNT DRM_ARRAY_SIZE(mga_ioctls) @@ -380,6 +383,21 @@ int mga_init(void) drm_proc_init(dev); DRM_DEBUG("doing agp init\n"); dev->agp = drm_agp_init(); + if(dev->agp == NULL) { + DRM_DEBUG("The mga drm module requires the agpgart module" + " to function correctly\nPlease load the agpgart" + " module before you load the mga module\n"); + drm_proc_cleanup(); + misc_deregister(&mga_misc); + mga_takedown(dev); + return -ENOMEM; + } +#ifdef CONFIG_MTRR + dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024 * 1024, + MTRR_TYPE_WRCOMB, + 1); +#endif DRM_DEBUG("doing ctxbitmap init\n"); if((retcode = drm_ctxbitmap_init(dev))) { DRM_ERROR("Cannot allocate memory for context bitmap.\n"); @@ -416,6 +434,16 @@ void mga_cleanup(void) } drm_ctxbitmap_cleanup(dev); mga_dma_cleanup(dev); +#ifdef CONFIG_MTRR + if(dev->agp && dev->agp->agp_mtrr) { + int retval; + retval = mtrr_del(dev->agp->agp_mtrr, + dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024*1024); + DRM_DEBUG("mtrr_del = %d\n", retval); + } +#endif + mga_takedown(dev); if (dev->agp) { drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.h index bc7808b0a..60c00f93b 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.h @@ -24,7 +24,7 @@ * DEALINGS IN THE SOFTWARE. * * Authors: Rickard E. (Rik) Faith <faith@precisioninsight.com> - * Jeff Hartmann <jhartmann@precisioninsight.com> + * Jeff Hartmann <jhartmann@precisioninsight.com> * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_drv.h,v 1.1 2000/02/11 17:26:08 dawes Exp $ */ @@ -33,6 +33,27 @@ #define _MGA_DRV_H_ #include "mga_drm_public.h" +typedef struct { + unsigned int num_dwords; + unsigned int max_dwords; + u32 *current_dma_ptr; + u32 *head; + u32 phys_head; + int sec_used; + int idx; + int swap_pending; + u32 in_use; + atomic_t force_fire; + atomic_t needs_overflow; +} drm_mga_prim_buf_t; + +typedef struct _drm_mga_freelist { + unsigned int age; + drm_buf_t *buf; + struct _drm_mga_freelist *next; + struct _drm_mga_freelist *prev; +} drm_mga_freelist_t; + typedef struct _drm_mga_private { int reserved_map_idx; int buffer_map_idx; @@ -40,7 +61,7 @@ typedef struct _drm_mga_private { int primary_size; int warp_ucode_size; int chipset; - int fbOffset; + int frontOffset; int backOffset; int depthOffset; int textureOffset; @@ -50,24 +71,31 @@ typedef struct _drm_mga_private { int sgram; int use_agp; mgaWarpIndex WarpIndex[MGA_MAX_G400_PIPES]; + unsigned int WarpPipe; __volatile__ unsigned long softrap_age; - atomic_t dispatch_lock; + u32 dispatch_lock; + atomic_t in_flush; + atomic_t in_wait; atomic_t pending_bufs; - void *ioremap; - u32 *prim_head; - u32 *current_dma_ptr; - u32 prim_phys_head; - int prim_num_dwords; - int prim_max_dwords; - + unsigned int last_sync_tag; + unsigned int sync_tag; + void *status_page; + unsigned long real_status_page; + u8 *ioremap; + drm_mga_prim_buf_t **prim_bufs; + drm_mga_prim_buf_t *next_prim; + drm_mga_prim_buf_t *last_prim; + drm_mga_prim_buf_t *current_prim; + int current_prim_idx; + struct pci_dev *device; + drm_mga_freelist_t *head; + drm_mga_freelist_t *tail; + wait_queue_head_t flush_queue; /* Processes waiting until flush */ + wait_queue_head_t wait_queue; /* Processes waiting until interrupt */ /* Some validated register values: */ - u32 frontOrg; - u32 backOrg; - u32 depthOrg; u32 mAccess; - } drm_mga_private_t; /* mga_drv.c */ @@ -92,16 +120,18 @@ extern int mga_control(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_lock(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -#if 0 -extern void mga_dma_init(drm_device_t *dev); -extern void mga_dma_cleanup(drm_device_t *dev); -#endif +/* mga_dma_init does init and release */ extern int mga_dma_init(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_dma_cleanup(drm_device_t *dev); +extern int mga_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); -/* mga_dma_init does init and release */ +extern unsigned int mga_create_sync_tag(drm_device_t *dev); +extern drm_buf_t *mga_freelist_get(drm_device_t *dev); +extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf); +extern int mga_advance_primary(drm_device_t *dev); /* mga_bufs.c */ @@ -124,6 +154,8 @@ extern int mga_swap_bufs(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); extern int mga_iload(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); +extern int mga_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* mga_context.c */ extern int mga_resctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.c index d09881bad..941ca4d00 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.c @@ -24,7 +24,7 @@ * DEALINGS IN THE SOFTWARE. * * Authors: Jeff Hartmann <jhartmann@precisioninsight.com> - * Keith Whitwell <keithw@precisioninsight.com> + * Keith Whitwell <keithw@precisioninsight.com> * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.c,v 1.1 2000/02/11 17:26:08 dawes Exp $ * @@ -35,180 +35,209 @@ #include "mga_drv.h" #include "mgareg_flags.h" #include "mga_dma.h" -#include "mga_state.h" #include "drm.h" -void mgaEmitClipRect( drm_mga_private_t *dev_priv, xf86drmClipRectRec *box ) +static void mgaEmitClipRect( drm_mga_private_t *dev_priv, xf86drmClipRectRec *box ) { + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; PRIMLOCALS; + /* This takes 10 dwords */ PRIMGETPTR( dev_priv ); + + /* Force reset of dwgctl (eliminates clip disable) */ + PRIMOUTREG( MGAREG_DMAPAD, 0 ); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 ); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag - 1 ); + PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] ); - /* The G400 seems to have an issue with the second WARP not - * stalling clipper register writes. This bothers me, but the only - * way I could get it to never clip the last triangle under any - * circumstances is by inserting TWO dwgsync commands. - */ - if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - PRIMOUTREG( MGAREG_DWGSYNC, 0 ); - PRIMOUTREG( MGAREG_DWGSYNC, 0 ); - } - + PRIMOUTREG( MGAREG_DMAPAD, 0 ); PRIMOUTREG( MGAREG_CXBNDRY, ((box->x2)<<16)|(box->x1) ); - PRIMOUTREG( MGAREG_YTOP, box->y1 * dev_priv->stride ); - PRIMOUTREG( MGAREG_YBOT, box->y2 * dev_priv->stride ); + PRIMOUTREG( MGAREG_YTOP, box->y1 * dev_priv->stride/2 ); + PRIMOUTREG( MGAREG_YBOT, box->y2 * dev_priv->stride/2 ); + PRIMADVANCE( dev_priv ); } - -static void mgaEmitContext(drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv) +static void mgaEmitContext(drm_mga_private_t *dev_priv ) { - unsigned int *regs = buf_priv->ContextState; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; PRIMLOCALS; + /* This takes a max of 15 dwords */ PRIMGETPTR( dev_priv ); + PRIMOUTREG( MGAREG_DSTORG, regs[MGA_CTXREG_DSTORG] ); PRIMOUTREG( MGAREG_MACCESS, regs[MGA_CTXREG_MACCESS] ); PRIMOUTREG( MGAREG_PLNWT, regs[MGA_CTXREG_PLNWT] ); PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] ); + PRIMOUTREG( MGAREG_ALPHACTRL, regs[MGA_CTXREG_ALPHACTRL] ); PRIMOUTREG( MGAREG_FOGCOL, regs[MGA_CTXREG_FOGCOLOR] ); PRIMOUTREG( MGAREG_WFLAG, regs[MGA_CTXREG_WFLAG] ); + PRIMOUTREG( MGAREG_ZORG, dev_priv->depthOffset ); /* invarient */ if (dev_priv->chipset == MGA_CARD_TYPE_G400) { PRIMOUTREG( MGAREG_WFLAG1, regs[MGA_CTXREG_WFLAG] ); PRIMOUTREG( MGAREG_TDUALSTAGE0, regs[MGA_CTXREG_TDUAL0] ); PRIMOUTREG( MGAREG_TDUALSTAGE1, regs[MGA_CTXREG_TDUAL1] ); - } + PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] ); + } else { + PRIMOUTREG( MGAREG_FCOL, regs[MGA_CTXREG_FCOL] ); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + } PRIMADVANCE( dev_priv ); } -static void mgaG200EmitTex( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ) +static void mgaG200EmitTex( drm_mga_private_t *dev_priv ) { - unsigned int *regs = buf_priv->TexState[0]; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->TexState[0]; PRIMLOCALS; PRIMGETPTR( dev_priv ); + + /* This takes 20 dwords */ + PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] ); PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] ); PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] ); PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] ); + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] ); PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] ); PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] ); PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] ); + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] ); PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] ); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); - + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); PRIMOUTREG(0x2d00 + 24*4, regs[MGA_TEXREG_WIDTH] ); + PRIMOUTREG(0x2d00 + 34*4, regs[MGA_TEXREG_HEIGHT] ); + PRIMOUTREG( MGAREG_TEXTRANS, 0xffff ); + PRIMOUTREG( MGAREG_TEXTRANSHIGH, 0xffff ); + PRIMOUTREG( MGAREG_DMAPAD, 0 ); PRIMADVANCE( dev_priv ); } -static void mgaG400EmitTex0( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ) +static void mgaG400EmitTex0( drm_mga_private_t *dev_priv ) { - unsigned int *regs = buf_priv->TexState[0]; - int multitex = buf_priv->WarpPipe & MGA_T2; - + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->TexState[0]; + int multitex = sarea_priv->WarpPipe & MGA_T2; PRIMLOCALS; + PRIMGETPTR( dev_priv ); + + /* This takes a max of 30 dwords */ PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] ); PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] ); PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] ); PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] ); + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] ); PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] ); PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] ); PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] ); + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] ); PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] ); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); - + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); PRIMOUTREG(0x2d00 + 49*4, 0); + PRIMOUTREG(0x2d00 + 57*4, 0); PRIMOUTREG(0x2d00 + 53*4, 0); PRIMOUTREG(0x2d00 + 61*4, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0 ); if (!multitex) { PRIMOUTREG(0x2d00 + 52*4, 0x40 ); PRIMOUTREG(0x2d00 + 60*4, 0x40 ); + PRIMOUTREG( MGAREG_DMAPAD, 0 ); + PRIMOUTREG( MGAREG_DMAPAD, 0 ); } - PRIMOUTREG(0x2d00 + 54*4, regs[MGA_TEXREG_WIDTH] | 0x40 ); - PRIMOUTREG(0x2d00 + 62*4, regs[MGA_TEXREG_HEIGHT] | 0x40 ); + PRIMOUTREG( 0x2d00 + 54*4, regs[MGA_TEXREG_WIDTH] | 0x40 ); + PRIMOUTREG( 0x2d00 + 62*4, regs[MGA_TEXREG_HEIGHT] | 0x40 ); + PRIMOUTREG( MGAREG_TEXTRANS, 0xffff ); + PRIMOUTREG( MGAREG_TEXTRANSHIGH, 0xffff ); PRIMADVANCE( dev_priv ); } #define TMC_map1_enable 0x80000000 - -static void mgaG400EmitTex1( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ) +static void mgaG400EmitTex1( drm_mga_private_t *dev_priv ) { - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int *regs = sarea_priv->TexState[1]; - PRIMLOCALS; + PRIMGETPTR(dev_priv); + /* This takes 25 dwords */ PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] | TMC_map1_enable); PRIMOUTREG(MGAREG_TEXCTL, regs[MGA_TEXREG_CTL] ); PRIMOUTREG(MGAREG_TEXFILTER, regs[MGA_TEXREG_FILTER] ); PRIMOUTREG(MGAREG_TEXBORDERCOL, regs[MGA_TEXREG_BORDERCOL] ); + PRIMOUTREG(MGAREG_TEXORG, regs[MGA_TEXREG_ORG] ); PRIMOUTREG(MGAREG_TEXORG1, regs[MGA_TEXREG_ORG1] ); PRIMOUTREG(MGAREG_TEXORG2, regs[MGA_TEXREG_ORG2] ); PRIMOUTREG(MGAREG_TEXORG3, regs[MGA_TEXREG_ORG3] ); + PRIMOUTREG(MGAREG_TEXORG4, regs[MGA_TEXREG_ORG4] ); PRIMOUTREG(MGAREG_TEXWIDTH, regs[MGA_TEXREG_WIDTH] ); - PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); - + PRIMOUTREG(MGAREG_TEXHEIGHT, regs[MGA_TEXREG_HEIGHT] ); PRIMOUTREG(0x2d00 + 49*4, 0); + PRIMOUTREG(0x2d00 + 57*4, 0); PRIMOUTREG(0x2d00 + 53*4, 0); PRIMOUTREG(0x2d00 + 61*4, 0); - PRIMOUTREG(0x2d00 + 52*4, regs[MGA_TEXREG_WIDTH] | 0x40 ); - PRIMOUTREG(0x2d00 + 60*4, regs[MGA_TEXREG_HEIGHT] | 0x40 ); + PRIMOUTREG(0x2d00 + 60*4, regs[MGA_TEXREG_HEIGHT] | 0x40 ); + PRIMOUTREG( MGAREG_TEXTRANS, 0xffff ); + PRIMOUTREG( MGAREG_TEXTRANSHIGH, 0xffff ); PRIMOUTREG(MGAREG_TEXCTL2, regs[MGA_TEXREG_CTL2] ); - PRIMADVANCE( dev_priv ); + PRIMADVANCE( dev_priv ); } - -static void mgaG400EmitPipe(drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv) +static void mgaG400EmitPipe(drm_mga_private_t *dev_priv ) { - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->WarpPipe; float fParam = 12800.0f; PRIMLOCALS; PRIMGETPTR(dev_priv); - PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); + + /* This takes 25 dwords */ /* Establish vertex size. */ if (pipe & MGA_T2) { + PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001e09); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x1e000000); + PRIMOUTREG(MGAREG_WFLAG, 0); } else { + PRIMOUTREG(MGAREG_WIADDR2, WIA_wmode_suspend); PRIMOUTREG(MGAREG_WVRTXSZ, 0x00001807); PRIMOUTREG(MGAREG_WACCEPTSEQ, 0x18000000); - } - - PRIMOUTREG(MGAREG_WFLAG, 0); - PRIMOUTREG(MGAREG_WFLAG1, 0); - + PRIMOUTREG(MGAREG_WFLAG, 0); + } + + PRIMOUTREG(MGAREG_WFLAG1, 0); PRIMOUTREG(0x2d00 + 56*4, *((u32 *)(&fParam))); PRIMOUTREG(MGAREG_DMAPAD, 0); PRIMOUTREG(MGAREG_DMAPAD, 0); @@ -227,19 +256,21 @@ static void mgaG400EmitPipe(drm_mga_private_t *dev_priv, PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_WIADDR2, (dev_priv->WarpIndex[pipe].phys_addr | - WIA_wmode_start | WIA_wagp_agp)); + PRIMOUTREG(MGAREG_WIADDR2, (__u32)(dev_priv->WarpIndex[pipe].phys_addr | + WIA_wmode_start | WIA_wagp_agp)); PRIMADVANCE(dev_priv); } -static void mgaG200EmitPipe( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ) +static void mgaG200EmitPipe( drm_mga_private_t *dev_priv ) { - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->WarpPipe; PRIMLOCALS; PRIMGETPTR(dev_priv); + + /* This takes 15 dwords */ + PRIMOUTREG(MGAREG_WIADDR, WIA_wmode_suspend); PRIMOUTREG(MGAREG_WVRTXSZ, 7); PRIMOUTREG(MGAREG_WFLAG, 0); @@ -254,109 +285,640 @@ static void mgaG200EmitPipe( drm_mga_private_t *dev_priv, PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); PRIMOUTREG(MGAREG_DMAPAD, 0xffffffff); - PRIMOUTREG(MGAREG_WIADDR, (dev_priv->WarpIndex[pipe].phys_addr | - WIA_wmode_start | WIA_wagp_agp)); + PRIMOUTREG(MGAREG_WIADDR, (__u32)(dev_priv->WarpIndex[pipe].phys_addr | + WIA_wmode_start | WIA_wagp_agp)); PRIMADVANCE(dev_priv); } -void mgaEmitState( drm_mga_private_t *dev_priv, drm_mga_buf_priv_t *buf_priv ) +static void mgaEmitState( drm_mga_private_t *dev_priv ) { - unsigned int dirty = buf_priv->dirty; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int dirty = sarea_priv->dirty; if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - if (dirty & MGASAREA_NEW_CONTEXT) - mgaEmitContext( dev_priv, buf_priv ); - - if (dirty & MGASAREA_NEW_TEX1) - mgaG400EmitTex1( dev_priv, buf_priv ); - - if (dirty & MGASAREA_NEW_TEX0) - mgaG400EmitTex0( dev_priv, buf_priv ); - - if (dirty & MGASAREA_NEW_PIPE) - mgaG400EmitPipe( dev_priv, buf_priv ); + int multitex = sarea_priv->WarpPipe & MGA_T2; + +/* DRM_DEBUG("BUF PIPE: %x LOADED PIPE: %x\n", */ +/* sarea_priv->WarpPipe, dev_priv->WarpPipe); */ + + if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { + mgaG400EmitPipe( dev_priv ); + dev_priv->WarpPipe = sarea_priv->WarpPipe; + } + + if (dirty & MGA_UPLOAD_CTX) { + mgaEmitContext( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CTX; + } + + if (dirty & MGA_UPLOAD_TEX0) { + mgaG400EmitTex0( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } + + if ((dirty & MGA_UPLOAD_TEX1) && multitex) { + mgaG400EmitTex1( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; + } } else { - if (dirty & MGASAREA_NEW_CONTEXT) - mgaEmitContext( dev_priv, buf_priv ); - - if (dirty & MGASAREA_NEW_TEX0) - mgaG200EmitTex( dev_priv, buf_priv ); - - if (dirty & MGASAREA_NEW_PIPE) - mgaG200EmitPipe( dev_priv, buf_priv ); - } + if (sarea_priv->WarpPipe != dev_priv->WarpPipe) { + mgaG200EmitPipe( dev_priv ); + dev_priv->WarpPipe = sarea_priv->WarpPipe; + } + + if (dirty & MGA_UPLOAD_CTX) { + mgaEmitContext( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_CTX; + } + + if (dirty & MGA_UPLOAD_TEX0) { + mgaG200EmitTex( dev_priv ); + sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; + } + } } +/* WARNING if you change any of the state functions + * verify these numbers */ +static int mgaCalcState( drm_mga_private_t *dev_priv ) +{ + /* It doesn't hurt to overestimate. + */ + return 25+15+30+25; +} /* Disallow all write destinations except the front and backbuffer. */ -static int mgaCopyContext(drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv) +static int mgaVerifyContext(drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int *regs = sarea_priv->ContextState; - - if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOrg && - regs[MGA_CTXREG_DSTORG] != dev_priv->backOrg) + + if (regs[MGA_CTXREG_DSTORG] != dev_priv->frontOffset && + regs[MGA_CTXREG_DSTORG] != dev_priv->backOffset) { + DRM_DEBUG("BAD DSTORG: %x (front %x, back %x)\n\n", + regs[MGA_CTXREG_DSTORG], dev_priv->frontOffset, + dev_priv->backOffset); + regs[MGA_CTXREG_DSTORG] = 0; return -1; + } - memcpy(buf_priv->ContextState, sarea_priv->ContextState, - sizeof(buf_priv->ContextState)); return 0; } - /* Disallow texture reads from PCI space. */ -static int mgaCopyTex(drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv, +static int mgaVerifyTex(drm_mga_private_t *dev_priv, int unit) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) + if ((sarea_priv->TexState[unit][MGA_TEXREG_ORG] & 0x3) == 0x1) { + DRM_DEBUG("BAD TEXREG_ORG: %x, unit %d\n", + sarea_priv->TexState[unit][MGA_TEXREG_ORG], + unit); + sarea_priv->TexState[unit][MGA_TEXREG_ORG] = 0; return -1; - - memcpy(buf_priv->TexState[unit], sarea_priv->TexState[unit], - sizeof(buf_priv->TexState[0])); + } return 0; } - -int mgaCopyAndVerifyState( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ) +static int mgaVerifyState( drm_mga_private_t *dev_priv ) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty ; + unsigned int dirty = sarea_priv->dirty; int rv = 0; - buf_priv->dirty = sarea_priv->dirty; - buf_priv->WarpPipe = sarea_priv->WarpPipe; + if (sarea_priv->nbox >= MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if (dirty & MGASAREA_NEW_CONTEXT) - rv |= mgaCopyContext( dev_priv, buf_priv ); + if (dirty & MGA_UPLOAD_CTX) + rv |= mgaVerifyContext( dev_priv ); - if (dirty & MGASAREA_NEW_TEX0) - rv |= mgaCopyTex( dev_priv, buf_priv, 0 ); + if (dirty & MGA_UPLOAD_TEX0) + rv |= mgaVerifyTex( dev_priv, 0 ); if (dev_priv->chipset == MGA_CARD_TYPE_G400) { - if (dirty & MGASAREA_NEW_TEX1) - rv |= mgaCopyTex( dev_priv, buf_priv, 1 ); + if (dirty & MGA_UPLOAD_TEX1) + rv |= mgaVerifyTex( dev_priv, 1 ); - if (dirty & MGASAREA_NEW_PIPE) - rv |= (buf_priv->WarpPipe > MGA_MAX_G400_PIPES); + if (dirty & MGA_UPLOAD_PIPE) + rv |= (sarea_priv->WarpPipe > MGA_MAX_G400_PIPES); } else { - if (dirty & MGASAREA_NEW_PIPE) - rv |= (buf_priv->WarpPipe > MGA_MAX_G200_PIPES); + if (dirty & MGA_UPLOAD_PIPE) + rv |= (sarea_priv->WarpPipe > MGA_MAX_G200_PIPES); } return rv == 0; } +static int mgaVerifyIload( drm_mga_private_t *dev_priv, + unsigned long bus_address, + unsigned int dstOrg, int length ) +{ + if(dstOrg < dev_priv->textureOffset || + dstOrg + length > + (dev_priv->textureOffset + dev_priv->textureSize)) { + return -EINVAL; + } + if(length % 64) { + return -EINVAL; + } + return 0; +} + +/* This copies a 64 byte aligned agp region to the frambuffer + * with a standard blit, the ioctl needs to do checking */ + +static inline void mga_dma_dispatch_tex_blit( drm_device_t *dev, + unsigned long bus_address, + int length, + unsigned int destOrg ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + int use_agp = PDEA_pagpxfer_enable | 0x00000001; + u16 y2; + PRIMLOCALS; + + y2 = length / 64; + + PRIM_OVERFLOW(dev, dev_priv, 30); + PRIMGETPTR( dev_priv ); + + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + + PRIMOUTREG( MGAREG_DSTORG, destOrg); + PRIMOUTREG( MGAREG_MACCESS, 0x00000000); + DRM_DEBUG("srcorg : %lx\n", bus_address | use_agp); + PRIMOUTREG( MGAREG_SRCORG, (u32) bus_address | use_agp); + PRIMOUTREG( MGAREG_AR5, 64); + + PRIMOUTREG( MGAREG_PITCH, 64); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGCTL, MGA_COPY_CMD); + + PRIMOUTREG(MGAREG_AR0, 63); + PRIMOUTREG(MGAREG_AR3, 0); + PRIMOUTREG(MGAREG_FXBNDRY, (63 << 16)); + PRIMOUTREG(MGAREG_YDSTLEN+MGAREG_MGA_EXEC, y2); + + PRIMOUTREG( MGAREG_SRCORG, 0); + PRIMOUTREG( MGAREG_PITCH, dev_priv->stride / dev_priv->cpp); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMADVANCE(dev_priv); +} +static inline void mga_dma_dispatch_vertex(drm_device_t *dev, + drm_buf_t *buf, int real_idx, + int idx) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned long address = (unsigned long)buf->bus_address; + int length = buf->used; + int use_agp = PDEA_pagpxfer_enable; + int i = 0; + int primary_needed; + PRIMLOCALS; + + DRM_DEBUG("dispatch vertex %d addr 0x%lx, length 0x%x nbox %d dirty %x\n", + buf->idx, address, length, sarea_priv->nbox, sarea_priv->dirty); + + + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + if(real_idx == idx) { + buf_priv->my_freelist->age = dev_priv->last_sync_tag; + mga_freelist_put(dev, buf); + } + + /* Overestimating this doesn't hurt. + */ + primary_needed = (25+15+30+25+ + 10 + + 15 * MGA_NR_SAREA_CLIPRECTS); + + + PRIM_OVERFLOW(dev, dev_priv, primary_needed); + mgaEmitState( dev_priv ); + do { + if (i < sarea_priv->nbox) { + DRM_DEBUG("idx %d Emit box %d/%d:" + "%d,%d - %d,%d\n", + buf->idx, + i, sarea_priv->nbox, + sarea_priv->boxes[i].x1, + sarea_priv->boxes[i].y1, + sarea_priv->boxes[i].x2, + sarea_priv->boxes[i].y2); + + mgaEmitClipRect( dev_priv, + &sarea_priv->boxes[i] ); + } + + PRIMGETPTR(dev_priv); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_SECADDRESS, + ((__u32)address) | TT_VERTEX); + PRIMOUTREG( MGAREG_SECEND, + (((__u32)(address + length)) | + use_agp)); + PRIMADVANCE( dev_priv ); + } while (++i < sarea_priv->nbox); + + PRIMGETPTR( dev_priv ); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMADVANCE( dev_priv ); +} + +/* Not currently used + */ +static inline void mga_dma_dispatch_general(drm_device_t *dev, drm_buf_t *buf) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_buf_priv_t *buf_priv = buf->dev_private; + unsigned long address = (unsigned long)buf->bus_address; + int length = buf->used; + int use_agp = PDEA_pagpxfer_enable; + PRIMLOCALS; + + PRIM_OVERFLOW(dev, dev_priv, 10); + PRIMGETPTR(dev_priv); + + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + buf_priv->my_freelist->age = dev_priv->last_sync_tag; + mga_freelist_put(dev, buf); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_SECADDRESS, ((__u32)address) | TT_GENERAL); + PRIMOUTREG( MGAREG_SECEND, (((__u32)(address + length)) | use_agp)); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMADVANCE(dev_priv); +} + +static inline void mga_dma_dispatch_clear( drm_device_t *dev, int flags, + unsigned int clear_color, + unsigned int clear_zval ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + int nbox = sarea_priv->nbox; + xf86drmClipRectRec *pbox = sarea_priv->boxes; + unsigned int cmd; + int i; + int primary_needed; + PRIMLOCALS; + + if ( dev_priv->sgram ) + cmd = MGA_CLEAR_CMD | DC_atype_blk; + else + cmd = MGA_CLEAR_CMD | DC_atype_rstr; + + primary_needed = nbox * 70; + if(primary_needed == 0) primary_needed = 70; + PRIM_OVERFLOW(dev, dev_priv, primary_needed); + PRIMGETPTR( dev_priv ); + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + + for (i = 0 ; i < nbox ; i++) { + unsigned int height = pbox[i].y2 - pbox[i].y1; + + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags %x!\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, + pbox[i].y2, flags); + + if ( flags & MGA_FRONT ) { + DRM_DEBUG("clear front\n"); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height); + PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_color); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); + PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd ); + } + + if ( flags & MGA_BACK ) { + DRM_DEBUG("clear back\n"); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height); + PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_color); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->backOffset); + PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd ); + } + + if ( flags & MGA_DEPTH ) { + DRM_DEBUG("clear depth\n"); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_YDSTLEN, (pbox[i].y1<<16)|height); + PRIMOUTREG(MGAREG_FXBNDRY, (pbox[i].x2<<16)|pbox[i].x1); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_FCOL, clear_zval); + PRIMOUTREG(MGAREG_DSTORG, dev_priv->depthOffset); + PRIMOUTREG(MGAREG_DWGCTL+MGAREG_MGA_EXEC, cmd ); + } + } + + /* Force reset of DWGCTL */ + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] ); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMADVANCE(dev_priv); +} + +static inline void mga_dma_dispatch_swap( drm_device_t *dev ) +{ + drm_mga_private_t *dev_priv = dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + unsigned int *regs = sarea_priv->ContextState; + int nbox = sarea_priv->nbox; + xf86drmClipRectRec *pbox = sarea_priv->boxes; + int i; + int primary_needed; + PRIMLOCALS; + + primary_needed = nbox * 5; + primary_needed += 60; + PRIM_OVERFLOW(dev, dev_priv, primary_needed); + PRIMGETPTR( dev_priv ); + + dev_priv->last_sync_tag = mga_create_sync_tag(dev); + + PRIMOUTREG(MGAREG_DSTORG, dev_priv->frontOffset); + PRIMOUTREG(MGAREG_MACCESS, dev_priv->mAccess); + PRIMOUTREG(MGAREG_SRCORG, dev_priv->backOffset); + PRIMOUTREG(MGAREG_AR5, dev_priv->stride/2); + + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG(MGAREG_DWGCTL, MGA_COPY_CMD); + + for (i = 0 ; i < nbox; i++) { + unsigned int h = pbox[i].y2 - pbox[i].y1; + unsigned int start = pbox[i].y1 * dev_priv->stride/2; + + DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", + pbox[i].x1, pbox[i].y1, + pbox[i].x2, pbox[i].y2); + + PRIMOUTREG(MGAREG_AR0, start + pbox[i].x2 - 1); + PRIMOUTREG(MGAREG_AR3, start + pbox[i].x1); + PRIMOUTREG(MGAREG_FXBNDRY, pbox[i].x1|((pbox[i].x2 - 1)<<16)); + PRIMOUTREG(MGAREG_YDSTLEN+MGAREG_MGA_EXEC, (pbox[i].y1<<16)|h); + } + + /* Force reset of DWGCTL */ + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGCTL, regs[MGA_CTXREG_DWGCTL] ); + + PRIMOUTREG( MGAREG_SRCORG, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DMAPAD, 0); + PRIMOUTREG( MGAREG_DWGSYNC, dev_priv->last_sync_tag); + PRIMADVANCE(dev_priv); +} + +int mga_clear_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + + drm_mga_clear_t clear; + + copy_from_user_ret(&clear, (drm_mga_clear_t *)arg, sizeof(clear), + -EFAULT); + + if (sarea_priv->nbox >= MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; + mga_dma_dispatch_clear( dev, clear.flags, + clear.clear_color, + clear.clear_depth ); + PRIMUPDATE(dev_priv); + mga_dma_schedule(dev, 1); + sarea_priv->last_dispatch = status[1]; + return 0; +} + +int mga_swap_bufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + + if (sarea_priv->nbox >= MGA_NR_SAREA_CLIPRECTS) + sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; + + /* Make sure we restore the 3D state next time. + */ + dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CTX; + mga_dma_dispatch_swap( dev ); + PRIMUPDATE(dev_priv); + set_bit(0, &dev_priv->current_prim->swap_pending); + dev_priv->current_prim->swap_pending = 1; + mga_dma_schedule(dev, 1); + sarea_priv->last_dispatch = status[1]; + return 0; +} + +int mga_iload(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_iload_t iload; + unsigned long bus_address; + + DRM_DEBUG("Starting Iload\n"); + copy_from_user_ret(&iload, (drm_mga_iload_t *)arg, sizeof(iload), + -EFAULT); + + buf = dma->buflist[ iload.idx ]; + buf_priv = buf->dev_private; + bus_address = buf->bus_address; + DRM_DEBUG("bus_address %lx, length %d, destorg : %x\n", + bus_address, iload.length, iload.destOrg); + + if(mgaVerifyIload(dev_priv, + bus_address, + iload.destOrg, + iload.length)) { + mga_freelist_put(dev, buf); + return -EINVAL; + } + + sarea_priv->dirty |= MGA_UPLOAD_CTX; + + mga_dma_dispatch_tex_blit(dev, bus_address, iload.length, + iload.destOrg); + buf_priv->my_freelist->age = dev_priv->last_sync_tag; + mga_freelist_put(dev, buf); + mga_dma_schedule(dev, 1); + sarea_priv->last_dispatch = status[1]; + return 0; +} + +int mga_vertex(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf; + drm_mga_buf_priv_t *buf_priv; + drm_mga_vertex_t vertex; + + copy_from_user_ret(&vertex, (drm_mga_vertex_t *)arg, sizeof(vertex), + -EFAULT); + + + DRM_DEBUG("mga_vertex\n"); + buf = dma->buflist[ vertex.real_idx ]; + buf_priv = buf->dev_private; + + if (!mgaVerifyState(dev_priv)) { + if(vertex.real_idx == vertex.idx) { + buf_priv->my_freelist->age = dev_priv->last_sync_tag; + mga_freelist_put(dev, buf); + } + return -EINVAL; + } + + buf->used = vertex.real_used; + if(vertex.discard) { + buf_priv->my_freelist->age = dev_priv->last_sync_tag; + mga_freelist_put(dev, buf); + } else { + mga_dma_dispatch_vertex(dev, buf, vertex.real_idx, + vertex.idx); + } + PRIMUPDATE(dev_priv); + mga_dma_schedule(dev, 1); + sarea_priv->last_dispatch = status[1]; + return 0; +} + +static int mga_dma_get_buffers(drm_device_t *dev, drm_dma_t *d) +{ + int i; + drm_buf_t *buf; + + for (i = d->granted_count; i < d->request_count; i++) { + buf = mga_freelist_get(dev); + if (!buf) break; + buf->pid = current->pid; + copy_to_user_ret(&d->request_indices[i], + &buf->idx, + sizeof(buf->idx), + -EFAULT); + copy_to_user_ret(&d->request_sizes[i], + &buf->total, + sizeof(buf->total), + -EFAULT); + ++d->granted_count; + } + return 0; +} + +int mga_dma(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_device_dma_t *dma = dev->dma; + drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; + __volatile__ unsigned int *status = + (__volatile__ unsigned int *)dev_priv->status_page; + int retcode = 0; + drm_dma_t d; + + copy_from_user_ret(&d, (drm_dma_t *)arg, sizeof(d), -EFAULT); + DRM_DEBUG("%d %d: %d send, %d req\n", + current->pid, d.context, d.send_count, d.request_count); + + /* Please don't send us buffers. + */ + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + current->pid, d.send_count); + return -EINVAL; + } + + /* We'll send you buffers. + */ + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + current->pid, d.request_count, dma->buf_count); + return -EINVAL; + } + + d.granted_count = 0; + + if (d.request_count) { + retcode = mga_dma_get_buffers(dev, &d); + } + + DRM_DEBUG("%d returning, granted = %d\n", + current->pid, d.granted_count); + copy_to_user_ret((drm_dma_t *)arg, &d, sizeof(d), -EFAULT); + sarea_priv->last_dispatch = status[1]; + return retcode; +} diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.h index e7b952e0c..40fa14512 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/mga_state.h @@ -3,9 +3,6 @@ #include "mga_drv.h" -int mgaCopyAndVerifyState( drm_mga_private_t *dev_priv, - drm_mga_buf_priv_t *buf_priv ); - void mgaEmitClipRect( drm_mga_private_t *dev_priv, xf86drmClipRectRec *box ); void mgaEmitState( drm_mga_private_t *dev_priv, drm_mga_buf_priv_t *buf_priv ); diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/picker.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/picker.c index ecdb2c15a..0bd8bfd57 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/picker.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/picker.c @@ -9,6 +9,16 @@ #define CONFIG_MODVERSIONS 0 #endif +#ifndef CONFIG_AGP_MODULE +#define CONFIG_AGP_MODULE 0 +#endif + +#ifndef CONFIG_AGP +#define CONFIG_AGP 0 +#endif + SMP = CONFIG_SMP MODVERSIONS = CONFIG_MODVERSIONS +AGP = CONFIG_AGP +AGP_MODULE = CONFIG_AGP_MODULE RELEASE = UTS_RELEASE diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/proc.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/proc.c index 54aba58c4..db98fd6a4 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/proc.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/proc.c @@ -164,7 +164,10 @@ static int _drm_vm_info(char *buf, char **start, off_t offset, int len, { drm_device_t *dev = (drm_device_t *)data; drm_map_t *map; - const char *types[] = { "FB", "REG", "SHM" }; + /* Hardcoded from _DRM_FRAME_BUFFER, + _DRM_REGISTERS, _DRM_SHM, and + _DRM_AGP. */ + const char *types[] = { "FB", "REG", "SHM", "AGP" }; const char *type; int i; @@ -175,7 +178,7 @@ static int _drm_vm_info(char *buf, char **start, off_t offset, int len, "address mtrr\n\n"); for (i = 0; i < dev->map_count; i++) { map = dev->maplist[i]; - if (map->type < 0 || map->type > 2) type = "??"; + if (map->type < 0 || map->type > 3) type = "??"; else type = types[map->type]; DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08lx ", i, diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_context.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_context.c new file mode 100644 index 000000000..d146035a8 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_context.c @@ -0,0 +1,212 @@ +/* r128_context.c -- IOCTLs for r128 contexts -*- linux-c -*- + * Created: Mon Dec 13 09:51:35 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * + * $XFree86$ + * + */ + +#include <linux/sched.h> + +#define __NO_VERSION__ +#include "drmP.h" +#include "r128_drv.h" + +extern drm_ctx_t r128_res_ctx; + +static int r128_alloc_queue(drm_device_t *dev) +{ + static int context = 0; + + return drm_ctxbitmap_next(dev); +} + +int r128_context_switch(drm_device_t *dev, int old, int new) +{ + char buf[64]; + + atomic_inc(&dev->total_ctx); + + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } + +#if DRM_DMA_HISTOGRAM + dev->ctx_start = get_cycles(); +#endif + + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } + + if (drm_flags & DRM_FLAG_NOCTX) { + r128_context_switch_complete(dev, new); + } else { + sprintf(buf, "C %d %d\n", old, new); + drm_write_string(dev, buf); + } + + return 0; +} + +int r128_context_switch_complete(drm_device_t *dev, int new) +{ + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; + + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } + + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.ctx[drm_histogram_slot(get_cycles() + - dev->ctx_start)]); + +#endif + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); + + return 0; +} + + +int r128_resctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; + + DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); + copy_from_user_ret(&res, (drm_ctx_res_t *)arg, sizeof(res), -EFAULT); + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + ctx.handle = i; + copy_to_user_ret(&res.contexts[i], + &i, + sizeof(i), + -EFAULT); + } + } + res.count = DRM_RESERVED_CONTEXTS; + copy_to_user_ret((drm_ctx_res_t *)arg, &res, sizeof(res), -EFAULT); + return 0; +} + + +int r128_addctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + if ((ctx.handle = r128_alloc_queue(dev)) == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = r128_alloc_queue(dev); + } + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + + copy_to_user_ret((drm_ctx_t *)arg, &ctx, sizeof(ctx), -EFAULT); + return 0; +} + +int r128_modctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t*)arg, sizeof(ctx), -EFAULT); + if (ctx.flags==_DRM_CONTEXT_PRESERVED) + r128_res_ctx.handle=ctx.handle; + return 0; +} + +int r128_getctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t*)arg, sizeof(ctx), -EFAULT); + /* This is 0, because we don't hanlde any context flags */ + ctx.flags = 0; + copy_to_user_ret((drm_ctx_t*)arg, &ctx, sizeof(ctx), -EFAULT); + return 0; +} + +int r128_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + return r128_context_switch(dev, dev->last_context, ctx.handle); +} + +int r128_newctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + r128_context_switch_complete(dev, ctx.handle); + + return 0; +} + +int r128_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; + + copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); + DRM_DEBUG("%d\n", ctx.handle); + drm_ctxbitmap_free(dev, ctx.handle); + + return 0; +} diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.c new file mode 100644 index 000000000..d477a70d9 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.c @@ -0,0 +1,712 @@ +/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com + * + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * + * $XFree86$ + * + */ + +#define EXPORT_SYMTAB +#include "drmP.h" +#include "r128_drv.h" +EXPORT_SYMBOL(r128_init); +EXPORT_SYMBOL(r128_cleanup); + +#define R128_NAME "r128" +#define R128_DESC "r128" +#define R128_DATE "19991213" +#define R128_MAJOR 0 +#define R128_MINOR 0 +#define R128_PATCHLEVEL 1 + +static drm_device_t r128_device; +drm_ctx_t r128_res_ctx; + +static struct file_operations r128_fops = { + open: r128_open, + flush: drm_flush, + release: r128_release, + ioctl: r128_ioctl, + mmap: drm_mmap, + read: drm_read, + fasync: drm_fasync, + poll: drm_poll, +}; + +static struct miscdevice r128_misc = { + minor: MISC_DYNAMIC_MINOR, + name: R128_NAME, + fops: &r128_fops, +}; + +static drm_ioctl_desc_t r128_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { r128_version, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_busid, 0, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_block, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_unblock, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap, 1, 1 }, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { r128_addctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { r128_rmctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { r128_modctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { r128_getctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { r128_switchctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { r128_newctx, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { r128_resctx, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { r128_lock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { r128_unlock, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, + + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info, 1, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, +}; +#define R128_IOCTL_COUNT DRM_ARRAY_SIZE(r128_ioctls) + +#ifdef MODULE +int init_module(void); +void cleanup_module(void); +static char *r128 = NULL; + +MODULE_AUTHOR("Precision Insight, Inc., Cedar Park, Texas."); +MODULE_DESCRIPTION("r128"); +MODULE_PARM(r128, "s"); + +/* init_module is called when insmod is used to load the module */ + +int init_module(void) +{ + return r128_init(); +} + +/* cleanup_module is called when rmmod is used to unload the module */ + +void cleanup_module(void) +{ + r128_cleanup(); +} +#endif + +#ifndef MODULE +/* r128_setup is called by the kernel to parse command-line options passed + * via the boot-loader (e.g., LILO). It calls the insmod option routine, + * drm_parse_drm. + * + * This is not currently supported, since it requires changes to + * linux/init/main.c. */ + + +void __init r128_setup(char *str, int *ints) +{ + if (ints[0] != 0) { + DRM_ERROR("Illegal command line format, ignored\n"); + return; + } + drm_parse_options(str); +} +#endif + +static int r128_setup(drm_device_t *dev) +{ + int i; + + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); + dev->buf_use = 0; + atomic_set(&dev->buf_alloc, 0); + + atomic_set(&dev->total_open, 0); + atomic_set(&dev->total_close, 0); + atomic_set(&dev->total_ioctl, 0); + atomic_set(&dev->total_irq, 0); + atomic_set(&dev->total_ctx, 0); + atomic_set(&dev->total_locks, 0); + atomic_set(&dev->total_unlocks, 0); + atomic_set(&dev->total_contends, 0); + atomic_set(&dev->total_sleeps, 0); + + for (i = 0; i < DRM_HASH_SIZE; i++) { + dev->magiclist[i].head = NULL; + dev->magiclist[i].tail = NULL; + } + dev->maplist = NULL; + dev->map_count = 0; + dev->vmalist = NULL; + dev->lock.hw_lock = NULL; + init_waitqueue_head(&dev->lock.lock_queue); + dev->queue_count = 0; + dev->queue_reserved = 0; + dev->queue_slots = 0; + dev->queuelist = NULL; + dev->irq = 0; + dev->context_flag = 0; + dev->interrupt_flag = 0; + dev->dma = 0; + dev->dma_flag = 0; + dev->last_context = 0; + dev->last_switch = 0; + dev->last_checked = 0; + init_timer(&dev->timer); + init_waitqueue_head(&dev->context_wait); + + dev->ctx_start = 0; + dev->lck_start = 0; + + dev->buf_rp = dev->buf; + dev->buf_wp = dev->buf; + dev->buf_end = dev->buf + DRM_BSZ; + dev->buf_async = NULL; + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); + + r128_res_ctx.handle=-1; + + DRM_DEBUG("\n"); + + /* The kernel's context could be created here, but is now created + in drm_dma_enqueue. This is more resource-efficient for + hardware that does not do DMA, but may mean that + drm_select_queue fails between the time the interrupt is + initialized and the time the queues are initialized. */ + + return 0; +} + + +static int r128_takedown(drm_device_t *dev) +{ + int i; + drm_magic_entry_t *pt, *next; + drm_map_t *map; + drm_vma_entry_t *vma, *vma_next; + + DRM_DEBUG("\n"); + + down(&dev->struct_sem); + del_timer(&dev->timer); + + if (dev->devname) { + drm_free(dev->devname, strlen(dev->devname)+1, DRM_MEM_DRIVER); + dev->devname = NULL; + } + + if (dev->unique) { + drm_free(dev->unique, strlen(dev->unique)+1, DRM_MEM_DRIVER); + dev->unique = NULL; + dev->unique_len = 0; + } + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { + next = pt->next; + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); + } + dev->magiclist[i].head = dev->magiclist[i].tail = NULL; + } + + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *entry; + drm_agp_mem_t *nexte; + + /* Remove AGP resources, but leave dev->agp + intact until r128_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { + nexte = entry->next; + if (entry->bound) drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); + } + dev->agp->memory = NULL; + + if (dev->agp->acquired && drm_agp.release) + (*drm_agp.release)(); + + dev->agp->acquired = 0; + dev->agp->enabled = 0; + } + + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { + vma_next = vma->next; + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); + } + dev->vmalist = NULL; + } + + /* Clear map area and mtrr information */ + if (dev->maplist) { + for (i = 0; i < dev->map_count; i++) { + map = dev->maplist[i]; + switch (map->type) { + case _DRM_REGISTERS: + case _DRM_FRAME_BUFFER: +#ifdef CONFIG_MTRR + if (map->mtrr >= 0) { + int retcode; + retcode = mtrr_del(map->mtrr, + map->offset, + map->size); + DRM_DEBUG("mtrr_del = %d\n", retcode); + } +#endif + drm_ioremapfree(map->handle, map->size); + break; + case _DRM_SHM: + drm_free_pages((unsigned long)map->handle, + drm_order(map->size) + - PAGE_SHIFT, + DRM_MEM_SAREA); + break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; + } + drm_free(map, sizeof(*map), DRM_MEM_MAPS); + } + drm_free(dev->maplist, + dev->map_count * sizeof(*dev->maplist), + DRM_MEM_MAPS); + dev->maplist = NULL; + dev->map_count = 0; + } + + if (dev->lock.hw_lock) { + dev->lock.hw_lock = NULL; /* SHM removed */ + dev->lock.pid = 0; + wake_up_interruptible(&dev->lock.lock_queue); + } + up(&dev->struct_sem); + + return 0; +} + +/* r128_init is called via init_module at module load time, or via + * linux/init/main.c (this is not currently supported). */ + +int r128_init(void) +{ + int retcode; + drm_device_t *dev = &r128_device; + + DRM_DEBUG("\n"); + + memset((void *)dev, 0, sizeof(*dev)); + dev->count_lock = SPIN_LOCK_UNLOCKED; + sema_init(&dev->struct_sem, 1); + +#ifdef MODULE + drm_parse_options(r128); +#endif + + if ((retcode = misc_register(&r128_misc))) { + DRM_ERROR("Cannot register \"%s\"\n", R128_NAME); + return retcode; + } + dev->device = MKDEV(MISC_MAJOR, r128_misc.minor); + dev->name = R128_NAME; + + drm_mem_init(); + drm_proc_init(dev); + + dev->agp = drm_agp_init(); + +#ifdef CONFIG_MTRR + dev->agp->agp_mtrr = mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size*1024*1024, + MTRR_TYPE_WRCOMB, + 1); +#endif + + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&r128_misc); + r128_takedown(dev); + return retcode; + } + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + R128_NAME, + R128_MAJOR, + R128_MINOR, + R128_PATCHLEVEL, + R128_DATE, + r128_misc.minor); + + return 0; +} + +/* r128_cleanup is called via cleanup_module at module unload time. */ + +void r128_cleanup(void) +{ + drm_device_t *dev = &r128_device; + + DRM_DEBUG("\n"); + + drm_proc_cleanup(); + if (misc_deregister(&r128_misc)) { + DRM_ERROR("Cannot unload module\n"); + } else { + DRM_INFO("Module unloaded\n"); + } + drm_ctxbitmap_cleanup(dev); + r128_takedown(dev); + if (dev->agp) { + /* FIXME -- free other information, too */ + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +} + +int r128_version(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_version_t version; + int len; + + copy_from_user_ret(&version, + (drm_version_t *)arg, + sizeof(version), + -EFAULT); + +#define DRM_COPY(name,value) \ + len = strlen(value); \ + if (len > name##_len) len = name##_len; \ + name##_len = strlen(value); \ + if (len && name) { \ + copy_to_user_ret(name, value, len, -EFAULT); \ + } + + version.version_major = R128_MAJOR; + version.version_minor = R128_MINOR; + version.version_patchlevel = R128_PATCHLEVEL; + + DRM_COPY(version.name, R128_NAME); + DRM_COPY(version.date, R128_DATE); + DRM_COPY(version.desc, R128_DESC); + + copy_to_user_ret((drm_version_t *)arg, + &version, + sizeof(version), + -EFAULT); + return 0; +} + +int r128_open(struct inode *inode, struct file *filp) +{ + drm_device_t *dev = &r128_device; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_open_helper(inode, filp, dev))) { + MOD_INC_USE_COUNT; + atomic_inc(&dev->total_open); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return r128_setup(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +int r128_release(struct inode *inode, struct file *filp) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + + DRM_DEBUG("open_count = %d\n", dev->open_count); + if (!(retcode = drm_release(inode, filp))) { + MOD_DEC_USE_COUNT; + atomic_inc(&dev->total_close); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), + dev->blocked); + spin_unlock(&dev->count_lock); + return -EBUSY; + } + spin_unlock(&dev->count_lock); + return r128_takedown(dev); + } + spin_unlock(&dev->count_lock); + } + return retcode; +} + +/* r128_ioctl is called whenever a process performs an ioctl on /dev/drm. */ + +int r128_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int nr = DRM_IOCTL_NR(cmd); + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + int retcode = 0; + drm_ioctl_desc_t *ioctl; + drm_ioctl_t *func; + + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->total_ioctl); + ++priv->ioctl_count; + + DRM_DEBUG("pid = %d, cmd = 0x%02x, nr = 0x%02x, dev 0x%x, auth = %d\n", + current->pid, cmd, nr, dev->device, priv->authenticated); + + if (nr >= R128_IOCTL_COUNT) { + retcode = -EINVAL; + } else { + ioctl = &r128_ioctls[nr]; + func = ioctl->func; + + if (!func) { + DRM_DEBUG("no function\n"); + retcode = -EINVAL; + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) + || (ioctl->auth_needed && !priv->authenticated)) { + retcode = -EACCES; + } else { + retcode = (func)(inode, filp, cmd, arg); + } + } + + atomic_dec(&dev->ioctl_count); + return retcode; +} + +int r128_lock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + DECLARE_WAITQUEUE(entry, current); + int ret = 0; + drm_lock_t lock; +#if DRM_DMA_HISTOGRAM + cycles_t start; + + dev->lck_start = start = get_cycles(); +#endif + + copy_from_user_ret(&lock, (drm_lock_t *)arg, sizeof(lock), -EFAULT); + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, dev->lock.hw_lock->lock, + lock.flags); + +#if 0 + /* dev->queue_count == 0 right now for + r128. FIXME? */ + if (lock.context < 0 || lock.context >= dev->queue_count) + return -EINVAL; +#endif + + if (!ret) { +#if 0 + if (_DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) + != lock.context) { + long j = jiffies - dev->lock.lock_time; + + if (lock.context == r128_res_ctx.handle && + j >= 0 && j < DRM_LOCK_SLICE) { + /* Can't take lock if we just had it and + there is contention. */ + DRM_DEBUG("%d (pid %d) delayed j=%d dev=%d jiffies=%d\n", + lock.context, current->pid, j, + dev->lock.lock_time, jiffies); + current->state = TASK_INTERRUPTIBLE; + current->policy |= SCHED_YIELD; + schedule_timeout(DRM_LOCK_SLICE-j); + DRM_DEBUG("jiffies=%d\n", jiffies); + } + } +#endif + add_wait_queue(&dev->lock.lock_queue, &entry); + for (;;) { + if (!dev->lock.hw_lock) { + /* Device has been unregistered */ + ret = -EINTR; + break; + } + if (drm_lock_take(&dev->lock.hw_lock->lock, + lock.context)) { + dev->lock.pid = current->pid; + dev->lock.lock_time = jiffies; + atomic_inc(&dev->total_locks); + break; /* Got lock */ + } + + /* Contention */ + atomic_inc(&dev->total_sleeps); + current->state = TASK_INTERRUPTIBLE; +#if 1 + current->policy |= SCHED_YIELD; +#endif + schedule(); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + current->state = TASK_RUNNING; + remove_wait_queue(&dev->lock.lock_queue, &entry); + } + +#if 0 + if (!ret && dev->last_context != lock.context && + lock.context != r128_res_ctx.handle && + dev->last_context != r128_res_ctx.handle) { + add_wait_queue(&dev->context_wait, &entry); + current->state = TASK_INTERRUPTIBLE; + /* PRE: dev->last_context != lock.context */ + r128_context_switch(dev, dev->last_context, lock.context); + /* POST: we will wait for the context + switch and will dispatch on a later call + when dev->last_context == lock.context + NOTE WE HOLD THE LOCK THROUGHOUT THIS + TIME! */ + current->policy |= SCHED_YIELD; + schedule(); + current->state = TASK_RUNNING; + remove_wait_queue(&dev->context_wait, &entry); + if (signal_pending(current)) { + ret = -EINTR; + } else if (dev->last_context != lock.context) { + DRM_ERROR("Context mismatch: %d %d\n", + dev->last_context, lock.context); + } + } +#endif + + if (!ret) { + if (lock.flags & _DRM_LOCK_READY) { + /* Wait for space in DMA/FIFO */ + } + if (lock.flags & _DRM_LOCK_QUIESCENT) { + /* Make hardware quiescent */ +#if 0 + r128_quiescent(dev); +#endif + } + } + +#if 0 + DRM_ERROR("pid = %5d, old counter = %5ld\n", + current->pid, current->counter); +#endif + if (lock.context != r128_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY/4; + } +#if 0 + while (current->counter > 25) + current->counter >>= 1; /* decrease time slice */ + DRM_ERROR("pid = %5d, new counter = %5ld\n", + current->pid, current->counter); +#endif + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); + +#if DRM_DMA_HISTOGRAM + atomic_inc(&dev->histo.lacq[drm_histogram_slot(get_cycles() - start)]); +#endif + + return ret; +} + + +int r128_unlock(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) +{ + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_lock_t lock; + + copy_from_user_ret(&lock, (drm_lock_t *)arg, sizeof(lock), -EFAULT); + + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } + + DRM_DEBUG("%d frees lock (%d holds)\n", + lock.context, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); + atomic_inc(&dev->total_unlocks); + if (_DRM_LOCK_IS_CONT(dev->lock.hw_lock->lock)) + atomic_inc(&dev->total_contends); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT); + /* FIXME: Try to send data to card here */ + if (!dev->context_flag) { + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); + } + } + +#if 0 + current->policy |= SCHED_YIELD; + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(1000); +#endif + + if (lock.context != r128_res_ctx.handle) { + current->counter = 5; + current->priority = DEF_PRIORITY; + } +#if 0 + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(10); +#endif + + return 0; +} diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.h b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.h new file mode 100644 index 000000000..c1faf7646 --- /dev/null +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/r128_drv.h @@ -0,0 +1,68 @@ +/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- + * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * + * $XFree86$ + * + */ + +#ifndef _R128_DRV_H_ +#define _R128_DRV_H_ + + /* r128_drv.c */ +extern int r128_init(void); +extern void r128_cleanup(void); +extern int r128_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_open(struct inode *inode, struct file *filp); +extern int r128_release(struct inode *inode, struct file *filp); +extern int r128_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + + /* r128_context.c */ + +extern int r128_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int r128_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int r128_context_switch(drm_device_t *dev, int old, int new); +extern int r128_context_switch_complete(drm_device_t *dev, int new); +#endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_context.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_context.c index 842d6f5d5..74b107bd2 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_context.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_context.c @@ -38,9 +38,7 @@ extern drm_ctx_t tdfx_res_ctx; static int tdfx_alloc_queue(drm_device_t *dev) { - static int context = 0; - - return ++context; /* Should this reuse contexts in the future? */ + return drm_ctxbitmap_next(dev); } int tdfx_context_switch(drm_device_t *dev, int old, int new) @@ -137,6 +135,12 @@ int tdfx_addctx(struct inode *inode, struct file *filp, unsigned int cmd, ctx.handle = tdfx_alloc_queue(dev); } DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ + return -ENOMEM; + } + copy_to_user_ret((drm_ctx_t *)arg, &ctx, sizeof(ctx), -EFAULT); return 0; } @@ -193,13 +197,13 @@ int tdfx_newctx(struct inode *inode, struct file *filp, unsigned int cmd, int tdfx_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; drm_ctx_t ctx; copy_from_user_ret(&ctx, (drm_ctx_t *)arg, sizeof(ctx), -EFAULT); DRM_DEBUG("%d\n", ctx.handle); - /* This is currently a noop because we - don't reuse context values. Perhaps we - should? */ - + drm_ctxbitmap_free(dev, ctx.handle); + return 0; } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_drv.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_drv.c index 57c1c719d..fb7a997b4 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_drv.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/tdfx_drv.c @@ -85,6 +85,16 @@ static drm_ioctl_desc_t tdfx_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { tdfx_lock, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { tdfx_unlock, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_finish, 1, 0 }, +#ifdef DRM_AGP + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_unbind, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_bind, 1, 1}, +#endif }; #define TDFX_IOCTL_COUNT DRM_ARRAY_SIZE(tdfx_ioctls) @@ -228,7 +238,24 @@ static int tdfx_takedown(drm_device_t *dev) } dev->magiclist[i].head = dev->magiclist[i].tail = NULL; } - +#ifdef DRM_AGP + /* Clear AGP information */ + if (dev->agp) { + drm_agp_mem_t *temp; + drm_agp_mem_t *temp_next; + + temp = dev->agp->memory; + while(temp != NULL) { + temp_next = temp->next; + drm_free_agp(temp->memory, temp->pages); + drm_free(temp, sizeof(*temp), DRM_MEM_AGPLISTS); + temp = temp_next; + } + if(dev->agp->acquired) (*drm_agp.release)(); + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); + dev->agp = NULL; + } +#endif /* Clear vma list (only built for debugging) */ if (dev->vmalist) { for (vma = dev->vmalist; vma; vma = vma_next) { @@ -262,6 +289,10 @@ static int tdfx_takedown(drm_device_t *dev) - PAGE_SHIFT, DRM_MEM_SAREA); break; + case _DRM_AGP: + /* Do nothing here, because this is all + handled in the AGP/GART driver. */ + break; } drm_free(map, sizeof(*map), DRM_MEM_MAPS); } @@ -309,6 +340,16 @@ int tdfx_init(void) drm_mem_init(); drm_proc_init(dev); +#ifdef DRM_AGP + dev->agp = drm_agp_init(); +#endif + if((retcode = drm_ctxbitmap_init(dev))) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); + drm_proc_cleanup(); + misc_deregister(&tdfx_misc); + tdfx_takedown(dev); + return retcode; + } DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", TDFX_NAME, @@ -335,6 +376,7 @@ void tdfx_cleanup(void) } else { DRM_INFO("Module unloaded\n"); } + drm_ctxbitmap_cleanup(dev); tdfx_takedown(dev); } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/vm.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/vm.c index 85470ac52..389f2faee 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/vm.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/vm.c @@ -250,9 +250,10 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) switch (map->type) { case _DRM_FRAME_BUFFER: case _DRM_REGISTERS: + case _DRM_AGP: if (VM_OFFSET(vma) >= __pa(high_memory)) { #if defined(__i386__) - if (boot_cpu_data.x86 > 3) { + if (boot_cpu_data.x86 > 3 && map->type != _DRM_AGP) { pgprot_val(vma->vm_page_prot) |= _PAGE_PCD; pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; } diff --git a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c index 3b0f98acd..ae81192bf 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c +++ b/xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c @@ -1,8 +1,7 @@ /* xf86drm.c -- User-level interface to DRM device * Created: Tue Jan 5 08:16:21 1999 by faith@precisioninsight.com - * Revised: Sun Feb 13 23:43:32 2000 by kevin@precisioninsight.com * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +23,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c,v 1.10 2000/02/23 04:47:23 martin Exp $ * */ @@ -143,7 +144,7 @@ static int drm_open(const char *file) return -errno; } -/* drmAvailable looks for /proc/drm, and returns 1 if it is present. */ +/* drmAvailable looks for /proc/dri, and returns 1 if it is present. */ int drmAvailable(void) { @@ -418,7 +419,8 @@ int drmAddMap(int fd, return 0; } -int drmAddBufs(int fd, int count, int size, int flags) +int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags, + int agp_offset) { drm_buf_desc_t request; @@ -427,6 +429,8 @@ int drmAddBufs(int fd, int count, int size, int flags) request.low_mark = 0; request.high_mark = 0; request.flags = flags; + request.agp_start = agp_offset; + if (ioctl(fd, DRM_IOCTL_ADD_BUFS, &request)) return -errno; return request.count; } @@ -744,6 +748,143 @@ int drmDestroyDrawable(int fd, drmDrawable handle) return 0; } +int drmAgpAcquire(int fd) +{ + if (ioctl(fd, DRM_IOCTL_AGP_ACQUIRE, NULL)) return -errno; + return 0; +} + +int drmAgpRelease(int fd) +{ + if (ioctl(fd, DRM_IOCTL_AGP_RELEASE, NULL)) return -errno; + return 0; +} + +int drmAgpEnable(int fd, unsigned long mode) +{ + drm_agp_mode_t m; + + m.mode = mode; + if (ioctl(fd, DRM_IOCTL_AGP_ENABLE, &m)) return -errno; + return 0; +} + +int drmAgpAlloc(int fd, unsigned long size, unsigned long type, + unsigned long *address, unsigned long *handle) +{ + drm_agp_buffer_t b; + *handle = 0; + b.size = size; + b.handle = 0; + b.type = type; + if (ioctl(fd, DRM_IOCTL_AGP_ALLOC, &b)) return -errno; + if (address != 0UL) *address = b.physical; + *handle = b.handle; + return 0; +} + +int drmAgpFree(int fd, unsigned long handle) +{ + drm_agp_buffer_t b; + + b.size = 0; + b.handle = handle; + if (ioctl(fd, DRM_IOCTL_AGP_FREE, &b)) return -errno; + return 0; +} + +int drmAgpBind(int fd, unsigned long handle, unsigned long offset) +{ + drm_agp_binding_t b; + + b.handle = handle; + b.offset = offset; + if (ioctl(fd, DRM_IOCTL_AGP_BIND, &b)) return -errno; + return 0; +} + +int drmAgpUnbind(int fd, unsigned long handle) +{ + drm_agp_binding_t b; + + b.handle = handle; + b.offset = 0; + if (ioctl(fd, DRM_IOCTL_AGP_UNBIND, &b)) return -errno; + return 0; +} + +int drmAgpVersionMajor(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.agp_version_major; +} + +int drmAgpVersionMinor(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return -errno; + return i.agp_version_minor; +} + +unsigned long drmAgpGetMode(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.mode; +} + +unsigned long drmAgpBase(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.aperture_base; +} + +unsigned long drmAgpSize(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.aperture_size; +} + +unsigned long drmAgpMemoryUsed(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.memory_used; +} + +unsigned long drmAgpMemoryAvail(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.memory_allowed; +} + +unsigned int drmAgpVendorId(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.id_vendor; +} + +unsigned int drmAgpDeviceId(int fd) +{ + drm_agp_info_t i; + + if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0; + return i.id_device; +} + int drmError(int err, const char *label) { switch (err) { diff --git a/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/drm.h b/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/drm.h index 7b8e88265..ebc6f7e79 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/drm.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/drm.h @@ -101,7 +101,8 @@ typedef struct drm_control { typedef enum drm_map_type { _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */ _DRM_REGISTERS = 1, /* no caching, no core dump */ - _DRM_SHM = 2 /* shared, cached */ + _DRM_SHM = 2, /* shared, cached */ + _DRM_AGP = 3 /* AGP/GART */ } drm_map_type_t; typedef enum drm_map_flags { @@ -165,8 +166,11 @@ typedef struct drm_buf_desc { int low_mark; /* Low water mark */ int high_mark; /* High water mark */ enum { - DRM_PAGE_ALIGN = 0x01 /* Align on page boundaries for DMA */ + _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */ } flags; + unsigned long agp_start; /* Start address of where the agp buffers + * are in the agp aperture */ } drm_buf_desc_t; typedef struct drm_buf_info { @@ -237,6 +241,38 @@ typedef struct drm_irq_busid { int funcnum; } drm_irq_busid_t; +typedef struct drm_agp_mode { + unsigned long mode; +} drm_agp_mode_t; + + /* For drm_agp_alloc -- allocated a buffer */ +typedef struct drm_agp_buffer { + unsigned long size; /* In bytes -- will round to page boundary */ + unsigned long handle; /* Used for BIND/UNBIND ioctls */ + unsigned long type; /* Type of memory to allocate */ + unsigned long physical; /* Physical used by i810 */ +} drm_agp_buffer_t; + + /* For drm_agp_bind */ +typedef struct drm_agp_binding { + unsigned long handle; /* From drm_agp_buffer */ + unsigned long offset; /* In bytes -- will round to page boundary */ +} drm_agp_binding_t; + +typedef struct drm_agp_info { + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ + unsigned short id_vendor; + unsigned short id_device; +} drm_agp_info_t; + #define DRM_IOCTL_BASE 'd' #define DRM_IOCTL_NR(n) _IOC_NR(n) #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) @@ -276,4 +312,14 @@ typedef struct drm_irq_busid { #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) +#define DRM_IOCTL_AGP_ENABLE DRM_IOR( 0x32, drm_agp_mode_t) +#define DRM_IOCTL_AGP_INFO DRM_IOW( 0x33, drm_agp_info_t) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) +#define DRM_IOCTL_AGP_BIND DRM_IOWR(0x36, drm_agp_binding_t) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) + +/* 0x40 is reserved for mga dma init */ #endif diff --git a/xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h b/xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h index 61287e3e2..372ba595e 100644 --- a/xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h +++ b/xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h @@ -1,8 +1,7 @@ /* xf86drm.h -- OS-independent header for DRM user-level library interface * Created: Tue Jan 5 08:17:23 1999 by faith@precisioninsight.com - * Revised: Sun Feb 13 23:46:21 2000 by kevin@precisioninsight.com * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +23,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * + * Author: Rickard E. (Rik) Faith <faith@precisioninsight.com> + * * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h,v 1.7 2000/02/23 04:47:21 martin Exp $ * */ @@ -65,7 +66,8 @@ typedef struct _drmVersion { typedef enum { DRM_FRAME_BUFFER = 0, /* WC, no caching, no core dump */ DRM_REGISTERS = 1, /* no caching, no core dump */ - DRM_SHM = 2 /* shared, cached */ + DRM_SHM = 2, /* shared, cached */ + DRM_AGP = 3 /* AGP/GART */ } drmMapType; typedef enum { @@ -95,6 +97,11 @@ typedef enum { /* These values *MUST* match drm.h */ } drmDMAFlags; typedef enum { + DRM_PAGE_ALIGN = 0x01, + DRM_AGP_BUFFER = 0x02 +} drmBufDescFlags; + +typedef enum { DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */ DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */ DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */ @@ -196,7 +203,7 @@ typedef struct { unsigned int a[100]; } __drm_dummy_lock_t; #endif #ifndef DRM_CAS -#define DRM_CAS(lock,old,new,ret) /* FAST LOCK FAILS */ +#define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ #endif #define DRM_LIGHT_LOCK(fd,lock,context) \ @@ -291,7 +298,9 @@ extern int drmAddMap(int fd, drmMapType type, drmMapFlags flags, drmHandlePtr handle); -extern int drmAddBufs(int fd, int count, int size, int flags); +extern int drmAddBufs(int fd, int count, int size, + drmBufDescFlags flags, + int agp_offset); extern int drmMarkBufs(int fd, double low, double high); extern int drmCreateContext(int fd, drmContextPtr handle); extern int drmSetContextFlags(int fd, drmContext context, @@ -332,6 +341,29 @@ extern int drmGetLock(int fd, extern int drmUnlock(int fd, drmContext context); extern int drmFinish(int fd, int context, drmLockFlags flags); +/* AGP/GART support: X server (root) only */ +extern int drmAgpAcquire(int fd); +extern int drmAgpRelease(int fd); +extern int drmAgpEnable(int fd, unsigned long mode); +extern int drmAgpAlloc(int fd, unsigned long size, + unsigned long type, unsigned long *address, + unsigned long *handle); +extern int drmAgpFree(int fd, unsigned long handle); +extern int drmAgpBind(int fd, unsigned long handle, + unsigned long offset); +extern int drmAgpUnbind(int fd, unsigned long handle); + +/* AGP/GART info: authenticated client and/or X */ +extern int drmAgpVersionMajor(int fd); +extern int drmAgpVersionMinor(int fd); +extern unsigned long drmAgpGetMode(int fd); +extern unsigned long drmAgpBase(int fd); /* Physical location */ +extern unsigned long drmAgpSize(int fd); /* Bytes */ +extern unsigned long drmAgpMemoryUsed(int fd); +extern unsigned long drmAgpMemoryAvail(int fd); +extern unsigned int drmAgpVendorId(int fd); +extern unsigned int drmAgpDeviceId(int fd); + /* Support routines */ extern int drmError(int err, const char *label); extern void *drmMalloc(int size); |