diff options
author | Vladimir Dergachev <volodya@freedesktop.org> | 2004-12-30 16:06:37 +0000 |
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committer | Vladimir Dergachev <volodya@freedesktop.org> | 2004-12-30 16:06:37 +0000 |
commit | 4a04f002dbc1c39059216dfad4be3d6c874c5408 (patch) | |
tree | 4829986d16423bd46bc87c101397d0927e460ddb | |
parent | 8f1ba083baa14182d508cdb9f94e2e41726984e9 (diff) |
Add missing files.shimmering_gears
-rw-r--r-- | src/mesa/drivers/dri/r300/pixel_shader.h | 94 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/vertex_shader.h | 90 |
2 files changed, 184 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r300/pixel_shader.h b/src/mesa/drivers/dri/r300/pixel_shader.h new file mode 100644 index 00000000000..07c84497340 --- /dev/null +++ b/src/mesa/drivers/dri/r300/pixel_shader.h @@ -0,0 +1,94 @@ +#ifndef __PIXEL_SHADER_H__ +#define __PIXEL_SHADER_H__ + +#include "r300_reg.h" + + +/* INSTR 0 */ + +#define PFS_OP_MAD 0 +#define PFS_OP_DP3 1 +#define PFS_OP_DP4 2 +#define PFS_OP_MIN 4 +#define PFS_OP_MAX 5 +#define PFS_OP_CMP 8 +#define PFS_OP_FRC 9 +#define PFS_OP_OUTC_REPL_ALPHA 10 + +/* "or" these with arg0 value to negate or take absolute value of an argument */ +#define PFS_ARG_NEG (1<<5) +#define PFS_ARG_ABS (1<<6) + +#define MAKE_PFS_INSTR0(op, arg0, arg1, arg2, flags) \ + ( ((op)<<23) \ + | ((arg0)<<R300_FPI0_ARG0C_SHIFT) \ + | ((arg1)<<R300_FPI0_ARG1C_SHIFT) \ + | ((arg2)<<R300_FPI0_ARG2C_SHIFT) \ + | (flags) \ + ) + +#define PFS_FLAG_X 1 +#define PFS_FLAG_Y 2 +#define PFS_FLAG_XY 3 +#define PFS_FLAG_Z 4 +#define PFS_FLAG_XZ 5 +#define PFS_FLAG_YZ 6 +#define PFS_FLAG_ALL 7 +#define PFS_FLAG_NONE 0 + +#define EASY_PFS_INSTR0(op, arg0, arg1, arg2) \ + MAKE_PFS_INSTR0(PFS_OP_##op, \ + R300_FPI0_ARGC_##arg0, \ + R300_FPI0_ARGC_##arg1, \ + R300_FPI0_ARGC_##arg2, \ + 0) + +/* INSTR 1 */ + +#define PFS_FLAG_CONST (1<<5) + +#define MAKE_PFS_INSTR1(dstc, src0, src1, src2, reg, output) \ + ((src0) | ((src1) << R300_FPI1_SRC1C_SHIFT) \ + | ((src2)<<R300_FPI1_SRC2C_SHIFT) \ + | ((dstc) << R300_FPI1_DSTC_SHIFT) \ + | ((reg) << 23) | ((output)<<26)) + +#define EASY_PFS_INSTR1(dstc, src0, src1, src2, reg, output) \ + MAKE_PFS_INSTR1(dstc, src0, src1, src2, PFS_FLAG_##reg, PFS_FLAG_##output) + +/* INSTR 2 */ + +/* you can "or" PFS_ARG_NEG with these values to negate them */ + +#define MAKE_PFS_INSTR2(op, arg0, arg1, arg2, flags) \ + (((op) << 23) | \ + ((arg0)<<R300_FPI2_ARG0A_SHIFT) | \ + ((arg1)<<R300_FPI2_ARG1A_SHIFT) | \ + ((arg2)<<R300_FPI2_ARG2A_SHIFT) | \ + (flags)) + +#define EASY_PFS_INSTR2(op, arg0, arg1, arg2) \ + MAKE_PFS_INSTR2(R300_FPI2_OUTA_##op, \ + R300_FPI2_ARGA_##arg0, \ + R300_FPI2_ARGA_##arg1, \ + R300_FPI2_ARGA_##arg2, \ + 0) + + +/* INSTR 3 */ + +#define PFS_FLAG_NONE 0 +#define PFS_FLAG_REG 1 +#define PFS_FLAG_OUTPUT 2 +#define PFS_FLAG_BOTH 3 + +#define MAKE_PFS_INSTR3(dstc, src0, src1, src2, flags) \ + ((src0) | ((src1) << R300_FPI1_SRC1C_SHIFT) \ + | ((src2)<<R300_FPI1_SRC2C_SHIFT) \ + | ((dstc) << R300_FPI1_DSTC_SHIFT) \ + | ((flags) << 23)) + +#define EASY_PFS_INSTR3(dstc, src0, src1, src2, flag) \ + MAKE_PFS_INSTR3(dstc, src0, src1, src2, PFS_FLAG_##flag) + +#endif diff --git a/src/mesa/drivers/dri/r300/vertex_shader.h b/src/mesa/drivers/dri/r300/vertex_shader.h new file mode 100644 index 00000000000..e756aaa343f --- /dev/null +++ b/src/mesa/drivers/dri/r300/vertex_shader.h @@ -0,0 +1,90 @@ +#ifndef __VERTEX_SHADER_H__ +#define __VERTEX_SHADER_H__ + +#include "r300_reg.h" + +typedef struct { + CARD32 op; + CARD32 src1; + CARD32 src2; + CARD32 src3; + } VERTEX_SHADER_INSTRUCTION; + +#define VSF_FLAG_X 1 +#define VSF_FLAG_Y 2 +#define VSF_FLAG_Z 4 +#define VSF_FLAG_W 8 +#define VSF_FLAG_ALL 0xf +#define VSF_FLAG_NONE 0 + +#define VSF_OUT_CLASS_TMP 0 +#define VSF_OUT_CLASS_RESULT 2 + + +/* first CARD32 of an instruction */ + +/* possible operations: + DOT, MUL, ADD, MAD, FRC, MAX, MIN, SGE, SLT, EXP, LOG, LIT, POW, RCP, RSQ, EX2, + LG2, MAD_2 */ + +#define MAKE_VSF_OP(op, out_reg_index, out_reg_fields, class) \ + ((op) \ + | ((out_reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT) \ + | ((out_reg_fields) << 20) \ + | ( (class) << 8 ) ) + +#define EASY_VSF_OP(op, out_reg_index, out_reg_fields, class) \ + MAKE_VSF_OP(R300_VPI_OUT_OP_##op, out_reg_index, VSF_FLAG_##out_reg_fields, VSF_OUT_CLASS_##class) \ + +/* according to Nikolai, the subsequent 3 CARD32 are sources, use same define for each */ + +#define VSF_IN_CLASS_TMP 0 +#define VSF_IN_CLASS_ATTR 1 +#define VSF_IN_CLASS_PARAM 2 +#define VSF_IN_CLASS_NONE 9 + +#define VSF_IN_COMPONENT_X 0 +#define VSF_IN_COMPONENT_Y 1 +#define VSF_IN_COMPONENT_Z 2 +#define VSF_IN_COMPONENT_W 3 +#define VSF_IN_COMPONENT_ZERO 4 +#define VSF_IN_COMPONENT_ONE 5 + +#define MAKE_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \ + ( ((in_reg_index)<<R300_VPI_IN_REG_INDEX_SHIFT) \ + | ((comp_x)<<R300_VPI_IN_X_SHIFT) \ + | ((comp_y)<<R300_VPI_IN_Y_SHIFT) \ + | ((comp_z)<<R300_VPI_IN_Z_SHIFT) \ + | ((comp_w)<<R300_VPI_IN_W_SHIFT) \ + | ((negate)<<25) | ((class))) + +#define EASY_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \ + MAKE_VSF_SOURCE(in_reg_index, \ + VSF_IN_COMPONENT_##comp_x, \ + VSF_IN_COMPONENT_##comp_y, \ + VSF_IN_COMPONENT_##comp_z, \ + VSF_IN_COMPONENT_##comp_w, \ + VSF_IN_CLASS_##class, VSF_FLAG_##negate) + +/* special sources: */ + +/* (1.0,1.0,1.0,1.0) vector (ATTR, plain ) */ +#define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE) +#define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE) + +/* contents of unmodified register */ +#define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE) + +/* contents of unmodified parameter */ +#define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE) + +/* contents of unmodified temporary register */ +#define VSF_TMP(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, TMP, NONE) + +/* components of ATTR register */ +#define VSF_ATTR_X(reg) EASY_VSF_SOURCE(reg, X, X, X, X, ATTR, NONE) +#define VSF_ATTR_Y(reg) EASY_VSF_SOURCE(reg, Y, Y, Y, Y, ATTR, NONE) +#define VSF_ATTR_Z(reg) EASY_VSF_SOURCE(reg, Z, Z, Z, Z, ATTR, NONE) +#define VSF_ATTR_W(reg) EASY_VSF_SOURCE(reg, W, W, W, W, ATTR, NONE) + +#endif |